EP0851468A3 - Verfahren zur Herstellung einer integrierten Schaltung mit doppelter Wanne - Google Patents

Verfahren zur Herstellung einer integrierten Schaltung mit doppelter Wanne Download PDF

Info

Publication number
EP0851468A3
EP0851468A3 EP97310164A EP97310164A EP0851468A3 EP 0851468 A3 EP0851468 A3 EP 0851468A3 EP 97310164 A EP97310164 A EP 97310164A EP 97310164 A EP97310164 A EP 97310164A EP 0851468 A3 EP0851468 A3 EP 0851468A3
Authority
EP
European Patent Office
Prior art keywords
integrated circuit
region
photoresist
twin
making integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97310164A
Other languages
English (en)
French (fr)
Other versions
EP0851468A2 (de
Inventor
Sailesh Chittipeddi
Stephen Knight
William Thomas Cochran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia of America Corp
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Publication of EP0851468A2 publication Critical patent/EP0851468A2/de
Publication of EP0851468A3 publication Critical patent/EP0851468A3/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
EP97310164A 1996-12-31 1997-12-16 Verfahren zur Herstellung einer integrierten Schaltung mit doppelter Wanne Withdrawn EP0851468A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/775,490 US6017787A (en) 1996-12-31 1996-12-31 Integrated circuit with twin tub
US775490 1996-12-31

Publications (2)

Publication Number Publication Date
EP0851468A2 EP0851468A2 (de) 1998-07-01
EP0851468A3 true EP0851468A3 (de) 1998-08-05

Family

ID=25104593

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97310164A Withdrawn EP0851468A3 (de) 1996-12-31 1997-12-16 Verfahren zur Herstellung einer integrierten Schaltung mit doppelter Wanne

Country Status (5)

Country Link
US (1) US6017787A (de)
EP (1) EP0851468A3 (de)
JP (1) JP3253908B2 (de)
KR (1) KR100554648B1 (de)
TW (1) TW410438B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566181B2 (en) * 1999-02-26 2003-05-20 Agere Systems Inc. Process for the fabrication of dual gate structures for CMOS devices
US6391700B1 (en) * 2000-10-17 2002-05-21 United Microelectronics Corp. Method for forming twin-well regions of semiconductor devices
US6518107B2 (en) * 2001-02-16 2003-02-11 Advanced Micro Devices, Inc. Non-arsenic N-type dopant implantation for improved source/drain interfaces with nickel silicides
US7825488B2 (en) 2006-05-31 2010-11-02 Advanced Analogic Technologies, Inc. Isolation structures for integrated circuits and modular methods of forming the same
US6900091B2 (en) * 2002-08-14 2005-05-31 Advanced Analogic Technologies, Inc. Isolated complementary MOS devices in epi-less substrate
US6855985B2 (en) * 2002-09-29 2005-02-15 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
KR100697289B1 (ko) * 2005-08-10 2007-03-20 삼성전자주식회사 반도체 장치의 형성 방법
US7407851B2 (en) * 2006-03-22 2008-08-05 Miller Gayle W DMOS device with sealed channel processing
JP2007273588A (ja) * 2006-03-30 2007-10-18 Fujitsu Ltd 半導体装置の製造方法
JP6216142B2 (ja) * 2012-05-28 2017-10-18 キヤノン株式会社 半導体装置の製造方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5613722A (en) * 1979-07-13 1981-02-10 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US4584027A (en) * 1984-11-07 1986-04-22 Ncr Corporation Twin well single mask CMOS process
EP0181501A2 (de) * 1984-10-18 1986-05-21 Matsushita Electronics Corporation Verfahren zur Herstellung einer integrierten komplementären MOS-Schaltung
JPH0483335A (ja) * 1990-07-25 1992-03-17 Fujitsu Ltd 半導体装置の製造方法
EP0564191A2 (de) * 1992-03-31 1993-10-06 STMicroelectronics, Inc. Struktur und Verfahren zur Herstellung von integrierten Schaltungen
JPH0745713A (ja) * 1993-07-29 1995-02-14 Kawasaki Steel Corp 半導体装置の製造方法
US5670395A (en) * 1996-04-29 1997-09-23 Chartered Semiconductor Manufacturing Pte. Ltd. Process for self-aligned twin wells without N-well and P-well height difference

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435896A (en) * 1981-12-07 1984-03-13 Bell Telephone Laboratories, Incorporated Method for fabricating complementary field effect transistor devices
US4558508A (en) * 1984-10-15 1985-12-17 International Business Machines Corporation Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step
US5141882A (en) * 1989-04-05 1992-08-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor field effect device having channel stop and channel region formed in a well and manufacturing method therefor
JPH081930B2 (ja) * 1989-09-11 1996-01-10 株式会社東芝 半導体装置の製造方法
US5217570A (en) * 1991-01-31 1993-06-08 Sony Corporation Dry etching method
JP2978345B2 (ja) * 1992-11-26 1999-11-15 三菱電機株式会社 半導体装置の製造方法
JP3391410B2 (ja) * 1993-09-17 2003-03-31 富士通株式会社 レジストマスクの除去方法
US5413944A (en) * 1994-05-06 1995-05-09 United Microelectronics Corporation Twin tub CMOS process
US5422312A (en) * 1994-06-06 1995-06-06 United Microelectronics Corp. Method for forming metal via
US5573963A (en) * 1995-05-03 1996-11-12 Vanguard International Semiconductor Corporation Method of forming self-aligned twin tub CMOS devices
US5573962A (en) * 1995-12-15 1996-11-12 Vanguard International Semiconductor Corporation Low cycle time CMOS process

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5613722A (en) * 1979-07-13 1981-02-10 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
EP0181501A2 (de) * 1984-10-18 1986-05-21 Matsushita Electronics Corporation Verfahren zur Herstellung einer integrierten komplementären MOS-Schaltung
US4584027A (en) * 1984-11-07 1986-04-22 Ncr Corporation Twin well single mask CMOS process
JPH0483335A (ja) * 1990-07-25 1992-03-17 Fujitsu Ltd 半導体装置の製造方法
EP0564191A2 (de) * 1992-03-31 1993-10-06 STMicroelectronics, Inc. Struktur und Verfahren zur Herstellung von integrierten Schaltungen
JPH0745713A (ja) * 1993-07-29 1995-02-14 Kawasaki Steel Corp 半導体装置の製造方法
US5670395A (en) * 1996-04-29 1997-09-23 Chartered Semiconductor Manufacturing Pte. Ltd. Process for self-aligned twin wells without N-well and P-well height difference

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 005, no. 063 (E - 054) 28 April 1981 (1981-04-28) *
PATENT ABSTRACTS OF JAPAN vol. 016, no. 303 (E - 1228) 3 July 1992 (1992-07-03) *
PATENT ABSTRACTS OF JAPAN vol. 095, no. 005 30 June 1995 (1995-06-30) *

Also Published As

Publication number Publication date
KR19980064838A (ko) 1998-10-07
EP0851468A2 (de) 1998-07-01
JPH10209297A (ja) 1998-08-07
US6017787A (en) 2000-01-25
JP3253908B2 (ja) 2002-02-04
KR100554648B1 (ko) 2006-04-21
TW410438B (en) 2000-11-01

Similar Documents

Publication Publication Date Title
ATE124168T1 (de) Silicium substituiert mit kohlenstoff.
EP0715344A3 (de) Verfahren zur Bildung von Gatteroxyden mit verschiedener Dicke auf einem Halbleitersubstrat
TW257875B (en) Method of forming miniature pattern
EP0628992A3 (de) Verfahren zur Herstellung von halbleitenden Wafern.
MY118631A (en) A method for forming self-aligned features
TW366527B (en) A method of producing a thin layer of semiconductor material
EP0851492A3 (de) Substratstruktur zur Oberflächenmontage und Methode
TW371789B (en) Method for fabricating a semiconductor device
EP0289163A3 (de) Silicid-Halbleiterelement mit Polysilizium-Bereiche und Verfahren zur seiner Herstellung
EP0404464A3 (de) Herstellen von Halbleitervorrichtungen
EP0851468A3 (de) Verfahren zur Herstellung einer integrierten Schaltung mit doppelter Wanne
EP0738006A3 (de) Verfahren zur Herstellung einer Halbleitergrabenkondensatorzelle
EP0797245A3 (de) Verfahren zur Herstellung von einem vertikalen MOS-Halbleiterbauelement
EP0928018A3 (de) Veringerung von schwarzem Silizium bei der Halbeiterproduktion
GB2227880B (en) Method of fabricating a submicron silicon gate mosfet which has a self-aligned threshold implant
EP0562309A3 (de) Planares Verfahren unter Verwendung von gemeinsamen Ausrichtungsmarken für die Wannenimplantierungen
TW368727B (en) Manufacturing method for shallow trench isolation structure
JPS6467955A (en) Manufacture of implanted well and island of cmos integrated circuit
EP1047118A3 (de) Verbessertes Deckschicht-Masken-Lithographieverfahren für Halbleiter-Herstellung
EP0942461A3 (de) Veringerung von schwarzem Silizium in der Halbleiterfabrikation
EP0314399A3 (de) Vergrabene Zenerdiode und Verfahren zu deren Herstellung
TW373270B (en) Method for forming impurity junction regions of semiconductor device
EP0785573A3 (de) Verfahren zur Bildung von erhöhten Source- und Drainzonen in integrierten Schaltungen
EP0942463A3 (de) Verfahren zur Entschichtung einer implantierten Photoresistschicht
EP0776040A3 (de) Integrierte Schaltungsverdichtung und Verfahren

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE ES FR GB IT NL

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

17P Request for examination filed

Effective date: 19990121

AKX Designation fees paid

Free format text: DE ES FR GB IT NL

RBV Designated contracting states (corrected)

Designated state(s): DE ES FR GB IT NL

17Q First examination report despatched

Effective date: 20040924

RAP3 Party data changed (applicant data changed or rights of an application transferred)

Owner name: LUCENT TECHNOLOGIES INC.

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: ALCATEL-LUCENT USA INC.

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: LUCENT TECHNOLOGIES INC.

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

R17C First examination report despatched (corrected)

Effective date: 20040924

R17C First examination report despatched (corrected)

Effective date: 20040924

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20190216