EP0816955B1 - Circuit électronique et pièce d'horlogerie contenant un tel circuit - Google Patents

Circuit électronique et pièce d'horlogerie contenant un tel circuit Download PDF

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Publication number
EP0816955B1
EP0816955B1 EP97810403A EP97810403A EP0816955B1 EP 0816955 B1 EP0816955 B1 EP 0816955B1 EP 97810403 A EP97810403 A EP 97810403A EP 97810403 A EP97810403 A EP 97810403A EP 0816955 B1 EP0816955 B1 EP 0816955B1
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EP
European Patent Office
Prior art keywords
signal
electronic circuit
circuit
voltage
circuit according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP97810403A
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German (de)
English (en)
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EP0816955A1 (fr
Inventor
Konrad Schafroth
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Richemont International SA
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Richemont International SA
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Publication date
Priority claimed from PCT/EP1996/002791 external-priority patent/WO1997009657A1/fr
Priority to DK96923940T priority Critical patent/DK0848842T3/da
Priority to ES97810403T priority patent/ES2196288T3/es
Priority to DE59709745T priority patent/DE59709745D1/de
Priority to EP02022189A priority patent/EP1276024B1/fr
Priority to EP97810403A priority patent/EP0816955B1/fr
Application filed by Richemont International SA filed Critical Richemont International SA
Publication of EP0816955A1 publication Critical patent/EP0816955A1/fr
Priority to TW087102932A priority patent/TW366444B/zh
Priority to US09/035,340 priority patent/US6194878B1/en
Priority to SG1998000515A priority patent/SG72793A1/en
Priority to KR1019980007891A priority patent/KR100547249B1/ko
Priority to JP10075010A priority patent/JP2933910B2/ja
Priority to US09/634,675 priority patent/US6208119B1/en
Publication of EP0816955B1 publication Critical patent/EP0816955B1/fr
Application granted granted Critical
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C10/00—Arrangements of electric power supplies in time pieces
    • G—PHYSICS
    • G04—HOROLOGY
    • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C19/00—Producing optical time signals at prefixed times by electric means
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G19/00—Electric power supply circuits specially adapted for use in electronic time-pieces
    • G—PHYSICS
    • G04—HOROLOGY
    • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C11/00—Synchronisation of independently-driven clocks

Definitions

  • the present invention relates to an electronic circuit according to the preamble of claim 1 and a clockwork which contains such a circuit.
  • CH-A-597636 (Ebauches S.A.) proposed the batteries of a clockwork to be replaced by a generator and a spring driving the generator.
  • the clockwork described contains a spring that a via a gear train Time display and drives an alternating voltage generator.
  • the generator feeds a rectifier, the rectifier feeds capacitive component, and the capacitive component feeds one electronic reference circuit with a stable crystal oscillator and a electronic control circuit.
  • the electronic control circuit has one Comparator logic circuit and one with the output of the comparator logic circuit connected and through the comparator logic circuit in their Power consumption controllable energy dissipation circuit.
  • An entrance The comparator logic circuit is with the electronic reference circuit and another input of the comparator logic circuit is with that Generator connected.
  • the comparator logic circuit is designed so that a clock signal coming from the electronic reference circuit compares a clock signal originating from the generator, depending on the Result of this comparison the size of the power consumption of the Energy dissipation circuit controls and in this way via the controller the control circuit power consumption the gear of the generator and thus regulates the course of the time display.
  • Patent documents EP-A-0239820 and EP-A-679968 describe various electronic circuits to control the speed a microgenerator in which a monitoring circuit constantly Angular position of the rotor is monitored and brakes as soon as its Angular position is ahead. These circuits are, because of their sensitivity on errors and phase variations of the components, difficult to handle.
  • the voltage converter circuit contains different capacities C1; C2; C3, which is fed by active elements from the microgenerator be, for example by field effect transistors instead of diodes. Diodes are only used to initialize the system. The energetic Efficiency of the circuit can be greatly improved in this way are avoided by the threshold voltage losses of the diodes become. The circuit can thus have a lower peak voltage work, reducing the size of the generator and the spring and allows an increase in the power reserve of the clockwork.
  • FIG 1 is a block diagram of an inventive electronic circuit 11 for speed control of a Microgenerators shown.
  • the electronic circuit is from the micro-generator 1, the speed of which it regulates, via a capacitance C3 which corresponds to that of Generator temporarily saves energy supplied, fed.
  • the Microgenerator 1, which generates an alternating voltage, is not used illustrated gear train driven by a spring, not shown. The In addition, gears drive the time display (not shown).
  • the Electronic circuit 11 regulates the power consumption of one Microgenerator connected energy dissipation circuit 9 (Fig. 11) so that the frequency of rotation of the rotor of the microgenerator with the Reference frequency at the output of a frequency divider 5, the input of a crystal oscillator 3, 4 is fed, is synchronized.
  • a microgenerator is used, which is described in patent application EP-A-0 851 332.
  • the nominal frequency of the alternating voltage of the microgenerator 1 is preferably 2 n Hz, where n is a natural number other than zero.
  • the mechanical part of the clockwork is part of the prior art and is described, for example, in CH-A-597636.
  • the microgenerator 1 is with the two inputs G- and G + electronic circuit 11 connected. Circuit 11 is preferred built as a single IC.
  • the inputs G- and G + are with one Rectifier and voltage converter circuit 2 connected, their function is described further below with reference to FIGS. 2-5.
  • the rectifier and voltage converter 2 charges a storage capacitor 10 (C3) that temporarily stores the electrical energy generated by the microgenerator is generated and gives the energy in the form of an essentially continuous voltage to the IC.
  • the rectifier and Voltage converter 2 also uses two further capacitors 16 (C1) and 15 (C2).
  • the capacitors C1, C2 and C3 are preferred external, although they could possibly be integrated in the IC 11.
  • the Energy dissipation circuit connected in parallel with the microgenerator 1.
  • the Energy dissipation circuit 9 could also on the other side of Rectifier and voltage converter 2, in parallel with the capacitor C3 switched, arranged.
  • the energy dissipation circuit 9 consists of an ohmic resistance, the value of which by energy dissipation control means 30 (Fig. 10) is controlled.
  • the energy dissipation circuit 9 could also consist of an adjustable power source. The Rotation speed of the rotor of the microgenerator 1 is thereby controlled by varying the resistance value.
  • a stabilized one, in particular with reference to FIG. 6 described current source 32 generates various stabilized currents pp, pn, which for feeding the rectifier and voltage converter 2 and the Elements 3, 7, 31 are determined.
  • the stabilized current source 32 obtains its Energy from the capacitance C3, which feeds the entire IC.
  • An oscillator 3.4 provides a reference signal with a predetermined frequency.
  • the oscillator 3.4 has a quartz 4, which is preferably mounted outside of the IC 11 and its vibrations are a reference frequency at the output of the Define oscillator 3. This reference frequency is determined using a Frequency divider 5 divided by a predetermined factor, which in will be described with reference to Figures 7 and 8.
  • the IC also includes a counter 6, which is detailed below Referring to Figure 9 will be described.
  • a decrement input (DOWN) of the counter 6 is connected to the output of the frequency divider 5, during the incremental input (UP) of the counter 6 via a Hysteresis comparator 7, which the zero transitions of the signal at the output of the microgenerator 1, and via an anti-coincidence circuit 8 the microgenerator 1 is connected.
  • the anti-coincidence circuit 8 prevents simultaneous entry of UP and DOWN pulses both inputs of counter 6, which would otherwise be an unpredictable one Can assume behavior.
  • the Anti-coincidence circuit the signals UP and DOWN on signals with different phase, which come from the frequency divider 5.
  • the IC further includes an internal voltage doubler 31, which it allowed the energy dissipation control means 30 and Energy dissipation circuit 9 with a higher voltage HV> Vdd and to feed and control a lower voltage LV ⁇ Vss.
  • the energy dissipation control means 30 control the Energy dissipation of the energy dissipation circuit 9 as a function of Reference signal, which is generated by the quartz oscillator 3.4 and from Signal that comes from the microgenerator 1. If the rotor of the Microgenerator 1 rotates too quickly, is the frequency of the signal between the Inputs G + and G- higher than the frequency of the reference signal on Output of the frequency divider 5. The counter 6 thus receives during one Time interval more pulses on its incremental input UP than on its decrement input DOWN; its count thus increases.
  • the regulation value B1: B31 which of the energy dissipation circuit 9 from the energy dissipation control means circuit 30 depends in this example from the counter value 6, that is, from the difference between Number of pulses of the UP signal, which come from the microgenerator, and the number of pulses DOWN, which come from the quartz oscillator 3.4, since the Start of the clock.
  • the type of control is thus integral.
  • Other Control types for example a control which is proportional to current frequency difference or to the gradient of the Frequency difference or a PID control (proportional-integral-derivative) can also be used.
  • a control which is proportional to current frequency difference or to the gradient of the Frequency difference or a PID control (proportional-integral-derivative) can also be used.
  • a control which is proportional to current frequency difference or to the gradient of the Frequency difference or a PID control (proportional-integral-derivative) can also be used.
  • an on-off control could
  • the energy dissipation control means include one Hysteresis comparator 7, which the signals G +, G- on the two with the Microgenerator 1 compares connected inputs.
  • the signal on The output of the comparator 7 is therefore a rectangular signal, which is its State with every change in polarity of the signal between the inputs G +, G- changes.
  • the use of a hysteresis comparator allows filtering interference of the signal between the inputs G +, G-. To avoid unwanted changes in the value of the signal Gen, which lead to incorrect Increments and thus excessive braking of the Microgenerators could lead to other filter media, for example Low pass or band filter, or a filter that only after a predefined Time period changes its state to be provided.
  • the Hysteresis comparator 7 is fed by the current source 32.
  • the rectification and voltage converter circuit 2 is on the Figures 2-5 shown.
  • the first switch 19 preferably consists of a Field effect transistor, which immediately after starting the clockwork as simple diode acts.
  • the voltage drop across the switch 19 is in this moment equal to the diode threshold voltage, about 400 mV.
  • the comparators can work the transistors that act as switches through the comparators driven. If the one provided by the voltage triplet circuit Voltage is higher than the voltage of the capacitor 10, the first Field effect transistor opened.
  • the voltage drop across the channel of the However, the field effect transistor is only about 10 mV. The loss of tension is used when using transistors and the transistors Comparators instead of diodes are therefore significantly reduced
  • the clockwork's energy reserve is used more economically and the power reserve elevated.
  • the field effect transistor 19 is only blocked again when the by voltage C2 supplied to the voltage tripler circuit again below the Voltage Vdd of the first capacitor 10 drops.
  • the first switch 19 is controlled by a signal / ser, which output by a first comparator circuit 21 shown in FIG becomes.
  • the comparator circuit 21 has a comparator 210, which compares the voltage on both sides of the switch 19. If the Voltage C2 on the left side of the switch is higher than the voltage Vdd on the right, the output of comparator 210 goes from 0 to 1.
  • the offset voltage is + 2mV
  • the Voltage difference across the switch 19 be 2mV or more so the output of comparator 210 goes to 1.
  • a NAND gate 3081 which the frequency divider 5 emitted signals of 16kHz, 8kHz, 4 kHz, 2kHz and 1kHz combined there a signal p off.
  • the pulsation signal p therefore always has the value 1, except once per 1 kHz cycle during a 16 kHz half cycle.
  • This signal at the output of NAND gate 3081 is through an inverter 3082, which is connected to an AND gate 3083, inverted.
  • a power-on reset Signal rud the formation of which will be explained later with reference to FIG. 8, is delivered to the other entrance to gate 3083.
  • the signal is zero, then always one. That's how it is Signal mess, which is given by gate 3083, always zero, except after start-up if p has the logical state 1.
  • the signal p at the output of the NAND gate 3081 is below other to the OR gate 3084, which also has a 32 kHz signal receives, which comes from the frequency divider 5.
  • the signal r coming from the gate 3084 is always set to zero, except if p and the 32 kHz signal are simultaneously zero, i.e. once per 1 kHz cycle during a half 32 kHz cycle.
  • This signal is through the signal was validated and inverted using a 3085 NAND gate. This is how it works the signal latch, which is output by the gate 3085, only at zero over when r has taken the value 1 and if not rud at the same time Is zero.
  • the latch signal is used to determine the state at the output of the comparators 20 and 21 in the memory elements 201, 211 in the Compare circuits 20, 21 to save.
  • the signals mess and latch can only be formed if the The crystal oscillator and the divider chain work.
  • the circuit must be designed in such a way that when starting the system, the switches directly from the comparators can be controlled:
  • the switches directly from the comparators can be controlled:
  • the switches 19 is driven directly by the comparators 20, 21.
  • the switch 19 With that in the storage means 211 stored value controlled.
  • the voltage tripler 15, 16, 17, 18 contains a second one Capacitor 15 (C2) and a third capacitor 16 (C1) in series with the microgenerator 1 are connected at the inputs G + and G-.
  • On second switch 17 is between the input G and the ground set end of the third capacitor 16 with respect to the microgenerator connected.
  • a third switch 18 is connected between the input G + and the End of the second capacitor 15 connected to the microgenerator, which is connected to the first switch 19.
  • Switches 17 and 18 are controlled by a second comparator circuit 20 (FIG. 3), which the electrical potential of the input G-, which corresponds to the second Capacitor 15 is connected to the potential of the ground.
  • the switches 17 and 18 also consist of Field effect transistors, which act as diodes in the blocked state.
  • the switches 17 and 18 also consist of Field effect transistors, which act as diodes in the blocked state.
  • the Capacities 15 and 16 are started by the Diode structures of transistors 17 and 18 loaded.
  • the second comparator circuit 20 toggles at the next one Edge of the signal mess, and the state of the comparator is at the Edge of the latch signal is stored in memory element 201, and the switch controlled with the stored values.
  • the two transistors 15 and 16 are then leading.
  • the capacitors 15 and 16 are therefore alone charged through the channel of transistors 17 and 18, which is energetically proves favorable. It should be noted that the one with the microgenerator 1 connected input G- via the channel of transistor 17 to ground is set as soon as the transistor 17 conducts.
  • Comparators 200 and 210 are used fed with the voltage Vdd stored in the capacitor C3. in the further you need a power supply pp, or pn, which is accomplished by the current source 32, which is explained in FIG. 6.
  • the comparators do not work as long as the currents pp and pn do not are high enough; in this case, its output remains in the zero state, such that the controlled switches 17, 18, 19 remain locked.
  • the current source 32 consists of a classic current mirror. It contains a high value resistor 321, for example 300K ⁇ , which is between the ground and the source of an N-channel field effect transistor 322 is switched.
  • the drain of transistor 322 is with the drain of the field effect transistor 323a and with the gate of 3 P-channel transistors 323a, 323b, 323c connected in series, the source of the latter is fed with the voltage generated by the voltage converter 2.
  • the drain of transistor 322 is further connected to the gate of the three P-channel field effect transistors 323a, 323b, 323c connected as a mirror circuit.
  • the Current pp which is the channel of transistor 322 and resistor 321 traverses, feeds the comparator 200, which is explained in Figure 3.
  • the drain of transistor 323a is with the drain of the N-channel transistor 322 connected and to the gate of the N-channel transistors 322a ', 322b ', 322c', 322d 'in series and as a mirror with respect to transistor 322 connected.
  • the source of transistor 322a ' is connected to ground.
  • the size of the current can therefore be determined by the characteristics of the elements in the power source, especially the number Transistors and the size of their channels. It is so possible to release the currents pp and pn through the two branches of the mirror to determine.
  • Such a current mirror has two equilibrium states. The the first has been described and is achieved when the currents pp and pn are the have reached the desired strength. The second state corresponds to the currents pp and pn equal to zero. This second state is reached when all Transistors are blocked. This condition exists especially if that System is energized, according to which the currents pp and pn are zero.
  • An N-channel initialization transistor 320 is provided to be at the start-up phase to force a current through the current mirror 32, so that he reaches his first state of equilibrium. The gate of transistor 320 is at ground while its source is connected to the G- des input Microgenerator 1 is connected. The drain of the initialization transistor will connected to the gate of the P-channel transistors.
  • the micro-generator 1 floating with respect to the mass.
  • the signal G-am The input of the microgenerator therefore oscillates approximately sinusoidal in terms of mass. If the input signal G- negative is, that is below the voltage of the ground, the transistor 320 permeable and the negative voltage of G- is applied to the gate of the P-channel transistor 323a ', 323b', 323c '. These transistors will be consequently suddenly conductive, such that only a current pn circulates that the Voltage at the gate of transistor 322 rises and that this too passes a current pp. This current is, as explained above, to the Comparator 20 ( Figure 3) applied in the rectifying and converter circuit 2, which starts to work.
  • the output signal of the comparator circuit 20 changes its state as indicated in Figure 2 when the voltage at node G- is lower than Vss, and opens transistors 17 and 18, which the input G- of the microgenerator 1 with the mass and the input G + of the Micro generator connects with C2. As soon as the input G- with the mass is connected, the transistor 320 is blocked and from now on stops current to consume. The current source 2 is initialized from now on and the currents pp and pn quickly reach the desired value.
  • the power source can be easily completed, for example by means of other N-channel transistors, whose gate connects to the drain of the Transistor 323a 'and the source are connected to ground.
  • the current through these transistors it can easily be used for feeding others Components are checked, for example by components of the Quartz oscillator 3.4.
  • FIG. 7 illustrates a preferred embodiment of a frequency divider 50 of the present invention.
  • the frequency divider consists of ten D flip-flops connected in series. The frequency of the signal is divided by 2 for each flip-flop. If the reference signal supplied by the oscillator 3, 4 at the input of the frequency divider 50 oscillates at 32 kHz, the frequency of the signal at the output of the divider 50 is 2 -10 * 32 kHz, that is to say 32 Hz 4 kHz signal combined to generate a signal DOWN, which assumes the logic state 1 once per cycle of 32 Hz and during a half cycle of 4 kHz.
  • FIG. 8 explains a circuit 51 that performs a power-on reset Signal rud delivers. This signal is determined, among other things, the counter 6 reset to a predetermined value during initialization and the Turn off energy dissipation circuit 9.
  • Circuit 51 includes FIG. 3 P-channel field effect transistors 510, 511, 512, which are in series with a P-channel transistor are arranged between the mass and the feed. The The gate of the three P-channel transistors receives the signal pp, which from the Power source 32 comes. During initialization, the 3 transistors 510, 511 and 512 blocked as long as the current source 32 does not have enough Supplies electricity. The voltage at point 516 is therefore zero.
  • the inverter 550 converts this voltage into a signal POR1, which is by means of an OR gate 528 is combined with a signal POR2.
  • the signal at the output of the Gate 528 is connected to one of the two NOR gates 517 and 518 Forwarded flip-flops with 2 inputs.
  • the other input of the flip-flop 517, 518 is connected to the output of a frequency divider 520, which consists of five flip-flops 521-526 is composed.
  • the 32 Hz output signal that is emitted by the frequency divider 50 is with the input of the first Flip flops 521 connected.
  • the inputs / reset for resetting the flip-flops 521-526 are connected via an inverter 527 to the output of inverter 515 connected.
  • the POR1 signal is one as long as the Power source does not provide enough power.
  • the signal is similar POR2 One as long as the frequency from the frequency divider 5 is not one predetermined value reached.
  • the signal at the output of gate 528 is therefore only zero when the quartz oscillator and the power source both function.
  • the 3rd Transistors 510 to 512 transparent.
  • the signal at point 516 is consequently Vdd such that the inverter 515 outputs a signal POR1 with a returns logical value zero.
  • the frequency divider 520 begins dividing the supplied 32 Hz frequency. After a second the signal goes out of the flip-flop 560 to 1. Since the two inputs of the flip-flop 517, 518 den received logic value 1, its output goes to zero, so that the signal rud reaches the logical value 1. This value is then maintained as long as the current value pp is sufficient and the Quartz oscillator also works.
  • the second power-on-reset signal POR2 goes to one as soon as the frequency from the frequency divider drops below a certain value. Thus appears after a short period of time the signal rud again, so that the switches 17, 18, 19 of the voltage converter also in this case directly from the Comparators 200, 210 are controlled.
  • the startup of the Ics only ensured with the signal POR2 from the frequency divider.
  • the signal POR2 remains at zero.
  • FIG. 9 explains a preferred embodiment the counter circuit 6.
  • the counter circuit 6 comprises one 6-bit counter 60 t.
  • the counter 60 can be reset, for example, by six and D-type flip-flops connected in series.
  • the binary number, which by The outputs Q1 through Q6 are formed by one unit at each Leading edge, which is output to input 601, too.
  • the counter is reset to zero when a signal rushes to reset input 603 is delivered.
  • the signals Q1-Q6, which are output by the counter 6, allow the coding of 64 different braking values.
  • the Energy dissipation via the braking resistor Rf the Energy dissipation circuit 9 preferably develops in such a way as shown schematically on the diagram of Figure 10A. Between 0 and 31 is the frequency difference integrated by counter 6 between the microgenerator 1 and the oscillator 3, 4 low: none Braking initiated.
  • FIG. 10 explains the energy dissipation control means 30 convert the signals Q1: Q6 from the counter into signals B1: B63, which the on Drive the energy dissipation circuit 9 explained in FIG. 11 directly.
  • the energy dissipation circuit 9 is direct switched between the inputs G +, G- of the microgenerator.
  • she consists from a variety of resistors 910 to 916 integrated on the IC Switches 900 through 906, which are determined by the energy dissipation control means 30 originating signals B1 to B5 and B62, B63 controlled allow the number of parallel ones to be modified Resistances.
  • the values of the resistors 910 to 916 are according to FIG. 10A inversely proportional to the strength of the control signals B1 - B63: the signals B62 and B63 thus control braking more effectively than, for example, the signal B1.
  • the switches 900 to 906 are N-channel field effect transistors. If the voltage at the gate of the transistor is at 0, the transistor blocks, it flows so no current through the transistor. But as soon as the voltage at the source of the corresponding transistor is below Vss, the transistor becomes conductive. This means that the generator is braked because now a current flows, since the Resistors connected between the terminals (G + and G-) of the generator are.
  • the Generator a significantly higher speed than the nominal speed and thus the highest possible output voltage is achieved so that the circuit can start at all. But it is possible that the voltage at G + and G- comes to be below Vss, so that the generator is then braked, because the switching transistor for the brake becomes conductive. But if the high Speed and thus the high output voltage is not reached, the Do not start the circuit due to the voltage drop across the diodes.
  • N-channel and P-channel transistors can only be close to Vss and Vdd can be used as good switches.
  • Vss voltage on drain and Source
  • the gate of the N-channel transistor must now a voltage higher than Vdd can be driven so that the transistor is good passes.
  • the P-channel transistor the gate of which with a Voltage that is at least one threshold value lower than Vss must be so that the transistor is well conductive.
  • the transistor 920 is not driven with Vss, but rather with a signal LV, which in the active state has a much lower voltage than Vss has.
  • the formation of LV in circuit 30 will be discussed further below described.
  • the N-channel transistors 900: 906 cannot directly use the signals Q1: Q6 are driven from the counter because these signals cannot be higher than Vdd. Therefore, these transistors with the Signals B1: B63 driven, the logic states of which of Q1: Q6 correspond, but the voltages are doubled. To this purpose, the signals Q1 - Q5 with level shifters 301 - 305 in the Energy dissipation control means 30 into the output signals B1-B5 converted.
  • the level shifters 301-305 in Figure 10 are by a voltage HV fed, which by doubling the voltage Vdd on Capacitor C3 by means of a voltage doubler 31, not shown is obtained. So that the circuit can start reliably, the Voltage doubler can be built so that it also during initialization provides a voltage that is at least equal to Vdd. For example the voltage doubler 31 rud by the signal already described can be controlled so that it has a voltage Vdd during initialization delivers, and a doubled voltage HV, only after the signal rud changed its state when the quartz oscillator and the power source both work.
  • the logical state «62» is represented by an AND gate 306 proven if the signals B2, B3, B4, B5 are all 1 (62 decimal expressed corresponds to 111110 binary).
  • Gate 306 multiplies signals B2 to B5 and delivers a signal B62 with the logic state 1 only if the Counter value reached levels 30 or 31.
  • a second AND gate multiplies B62 with B1 in such a way that the logical state «63» by means of a Signal B63 is detected.
  • the signals B62 and B63 directly control the Transistors 905 and 906, respectively.
  • the circuit 30 supplies the signal LV, which for driving the P-channel transistor 920 in the Energy dissipation circuit 9 is determined.
  • the LV signal is from one Levelshifter 300 generated.
  • the transistor 920 In order for the transistor 920 to conduct well, it must, as already mentions the voltage from the LV signal in the active state at least one Threshold be lower than Vss.
  • a transistor 3006 that how a diode works is between the other side of capacitance 3005 and the point / rud connected.
  • the transistor 3006 has a threshold value Ue, e.g. 400mV.
  • the level shifter 300 If the level shifter 300 supplies a voltage HV, it is in the capacity 3005 charged voltage AU HV-Ue. When the tension on Output of the level shifter 300 suddenly drops to Vss, the voltage drops of the LV signal to Vss- (HV-Ue), which allows transistor 920 to be in the bring conductive state.
  • the signal / rud is one, see above LV remains at one and transistor 920 is turned off.
  • the Transistor 920 can only conduct once the signal / rud is zero.
  • the level shifter 300 is controlled by a signal / b such that the energy dissipation circuit 9 brakes when the signal / b is zero.
  • the signal / b is emitted by a NAND gate 3080, which receives the signals Q6 and p logically combined.
  • the signal / b is 1 if at least one of these two signals is zero. For example, if Q6 is zero, that means if the counter 6 has not reached at least level 16, is the signal / b 1 such that the energy dissipation circuit 9 only from stage 16 of the counter can brake, according to the diagram of Fig. 10a.
  • the education of the pulsation signal p by circuit 308 has already been referenced to FIG. 5a explains.
  • the pulsation signal p therefore always has the value 1, except once per 1 kHz cycle during a 16 kHz half cycle. This is to recharge the capacity that the LV generates. there is the braking by the pulsation signal p once every millisecond interrupted (pulsed braking). Solutions are also conceivable, however those with LV 1 and LV 2 and accordingly with 2 P-channel transistors is worked so that the brake does not have to be interrupted.

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromechanical Clocks (AREA)
  • Dc-Dc Converters (AREA)
  • Electric Clocks (AREA)
  • Control Of Electric Motors In General (AREA)
  • Control Of Eletrric Generators (AREA)

Claims (24)

  1. Circuit électronique de réglage de la vitesse de rotation d'un microgénérateur (1), comprenant:
    une première entrée (G-) et une deuxième entrée (G+) pouvant être connectée avec le microgénérateur (1),
    un oscillateur (3, 4) délivrant un signal de référence d'une fréquence prédéterminée,
    un circuit de dissipation d'énergie (9) pour freiner le microgénérateur (9),
    des moyens de contrôle de la dissipation d'énergie (5, 6, 7, 8, 30, 31) pour contrôler la dissipation d'énergie du circuit de dissipation d'énergie (9) en fonction du signal de référence et du signal entre lesdites entrées (G-, G+),
    un circuit de redressement et de conversion de tension (2) pour redresser et multiplier le signal entre lesdites première et deuxième entrées, le circuit de redressement et de conversion de tension (2) comprenant au moins un condensateur (C1; C2; C3) pouvant être chargé par ledit microgénérateur au travers d'au moins un interrupteur (17, 18, 19),
    au moins un circuit de commande (20; 21) du ou desdits interrupteurs (17, 18, 19) comprenant au moins un moyen de mémoire qui, lors d'une phase de mesure avec l'interrupteur bloqué, mémorise au moins un signal de commande à appliquer sur ledit interrupteur (17, 18, 19), ledit interrupteur (17, 18, 19) étant commandé par ledit signal de commande (ser/par) lors d'une deuxième phase de commutation.
  2. Circuit électronique selon la revendication précédente, dans lequel
    ledit circuit de dissipation d'énergie (9) comporte un réseau d'éléments connectés en parallèle, chaque élément comportant une résistance (910 à 916) en série avec un interrupteur (900:906), la résistance totale du circuit de dissipation d'énergie pouvant être contrôlée en connectant une combinaison prédéterminée d'interrupteurs (900: 906),
    lesdits interrupteurs (900 à 906) en série avec lesdites résistances (910:916) étant des transistors à effet de champ à canal N,
    ledit circuit de dissipation d'énergie (9) comportant en outre au moins un transistor à effet de champ à canal P (920) en série avec ledit réseau d'éléments (900: 916) connectés en parallèle,
    ledit circuit comportant en outre des moyens de contrôle (3080, 300) dudit transistor à effet de champ à canal P (920) afin de bloquer ledit transistor à effet de champ à canal P lors de la mise en marche du circuit de manière à supprimer le freinage du microgénérateur.
  3. Circuit électronique selon la revendication précédente, dans lequel lesdits transistors à effet de champ à canal N sont commandés avec une tension supérieure à Vdd,
       ledit transistor à effet de champ à canal P (920) étant commandé avec une tension inférieure à Vss d'au moins une valeur de seuil.
  4. Circuit électronique selon l'une des revendications précédentes,
       le circuit de redressement et de conversion de tension comportant au moins un interrupteur entre ladite première entrée (G-) et un point de référence dans le circuit ainsi qu'un comparateur (20) pour contrôler le premier interrupteur,
       une source de courant stabilisée (32) alimentant en particulier ledit comparateur (20) dans le circuit de redressement et de conversion de tension,
       ladite source de courant stabilisée (32) comprenant un transistor d'initialisation (320) permettant l'injection ou le prélèvement de courant dans ladite source de courant.
  5. Circuit électronique selon la revendication 4, caractérisé en ce que ledit transistor d'initialisation (320) est connecté avec ladite première entrée (G-) et le point de référence de tension, de manière à ce qu'un courant soit injecté ou prélevé dans ladite source de courant aussi longtemps que ladite première entrée (G-) présente une différence de tension avec ledit point de référence.
  6. Circuit électronique selon l'une des revendications précédentes, caractérisé en ce que ledit point de référence est la masse et en ce que ledit transistor d'initialisation (320) est un transistor à effet de champ à canal N, dont la grille est connectée à la masse et dont la source est connectée avec ladite première entrée (G-).
  7. Circuit électronique selon l'une des revendications précédentes, caractérisé en ce que ledit circuit de commande (20, 21) comprend un comparateur (200, 210).
  8. Circuit électronique selon l'une des revendications précédentes, caractérisé en ce que le freinage est bloqué pendant un cycle sur deux du signal du microgénérateur.
  9. Circuit électronique selon la revendication 3, caractérisé par des décaleurs de niveau (301 à 305) pour augmenter la tension des signaux (Q1-Q5) de contrôle desdits transistors à effet de champ à canal P (900-906).
  10. Circuit électronique selon l'une des revendications précédentes, caractérisé en ce que ledit circuit de dissipation d'énergie (9) est connecté entre lesdites entrées (G-, G) destinées à être reliées au microgénérateur.
  11. Circuit électronique selon l'une des revendications précédentes, caractérisé en ce que ledit circuit de dissipation d'énergie (9) est connecté entre les bornes destinées au dit condensateur (10) chargé par le microgénérateur.
  12. Circuit électronique selon l'une des revendications précédentes, caractérisé en ce que lesdits moyens de contrôle de la dissipation d'énergie (5, 6, 7, 30, 31) comportent un compteur (6) dont la valeur dépend de la différence de fréquence entre le générateur (1) et l'oscillateur (3, 4), la dissipation d'énergie du circuit de dissipation d'énergie étant dépendante de ladite valeur de compteur.
  13. Circuit électronique selon la revendication précédente, dans lequel la valeur du compteur (9) augmente à chaque impulsion d'un signal d'incrémentation (UP) provenant du signal entre les deux entrées (G-, G+) et diminue à chaque impulsion d'un signal de décrémentation (DOWN) provenant dudit oscillateur (3, 4).
  14. Circuit électronique selon la revendication précédente, caractérisé en ce qu'il comporte des moyens (51, rud) pour réinitialiser ledit compteur (6) à une valeur prédéterminée lorsque le circuit est mis sous tension.
  15. Circuit électronique selon l'une des revendications précédentes, caractérisé en ce qu'il comporte des moyens d'initialisation (51) qui délivrent un signal (POR1) avec une valeur déterminée aussi longtemps que le courant délivré par ladite source de courant stabilisée (32) n'atteint pas une valeur prédéterminée, et un signal de valeur opposée dès que le courant délivré par ladite source de courant stabilisée (32) dépasse ladite valeur prédéterminée.
  16. Circuit électronique selon l'une des revendications précédentes, caractérisé en ce qu'il comporte des moyens d'initialisation qui délivrent un signal (POR2) avec une valeur déterminée aussi longtemps que l'oscillateur à quartz ne fonctionne pas, et un signal de valeur opposée dès que l'oscillateur à quartz fonctionne.
  17. Circuit électronique selon l'une des revendications précédentes, caractérisé en ce qu'il comporte des moyens d'initialisation qui délivrent les signaux suivants:
    un premier signal de power-on-reset (POR1) avec une valeur déterminée aussi longtemps que le courant délivré par ladite source de courant stabilisée (32) n'atteint pas une valeur prédéterminée, et un signal de valeur opposée dès que le courant délivré par ladite source de courant stabilisée (32) dépasse ladite valeur prédéterminée,
    un deuxième signal de power-on-reset (POR2) avec une valeur déterminée aussi longtemps que l'oscillateur à quartz ne fonctionne pas, et un signal de valeur opposée dès que l'oscillateur à quartz fonctionne,
    les moyens d'initialisation comportant en outre des moyens (528) qui combinent les deux signaux de power-on-reset (POR1, POR2).
  18. Circuit électronique selon l'une des revendications 15 à 18, caractérisé en ce que les moyens d'initialisation (51) contiennent des moyens de retardement (510).
  19. Circuit électronique selon l'une des revendications précédentes, caractérisé en ce que la dissipation d'énergie dudit circuit de dissipation d'énergie (9) peut prendre au moins trois valeurs déterminées.
  20. Circuit électronique selon l'une des revendications précédentes, caractérisé par des moyens (51) pour minimiser la dissipation d'énergie dudit circuit de dissipation d'énergie (9) lorsque le circuit électronique est mis sous tension.
  21. Circuit électronique selon l'une des revendications précédentes, caractérisé en ce que ledit oscillateur (3, 4) est relié à un diviseur de fréquence (50)
  22. Circuit électronique selon l'une des revendications précédentes, caractérisé en ce que lesdits moyens de contrôle de la dissipation d'énergie comprennent les composants suivants:
    un comparateur à hystérèse (7) qui compare le signal entre lesdites premières et deuxièmes entrées (G-, G+), et
    un circuit d'anticoïncidence (8) relié à la sortie dudit comparateur à hystérèse (7) et qui délivre ledit signal d'incrémentation (UP).
  23. Circuit électronique selon l'une des revendications précédentes, caractérisé en ce que ledit circuit de redressement et de conversion de tension (2) comporte au moins un condensateur (10, 15, 16) qui est chargé à travers un ou plusieurs éléments passifs lors de la mise sous tension du circuit électronique, le ou les dits éléments passifs étant remplacés par des éléments actifs (17, 18, 19) dès que la tension dans le ou les condensateurs (10, 15, 16) est suffisante pour activer les éléments actifs.
  24. Mouvement de montre comprenant un circuit selon l'une des revendications précédentes.
EP97810403A 1996-06-26 1997-06-25 Circuit électronique et pièce d'horlogerie contenant un tel circuit Expired - Lifetime EP0816955B1 (fr)

Priority Applications (11)

Application Number Priority Date Filing Date Title
DK96923940T DK0848842T3 (da) 1996-06-26 1996-06-26 Urværk
ES97810403T ES2196288T3 (es) 1996-06-26 1997-06-25 Circuito electronico y pieza de relojeria que contiene tal circuito.
DE59709745T DE59709745D1 (de) 1996-06-26 1997-06-25 Elektronischer Schaltkreis und Uhrwerk enthaltend einen solchen Schaltkreis
EP02022189A EP1276024B1 (fr) 1996-06-26 1997-06-25 Circuit de commutation électronique et pièce d'horlogerie avec un tel circuit de commutation
EP97810403A EP0816955B1 (fr) 1996-06-26 1997-06-25 Circuit électronique et pièce d'horlogerie contenant un tel circuit
TW087102932A TW366444B (en) 1997-06-25 1998-02-27 Speed-control circuit
US09/035,340 US6194878B1 (en) 1997-06-25 1998-03-05 Electronic speed control circuit
SG1998000515A SG72793A1 (en) 1997-06-25 1998-03-09 Electronic speed-control circuit
KR1019980007891A KR100547249B1 (ko) 1997-06-25 1998-03-10 전자식 속도-제어회로
JP10075010A JP2933910B2 (ja) 1997-06-25 1998-03-10 電子速度制御回路
US09/634,675 US6208119B1 (en) 1997-06-25 2000-08-08 Electronic speed-control circuit

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
PCT/EP1996/002791 WO1997009657A1 (fr) 1995-09-07 1996-06-26 Mouvement d'horlogerie
WOPCT/EP96/02791 1996-06-26
EP97810403A EP0816955B1 (fr) 1996-06-26 1997-06-25 Circuit électronique et pièce d'horlogerie contenant un tel circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
EP02022189A Division EP1276024B1 (fr) 1996-06-26 1997-06-25 Circuit de commutation électronique et pièce d'horlogerie avec un tel circuit de commutation

Publications (2)

Publication Number Publication Date
EP0816955A1 EP0816955A1 (fr) 1998-01-07
EP0816955B1 true EP0816955B1 (fr) 2003-04-09

Family

ID=8230273

Family Applications (2)

Application Number Title Priority Date Filing Date
EP02022189A Expired - Lifetime EP1276024B1 (fr) 1996-06-26 1997-06-25 Circuit de commutation électronique et pièce d'horlogerie avec un tel circuit de commutation
EP97810403A Expired - Lifetime EP0816955B1 (fr) 1996-06-26 1997-06-25 Circuit électronique et pièce d'horlogerie contenant un tel circuit

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP02022189A Expired - Lifetime EP1276024B1 (fr) 1996-06-26 1997-06-25 Circuit de commutation électronique et pièce d'horlogerie avec un tel circuit de commutation

Country Status (9)

Country Link
US (2) US6194878B1 (fr)
EP (2) EP1276024B1 (fr)
JP (1) JP2933910B2 (fr)
KR (1) KR100547249B1 (fr)
DE (1) DE59709745D1 (fr)
DK (1) DK0848842T3 (fr)
ES (1) ES2196288T3 (fr)
SG (1) SG72793A1 (fr)
TW (1) TW366444B (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998021815A1 (fr) 1996-11-13 1998-05-22 Seiko Epson Corporation Dispositif d'alimentation en energie et materiel electronique portatif
JP3006593B2 (ja) 1997-09-30 2000-02-07 セイコーエプソン株式会社 電子制御式機械時計およびその制御方法
US6795378B2 (en) 1997-09-30 2004-09-21 Seiko Epson Corporation Electronic device, electronically controlled mechanical timepiece, and control method therefor
US6633511B1 (en) 1998-11-17 2003-10-14 Seiko Epson Corporation Electronic controlling type mechanical timepiece
DE69940303D1 (de) * 1998-11-19 2009-03-05 Seiko Epson Corp Elektrisch kontrollierte mechanische uhr und bremsverfahren
EP1215545A1 (fr) 2000-12-18 2002-06-19 Asulab S.A. Montre électronique analogique ayant un dispositif de remise à l'heure suite à une insuffisance d'alimentation
JP3627660B2 (ja) * 2001-02-28 2005-03-09 セイコーエプソン株式会社 電子機器、電子制御式機械時計、電子機器の制御プログラム、記録媒体、電子機器の制御方法および電子機器の設計方法
CH694621A5 (fr) 2001-07-02 2005-04-29 Richemont Int Sa Procédé de régulation et module électronique de régulation pour mouvement d'horlogerie à remontage mécanique.
US6826124B2 (en) * 2002-12-04 2004-11-30 Asulab S.A. Timepiece with power reserve indication
EP1544692B1 (fr) * 2003-12-16 2007-03-14 Asulab S.A. Pièce d'horlogerie électromécanique comprenant un indicateur de réserve de marche
JP5707761B2 (ja) * 2010-07-20 2015-04-30 日産自動車株式会社 欠相診断装置及び欠相診断方法
CH705679B1 (fr) 2011-10-28 2017-01-31 Swatch Group Res & Dev Ltd Circuit d'autorégulation de la fréquence d'oscillation d'un système mécanique oscillant, et dispositif le comprenant.
EP2590035B1 (fr) * 2011-11-01 2020-12-30 The Swatch Group Research and Development Ltd. Circuit d'autorégulation de la fréquence d'oscillation d'un système mécanique oscillant, et dispositif le comprenant
CH707005B1 (fr) 2012-09-25 2023-02-15 Richemont Int Sa Mouvement de montre-chronographe avec barillet et régulateur à quartz.
CH707340A2 (fr) * 2012-12-11 2014-06-13 Richemont Internat Ltd Organe régulateur pour montre-bracelet.
CH707787B1 (fr) 2013-03-25 2021-09-15 Richemont Int Sa Organe régulateur pour montre bracelet et procédé d'assemblage d'un organe régulateur pour montre bracelet.

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH597636B5 (fr) * 1972-11-21 1978-04-14 Ebauches Sa
JPS5367826A (en) * 1976-11-29 1978-06-16 Seiko Epson Corp Boosting circuit
US4519024A (en) * 1983-09-02 1985-05-21 At&T Bell Laboratories Two-terminal transistor rectifier circuit arrangement
CH665082GA3 (fr) * 1986-03-26 1988-04-29
JPS63190562A (ja) * 1987-01-29 1988-08-08 Nec Corp 倍電圧整流回路
US4799003A (en) * 1987-05-28 1989-01-17 Tu Xuan M Mechanical-to-electrical energy converter
JP2652057B2 (ja) * 1988-01-25 1997-09-10 セイコーエプソン株式会社 発電装置
JP3000633B2 (ja) * 1990-07-18 2000-01-17 セイコーエプソン株式会社 電子機器
JP3058813B2 (ja) 1994-07-04 2000-07-04 セイコーエプソン株式会社 発電装置およびその制御方法
US5668414A (en) 1994-07-04 1997-09-16 Seiko Epson Corporation Spring driven electricity generator with a control circuit to regulate the release of energy in the spring
JP3174245B2 (ja) * 1994-08-03 2001-06-11 セイコーインスツルメンツ株式会社 電子制御時計
US5881027A (en) * 1995-09-07 1999-03-09 Schafroth; Konrad Timepiece movement
JPH0996686A (ja) * 1995-09-29 1997-04-08 Citizen Watch Co Ltd 電子時計とその充電方法
FR2752070B1 (fr) * 1996-08-01 1998-09-18 Asulab Sa Piece d'horlogerie electronique comportant une generatrice entrainee par un barillet a ressort
CN1119721C (zh) * 1997-09-30 2003-08-27 精工爱普生株式会社 电子控制式机械钟表及其控制方法

Also Published As

Publication number Publication date
ES2196288T3 (es) 2003-12-16
SG72793A1 (en) 2000-05-23
EP0816955A1 (fr) 1998-01-07
EP1276024B1 (fr) 2011-12-21
EP1276024A2 (fr) 2003-01-15
JPH1123743A (ja) 1999-01-29
US6194878B1 (en) 2001-02-27
DE59709745D1 (de) 2003-05-15
JP2933910B2 (ja) 1999-08-16
KR100547249B1 (ko) 2006-03-23
EP1276024A3 (fr) 2007-05-02
TW366444B (en) 1999-08-11
US6208119B1 (en) 2001-03-27
KR19990006361A (ko) 1999-01-25
DK0848842T3 (da) 1999-11-08

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