EP0788047B1 - Dispositif de référence de courant en circuit intégré - Google Patents
Dispositif de référence de courant en circuit intégré Download PDFInfo
- Publication number
- EP0788047B1 EP0788047B1 EP97400209A EP97400209A EP0788047B1 EP 0788047 B1 EP0788047 B1 EP 0788047B1 EP 97400209 A EP97400209 A EP 97400209A EP 97400209 A EP97400209 A EP 97400209A EP 0788047 B1 EP0788047 B1 EP 0788047B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- transistor
- resistor
- transistors
- current
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000005516 engineering process Methods 0.000 claims description 17
- 238000009792 diffusion process Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 229920006395 saturated elastomer Polymers 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000001419 dependent effect Effects 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 230000033228 biological regulation Effects 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000037213 diet Effects 0.000 description 1
- 235000005911 diet Nutrition 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S323/00—Electricity: power supply or regulation systems
- Y10S323/907—Temperature compensation of semiconductor
Definitions
- the invention relates to a reference device for stable current in integrated circuit.
- Such devices are used in particular in memory circuits, particular for generating timing signals stable necessary for reading or writing memory cells.
- EP-A-0 052 553 describes a current generator using the threshold difference between two transistors each mounted in a branch of a current mirror device, a resistance being placed in one of the branches to make up for this difference voltage and produce a stable current.
- the invention therefore relates to a device for intrinsically stable current reference, without feedback to compensate for this or that variation.
- the invention relates to a integrated circuit current reference device with a reference resistance.
- the device includes first and second transistor of the same type of conductivity, the first having its grid and its drain connected together to a first resistance terminal, the second having its grid and its drain connected together to a second resistance terminal, and the first transistor having a threshold voltage higher than that of the second transistor, the two transistors being polarized in saturated mode, the source of each of these transistors being polarized at the same potential as the substrate or the box in which the transistor is made.
- the device maybe transposed from one manufacturing technology to another without simulations.
- Figure 1 shows the electronic diagram of a integrated circuit current reference device according to the invention.
- the first transistor T1 has a voltage of threshold higher than that of the second transistor T2.
- the transistors T1 and T2 are of type N produced in a conventional technology with P substrate.
- the transistor T2 is then of the native type while the transistor T1 is of the enriched type, in order to fulfill the condition on the threshold voltages (Vt 1 ⁇ Vt 2 ).
- Their sources are then connected to ground.
- the substrate P is therefore connected to the same potential as the source of the transistors T1 and T2, which has the effect of eliminating the substrate effect. There is therefore a particularly stable threshold voltage with the supply voltage.
- a resistor R1 is connected to the drain of the first transistor T1 to call a load current I1.
- This polarization resistance R1 may very well be directly connected to the supply voltage Vcc, as shown in dotted lines in FIG. 1, or then, a bias circuit CP can be provided.
- the two transistors T1 and T2 which are mounted as a diode are then in saturated mode and there is on their drain, the threshold voltage of the transistor.
- the voltage V tN V tNna ' where V tN is the threshold voltage V t1 of the enriched transistor T1, of the order of 0.8 volt and V tNna is the threshold voltage V t2 of the native transistor T2, or about 0.2 volts.
- This reference current is independent of the temperature. Indeed, according to theory and as verified in practice, the threshold voltages of the native transistor and of the enriched transistor vary in parallel, by two millivolts per degree, so that their difference is practically independent of the temperature.
- the only variation with the possible temperature of the reference current obtained by the device of the invention can only come from the reference resistance Rr.
- This technology is that used in Mos technology with low drain doping called "LDD", and corresponding to a first implantation and slightly doped diffusion (N-) before the highly doped diffusion, to obtain a less abrupt junction profile, having better tensile strength.
- LDD low drain doping
- N- slightly doped diffusion
- Variations in characteristics due to the process manufacturing affect all threshold voltages as well as the value of the reference resistance.
- Vtn-Vtna threshold voltages
- the variation can only come in process from the variation of the threshold implant dose of the transistor enriched T1, since the thickness of the gate oxide is the same for both transistors and that the threshold variation due to the initial doping operation of the substrate is also found on the transistor native only on the enriched transistor.
- the variation in resistance with the process is of the same order. In the worst case, the variation of the reference current due to the process is thus of the order of ⁇ 20%, which is satisfactory.
- the polarization resistance of device could be connected directly to the voltage Vcc supply.
- the device then has the advantage of operate at very low voltage, since the path critical between supply voltage and ground is given by R1, Rr, T2.
- the current of load It is then directly dependent on the voltage Vcc supply. If we vary the voltage Vcc supply in a range from 1.6 volts to 6 volts, the charging current of the first transistor will vary greatly, with an annoying effect on the stability of the drain voltage of the first transistor and therefore on the reference current.
- a bias circuit CP which includes a transistor Mos T3, diode mounted, to impose on the resistance load R1 a transistor threshold voltage higher than the threshold voltage of transistor T1, at place of the supply voltage Vcc.
- a native P-type transistor to be able to bias the enriched transistor N T1.
- the tension of threshold of a native P transistor (about 1.5 volts) is indeed higher than the threshold voltage of a enriched N transistor (approximately 0.8 volts).
- House could very well choose an N-type transistor, more enriched than transistor T1.
- I1 (V tPna - V tN ) / R1.
- the reference current Ir (V tN -V tNna ) / Rr is then practically independent of the supply voltage Vcc.
- resistor R1 is charged from the resistor R2 and the reference resistor Rr is charged from the resistor R1. So that the current is sufficient to bias the entire device, it is therefore necessary to choose resistors with values such as R2 ⁇ R1 ⁇ Rr. And if you want to limit the current consumption of the device, you need high resistances.
- resistors with values such as R2 ⁇ R1 ⁇ Rr.
- the technology in drain extension it will be preferable to use the technology in drain extension to achieve the resistances , because it is less bulky (2000 ohms / square) than the source drain technology (typically 50 to 100 ohms / square in P + , 20 to 50 ohms / square in N +).
- this drain-extension technology is less stable in temperature.
- FIG. 2 thus represents another electronic diagram of a current reference device in integrated circuit according to an alternative embodiment of the invention, which makes it possible to use resistors of lower values.
- a Mos transistor T4 is used as a follower to apply to the load resistor R1, a bias voltage independent of the supply voltage.
- the transistor Mos T4 is of type N and connected between the supply voltage Vcc and the resistor R1.
- This transistor T4 is controlled on its gate by the voltage imposed by the series connection of a transistor T5 mounted in direct diode (gate and drain connected) and of a transistor T6 mounted in direct diode. These two transistors T5 and T6 are connected in series between the gate of the follower transistor T4 and the ground.
- the transistor T5 is preferably of the same type as the transistor T4 and with the same threshold voltage (to compensate as we will see).
- the transistor T6 is of type P and native. It could be of type N. It is only necessary that its threshold voltage is greater than that of transistor T1.
- a resistor R3 is provided between the supply voltage Vcc and the transistor T5 to bias the transistors T5 and T6 in saturated mode.
- the transistors T4 and T5 of type N are chosen to be native, in order to have the lowest threshold voltage, which allows the device to operate at the lowest possible supply voltage. In this manner is found on the terminal of the load resistor R1 connected to the transistor T4, the voltage (V F + ASPR TNNA -Vt Nna) is thus V ASPR.
- the load current of the transistor T1 is therefore (V tPna -Vt tNna ) / R1 and is therefore very stable, as already explained previously.
- Figure 3 shows a variant of the device in Figure 2, which further improves the stability of the reference current.
- the resistor R3 is directly supplied by the voltage logic supply to the circuit. If the tension diet varies, for example if it increases, we has an effect on the gate of transistor T4 follower, which will tend to increase the current of reference Ir.
- a resistor R4 is inserted between the supply voltage Vcc and terminal C of the resistance R3.
- a branch identical to the branch (T5, T6) is provided between terminal C and earth, comprising two transistors T8 and T9.
- the T8 transistor is mounted as a diode and identical to transistor T5.
- the transistor T9 is diode mounted and identical to transistor T6. In the example they are all the same type N enriched and of the same geometry (W / L). Which is important in practice is that two by two, T5 and T8, T6 and T9, are identical to have the compensation expected.
- This branch (T8, T9) serves as a limiter of the tension at node C, to make this node less dependent on variations in supply voltage Vdd.
- the node C follows the increase of the supply voltage through the resistor R4. But as soon as node C reaches a potential of the order of 2 x Vt n (sum of the threshold voltages of transistors T8 and T9 in series), the branch T8, T9, tends to maintain this level at node C: the voltage Vc will then move much less, as shown in Figure 4. Indeed T8 and T9 do not have the resistance R3 in their branch, they will pass more current (I) than T5 and T6. Thus the voltage on this branch given by Vt8 + Vt9 + Ron.I, where Ron is the equivalent pass resistance of the two transistors, will always be slightly higher than Vt5 + Vt6 (Vti is the threshold voltage of the transistor Ti).
- the device shown may very well be made in NMOS technology.
- a current Ir from which we can obtain other reference currents, by mirrored arrangements of current.
- Such an assembly is for example shown on the Figure 2: an N-type native T7 transistor is mounted in current mirror with respect to transistor T2: its gate is controlled by the gate of transistor T2.
- Another reference resistance Rr ' is connected to the drain of transistor T7 on one terminal. The other terminal is connected to the supply voltage Vcc.
- Vcc supply voltage
- the current reference device in circuit integrated according to the invention therefore offers great stability. And by design without feedback, it can be transposed from a technology of manufacturing to another without simulations, which is not not the least of its advantages.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
Description
- la figure 1 représente un mode de réalisation d'un dispositif de référence de courant selon l'invention,
- la figure 2 représente un autre mode de réalisation de l'invention,
- la figure 3 représente une variante du dispositif de la figure 2 et
- la figure 4 montre l'évolution de la tension au noeud C du dispositif de la figure 3 en fonction de la tension d'alimentation.
Claims (10)
- Dispositif de référence de courant en circuit intégré comprenant une résistance de référence (Rr), caractérisé en ce qu'il comprend un premier et un deuxième transistor Mos de même type de conductivité, le premier (T1) ayant sa grille et son drain reliés ensemble à une première borne (A) de la résistance de référence, le deuxième (T2) ayant sa grille et son drain reliés ensemble à une deuxième borne (B) de la résistance de référence, le premier transistor ayant une tension de seuil supérieure à celle du deuxième transistor et les deux transistors étant polarisés en mode saturé, la source de chacun de ces transistors étant polarisée au même potentiel que le substrat ou le caisson dans lequel le transistor est réalisé.
- Dispositif de référence selon la revendication 1, caractérisé en ce qu'il comprend un troisième transistor Mos (T3) avec une tension de seuil supérieure à celle du premier transistor et ayant sa grille reliée à son drain, de manière à appliquer au premier transistor un courant de polarisation (I1) proportionnel à la différence des tensions de seuil desdits premier et troisième transistors au moyen d'une résistance de polarisation (R1) connectée entre le premier et le troisième transistor.
- Dispositif de référence selon la revendication 1, caractérisé en ce que le circuit de polarisation comprend un quatrième transistor suiveur Mos (T4), connecté en série avec une première résistance (R1) pour polariser le premier transistor (T1), ledit transistor suiveur étant commandé sur sa grille par le montage série d'un cinquième et d'un sixième transistors Mos, le cinquième transistor (T5) ayant le même type de conductivité et la même tension de seuil que le transistor suiveur et étant monté en diode, et le sixième transistor Mos (T6) ayant une tension de seuil supérieure à celle du premier transistor (T1) et étant monté en diode, ces deux transistors étant polarisés en mode saturé par une deuxième résistance (R3) connectée entre le drain du transistor T5 et la tension d'alimentation Vcc.
- Dispositif selon la revendication 3, caractérisé en ce qu'il comprend une troisième résistance de polarisation (R4) intercalée entre la tension d'alimentation et la deuxième résistance (R3) à un noeud C, et un montage en série entre ce noeud C et la masse d'un septième transistor (T8) monté en diode et identique au cinquième transistor (T5) et d'un huitième transistor (T9) monté en diode identique au sixième transistor (T6).
- Dispositif selon l'une quelconque des revendications 1 à 4, caractérisé en ce que la résistance de référence (Rr) est réalisée en diffusion de type drain extension.
- Dispositif selon l'une quelconque des revendications 1 à 4, caractérisé en ce que la résistance de référence (Rr) est réalisée en diffusion de type source/drain.
- Dispositif selon la revendication 5, caractérisé en ce que les résistances de polarisation (R1, R3, R4) sont aussi réalisées en diffusion de type source/drain.
- Dispositif selon l'une quelconque des revendications précédentes, caractérisé en ce qu'il comprend en outre au moins une structure en miroir (T7) de courant par rapport au deuxième transistor (T2) pour obtenir un autre courant de référence (Ir') dans une autre résistance de référence Rr'.
- Dispositif selon la revendication 8, caractérisé en ce que l'autre résistance de référence est réalisée dans la même technologie que la première (Rr).
- Dispositif selon la revendication 8, caractérisé en ce que les transistors (T2, T7) utilisés dans la structure en miroir de courant sont à canal long.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9601168 | 1996-01-31 | ||
FR9601168A FR2744262B1 (fr) | 1996-01-31 | 1996-01-31 | Dispositif de reference de courant en circuit integre |
FR9607705A FR2744263B3 (fr) | 1996-01-31 | 1996-06-20 | Dispositif de reference de courant en circuit integre |
FR9607705 | 1996-06-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0788047A1 EP0788047A1 (fr) | 1997-08-06 |
EP0788047B1 true EP0788047B1 (fr) | 1998-10-07 |
Family
ID=26232490
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP97400209A Expired - Lifetime EP0788047B1 (fr) | 1996-01-31 | 1997-01-29 | Dispositif de référence de courant en circuit intégré |
Country Status (4)
Country | Link |
---|---|
US (1) | US5903141A (fr) |
EP (1) | EP0788047B1 (fr) |
DE (1) | DE69700031T2 (fr) |
FR (1) | FR2744263B3 (fr) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2749939B1 (fr) * | 1996-06-13 | 1998-07-31 | Sgs Thomson Microelectronics | Detecteur de gamme de tension d'alimentation dans un circuit integre |
DE69830469D1 (de) * | 1998-03-16 | 2005-07-14 | St Microelectronics Srl | Polarisationsspannungssteuerschaltung für schwebende Senke in einer integrierten Halbleiterschaltung |
US6175267B1 (en) * | 1999-02-04 | 2001-01-16 | Microchip Technology Incorporated | Current compensating bias generator and method therefor |
JP2001332696A (ja) * | 2000-05-24 | 2001-11-30 | Nec Corp | 基板電位検知回路及び基板電位発生回路 |
US6424205B1 (en) * | 2000-08-07 | 2002-07-23 | Semiconductor Components Industries Llc | Low voltage ACMOS reference with improved PSRR |
US6750699B2 (en) * | 2000-09-25 | 2004-06-15 | Texas Instruments Incorporated | Power supply independent all bipolar start up circuit for high speed bias generators |
US6433624B1 (en) | 2000-11-30 | 2002-08-13 | Intel Corporation | Threshold voltage generation circuit |
US6346803B1 (en) * | 2000-11-30 | 2002-02-12 | Intel Corporation | Current reference |
US6693332B2 (en) * | 2001-12-19 | 2004-02-17 | Intel Corporation | Current reference apparatus |
JP2003347852A (ja) * | 2002-05-24 | 2003-12-05 | Toshiba Corp | バイアス回路及び半導体装置 |
US20050003764A1 (en) * | 2003-06-18 | 2005-01-06 | Intel Corporation | Current control circuit |
US7118274B2 (en) * | 2004-05-20 | 2006-10-10 | International Business Machines Corporation | Method and reference circuit for bias current switching for implementing an integrated temperature sensor |
US7489183B2 (en) * | 2004-12-08 | 2009-02-10 | Triquint Semiconductor, Inc. | Bias control system for a power amplifier |
US7768248B1 (en) | 2006-10-31 | 2010-08-03 | Impinj, Inc. | Devices, systems and methods for generating reference current from voltage differential having low temperature coefficient |
TWI335496B (en) * | 2007-08-22 | 2011-01-01 | Faraday Tech Corp | Bandgap reference circuit |
TW200910050A (en) * | 2007-08-22 | 2009-03-01 | Faraday Tech Corp | Bandgap reference circuit |
US9092045B2 (en) * | 2013-04-18 | 2015-07-28 | Freescale Semiconductor, Inc. | Startup circuits with native transistors |
CN106527558B (zh) * | 2016-12-23 | 2018-08-07 | 长沙景美集成电路设计有限公司 | 一种低功耗的与绝对温度成正比的电流源电路 |
CN116136704A (zh) * | 2021-11-16 | 2023-05-19 | 罗姆股份有限公司 | 电流源电路 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS562017A (en) * | 1979-06-19 | 1981-01-10 | Toshiba Corp | Constant electric current circuit |
FR2494519A1 (fr) * | 1980-11-14 | 1982-05-21 | Efcis | Generateur de courant integre en technologie cmos |
IT1190325B (it) * | 1986-04-18 | 1988-02-16 | Sgs Microelettronica Spa | Circuito di polarizzazione per dispositivi integrati in tecnologia mos,particolarmente di tipo misto digitale-analogico |
US4978904A (en) * | 1987-12-15 | 1990-12-18 | Gazelle Microcircuits, Inc. | Circuit for generating reference voltage and reference current |
JPH0727424B2 (ja) * | 1988-12-09 | 1995-03-29 | 富士通株式会社 | 定電流源回路 |
JPH0690653B2 (ja) * | 1988-12-21 | 1994-11-14 | 日本電気株式会社 | トランジスタ回路 |
CA2066929C (fr) * | 1991-08-09 | 1996-10-01 | Katsuji Kimura | Circuit capteur de temperature et circuit a courant constant |
JP2531104B2 (ja) * | 1993-08-02 | 1996-09-04 | 日本電気株式会社 | 基準電位発生回路 |
JPH07106869A (ja) * | 1993-09-30 | 1995-04-21 | Nec Corp | 定電流回路 |
US5739682A (en) * | 1994-01-25 | 1998-04-14 | Texas Instruments Incorporated | Circuit and method for providing a reference circuit that is substantially independent of the threshold voltage of the transistor that provides the reference circuit |
FR2721119B1 (fr) * | 1994-06-13 | 1996-07-19 | Sgs Thomson Microelectronics | Source de courant stable en température. |
JP3374541B2 (ja) * | 1994-08-22 | 2003-02-04 | 富士電機株式会社 | 定電流回路の温度依存性の調整方法 |
-
1996
- 1996-06-20 FR FR9607705A patent/FR2744263B3/fr not_active Expired - Fee Related
-
1997
- 1997-01-29 EP EP97400209A patent/EP0788047B1/fr not_active Expired - Lifetime
- 1997-01-29 DE DE69700031T patent/DE69700031T2/de not_active Expired - Fee Related
- 1997-01-30 US US08/791,383 patent/US5903141A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69700031T2 (de) | 1999-02-25 |
US5903141A (en) | 1999-05-11 |
DE69700031D1 (de) | 1998-11-12 |
EP0788047A1 (fr) | 1997-08-06 |
FR2744263B3 (fr) | 1998-03-27 |
FR2744263A1 (fr) | 1997-08-01 |
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