EP0729273A2 - Dispositif pour engendrer une tension de compensation pour un affichage à images multiples et appareil d'affichage vidéo utilisant un tel dispositif - Google Patents

Dispositif pour engendrer une tension de compensation pour un affichage à images multiples et appareil d'affichage vidéo utilisant un tel dispositif Download PDF

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Publication number
EP0729273A2
EP0729273A2 EP95309314A EP95309314A EP0729273A2 EP 0729273 A2 EP0729273 A2 EP 0729273A2 EP 95309314 A EP95309314 A EP 95309314A EP 95309314 A EP95309314 A EP 95309314A EP 0729273 A2 EP0729273 A2 EP 0729273A2
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EP
European Patent Office
Prior art keywords
compensation
picture
multipicture
video signal
compensation voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP95309314A
Other languages
German (de)
English (en)
Other versions
EP0729273A3 (fr
Inventor
Hiroshi Ando
Atsuhisa Kageyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of EP0729273A2 publication Critical patent/EP0729273A2/fr
Publication of EP0729273A3 publication Critical patent/EP0729273A3/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/45—Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/18—Generation of supply voltages, in combination with electron beam deflecting
    • H04N3/19—Arrangements or assemblies in supply circuits for the purpose of withstanding high voltages
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/141—Beam current control means
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/16—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
    • H04N5/165—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level to maintain the black level constant
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/16—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
    • H04N5/18—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit
    • H04N5/185—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit for the black level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/20—Circuitry for controlling amplitude response
    • H04N5/202—Gamma control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/57—Control of contrast or brightness
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/20—Circuitry for controlling amplitude response

Definitions

  • the present invention relates to a compensation voltage generating apparatus for multipicture display to simultaneously display a plurality of pictures on one display device and especially relates to a video display apparatus to display a plurality of pictures on a display device at the same time and relates to an automatic brightness limiter (ABL) and an automatic contrast limiter (ACL) of a luminance signal adjusting circuit which keeps the brightness of each picture constant and a gamma compensation circuit and a black stretch compensation circuit for a video signal, especially at a multipicture display television receiver.
  • ABL automatic brightness limiter
  • ACL automatic contrast limiter
  • an ABL/ACL circuit is particularly necessary for automatically adjusting the blackest level and the amplitude of a brightness signal against EHT variation and for reducing a load in an EHT circuit.
  • Japanese Patent Laid-Open no.5-167946 is proposed.
  • FIG. 1 is a block diagram of a signal processing circuit for a parent/child two picture display which compensates the picture, using an ABL/ACL circuit having reverse characteristics between the parent picture and the child picture.
  • An ABL/ACL compensation signal coming from an ABL/ACL compensation voltage generating circuit 107 is turned its polarity at an inverter 108 and is superimposed on a brightness/contrast adjusting voltage 105 at a first adder 109.
  • a signal processing circuit for a child picture 103 is supplied with a child picture signal 102, adjusts a brightness/contrast of the child picture signal by a signal from first adder 109 and at the same time compensates an ABL/ACL characteristic.
  • An ABL/ACL compensation signal coming from an ABL/ACL compensation voltage generating circuit 107 is lead to a second adder 110 without turning its polarity and is superimposed on a brightness/contrast adjusting voltage 106 at second adder 110.
  • a synthesizing circuit 111 synthesizes a parent picture signal 101 and a compensated child picture signal from signal processing circuit for a child picture 103.
  • a signal processing circuit 112 adds a signal coming from second adder 110 on a video signal in which the parent picture and the child picture are synthesized and is coming from synthesizing circuit 111 and outputs a parent/child two picture signal which the brightness/contrast is adjusted and the ABL/ACL characteristic is compensated.
  • an ABL/ACL compensation voltage is applied from ABL/ACL voltage generating circuit 107 to the picture after two picture synthesis, because an inverse compensation voltage is applied to a signal processing circuit 103 for a child picture by inverter 108, an inverse ABL/ACL compensation is applied to the child picture and the brightness reduction of the child picture is reduced when the parent picture is bright and an ABL/ACL compensation is applied.
  • the ABL/ACL compensation voltage becomes a medium value.
  • the present invention aims to obtain an optimum picture characteristic by sharing a compensation voltage of a picture quality compensation circuit such as ABL/ACL compensation, gamma compensation and black stretch compensation according to a ratio of average picture level (APL) of each composing picture of a multipicture and by compensating each picture according to the shared compensation voltages.
  • a picture quality compensation circuit such as ABL/ACL compensation, gamma compensation and black stretch compensation according to a ratio of average picture level (APL) of each composing picture of a multipicture
  • a multipicture compensation voltage generating apparatus in accordance with the present invention includes a plurality of APL detection circuits for detecting an APL value of each picture independently and a compensation voltage sharing circuit for varying the compensation degree according to the outputs of the APL detection circuits.
  • FIG. 1 is a block diagram of an ABL/ACL circuit in accordance with the prior art.
  • FIG. 2(a1) illustrates a two picture display in accordance with the prior art.
  • FIG. 2(a2) is a brightness waveform of a two picture display video signal in accordance with the prior art.
  • FIG. 2(b) is a sharing characteristic of ABL/ACL compensation voltages shared according to the ratio of the APL values of two pictures in accordance with an exemplary embodiment of the present invention.
  • FIG. 2(c1) illustrates a two picture display compensated by the circuit shown in FIG. 4.
  • FIG. 2(c2) is a brightness waveform of a two picture display video signal after compensation in accordance with an exemplary embodiment.
  • FIG. 3 is a block diagram of a multipicture compensation voltage generating circuit of an APL adaptive type in accordance with an exemplary embodiment of the present invention.
  • FIG. 4 is a block diagram of a video display apparatus using an ABL/ACL compensation circuit for a multipicture of an APL adaptive type in accordance with an exemplary embodiment of the present invention.
  • FIG. 5 is a block diagram of a compensation voltage sharing circuit 006 used in a compensation voltage generating circuit for a multipicture of an APL adaptive type in accordance with an exemplary embodiment of the present invention.
  • FIG. 6 is a block diagram of a gamma compensation circuit for a multipicture of an APL adaptive type in accordance with an exemplary embodiment of the present invention.
  • FIG. 7 is a block diagram of a black stretch compensation circuit for a multipicture of an APL adaptive type in accordance with an exemplary embodiment of the present invention.
  • FIG. 3 is a block diagram of a multipicture compensation voltage generating circuit of an APL adaptive type in accordance with an exemplary embodiment of the present invention. Explanation is given about two picture display for simplicity.
  • a first APL detection circuit 003 detects an APL of the first video signal (for example, parent picture signal) 001 and a second APL detection circuit 004 detects an APL of the second video signal (for example, child picture signal) 002.
  • a compensation voltage generating circuit 005 generates a compensation voltage, for example, an ABL/ACL compensation voltage.
  • a compensation voltage sharing circuit 006 shares the compensation voltage from compensation voltage generating circuit 005 according to the ratio of the APL values detected at first and second APL detection circuits 003 and 004, respectively and outputs a first compensation voltage 007 and a second compensation voltage 008, respectively.
  • the APL values of first video signal 001 and second video signal 002 are detected and the compensation voltage from compensation voltage generating circuit 005 can be shared at compensation voltage sharing circuit 006 according to the ratio of these detected APL values.
  • FIG. 4 is a block diagram of an ABL/ACL compensation circuit of an APL adaptive type.
  • a first APL detection circuit 013 detects an APL of the first video signal (for example, parent picture signal) 011 and a second APL detection circuit 014 detects an APL of the second video signal (for example, child picture signal) 012.
  • An ABL/ACL compensation voltage is made at an EHT circuit 015.
  • a compensation voltage sharing circuit 016 shares the compensation voltage outputted from EHT circuit 015 according to the ratio of the APL values detected at first APL detection circuits 013 and second APL detection circuit 014 and outputs a first compensation voltage and a second compensation voltage.
  • a first adder 023 superimposes the first compensation voltage shared at compensation voltage sharing circuit 016 on a first brightness/contrast adjusting voltage 021 and outputs to a first signal processing circuit 017 as a first brightness/contrast adjusting voltage 019 superimposed with first ABL/ACL compensation voltage.
  • a second adder 024 superimposes the second compensation voltage shared at compensation voltage sharing circuit 016 on a second brightness/contrast adjusting voltage 022 and outputs to a second signal processing circuit 018 as a second brightness/contrast adjusting voltage 020 superimposed with second ABL/ACL compensation voltage.
  • First signal processing circuit 017 controls first video signal 011 by first brightness/contrast adjusting voltage 019 superimposed with first ABL/ACL compensation voltage from first adder 023.
  • Second signal processing circuit 020 controls second video signal 012 by second brightness/contrast adjusting voltage 020 superimposed with second ABL/ACL compensation voltage from second adder 024.
  • the video signal outputted from first signal processing circuit 017 and the video signal outputted from second signal processing circuit 018 are synthesized at a multipicture synthesizing circuit 025 and the synthesized signal is amplified at a succeeding amplification circuit 026 and drives a CRT 027.
  • ABL/ACL compensation circuit of an APL adaptive type configurated as shown in FIG. 4 The performance of a video display apparatus using an ABL/ACL compensation circuit of an APL adaptive type configurated as shown in FIG. 4 is explained below referring to FIG. 2.
  • ABL/ACL compensation is given equally, that is, the compensation is insufficient for the brighter picture A and white saturation remains and on the other hand, the compensation is excessive for the darker picture B and the black level sinks too much.
  • the ABL/ACL compensation voltage supplied from the EHT circuit can be shared to the pictures A and B according to the ratio of the APL values of the pictures A and B as shown in the characteristic curves of FIG. 2(b).
  • the ABL/ACL compensation voltage for each picture can be independently controlled and it is possible to reduce white saturation at a bright scene and black sink at a dark scene as shown in FIG. 2(c1) and FIG. 2(c2).
  • the broken line indicates a state without compensation and the real line indicates a state with compensation according to an exemplary embodiment of the present invention.
  • FIG. 5 A concrete example of a multipicture compensation voltage generating circuit of an APL adaptive type shown in FIG. 3 is explained referring to FIG. 5.
  • APL detection voltages 031 and 032 of the first and the second pictures detected at first and second APL detection circuits 013 and 014 shown in FIG. 4 are inputted to two bases of a differential amplifier 034, respectively.
  • a compensation current 033 such as EHT circuit current for ABL/ACL compensation supplied from EHT circuit 015 of FIG. 4 is supplied to a common emitter of differential amplifier 034.
  • the block 035 is a mirror circuit and first and second compensation voltages 037 and 038 are outputted from each of two collector resistors 036.
  • first and second compensation voltages 037 and 038 are inputted to first and second adders 023 and 024, respectively.
  • APL detection voltages 031 and 032 are compared at differential amplifier 034, the compensation currents are converted into voltages at resistors 036 for generating a compensation voltage after passing through mirror circuit 035.
  • first APL detection voltage 031 is larger than second APL detection voltage 032
  • first compensation voltage output 037 is larger than second compensation voltage output 038 and each picture has a different ABL/ACL characteristic.
  • FIG. 6 is a block diagram of a gamma compensation circuit used in a multipicture compensation voltage generating circuit in accordance with an exemplary embodiment of the present invention.
  • a first APL detection circuit 043 detects an APL of the first video signal (for example, parent picture signal) 041 and a second APL detection circuit 044 detects an APL of the second video signal (for example, child picture signal) 042.
  • a compensation voltage sharing circuit 046 shares the gamma compensation voltage outputted from gamma compensation voltage generating circuit 045 according to the ratio of the APL values detected at first APL detection circuit 043 and second APL detection circuit 044 and the shared gamma compensation voltages are supplied to a first gamma compensation circuit 047 and a second gamma compensation circuit 048.
  • First gamma compensation circuit 047 and second gamma compensation circuit 048 add the compensation voltages shared at compensation voltage sharing circuit 046 to first and second video signals 041 and 042 and output a gamma compensated video signal 051 for the first picture (parent picture) and a gamma compensated video signal 052 for the second picture (child picture), respectively.
  • the gamma compensated video signals of the first picture and the second picture are synthesized at multipicture synthesizing circuit 025 shown in FIG. 4 and the synthesized video signal is supplied to CRT 027 after passing through amplification circuit 026 and is displayed on the screen of CRT 027 as a multipicture in which each picture is independently compensated.
  • FIG. 7 is a block diagram of a black stretch compensation circuit used in a multipicture compensation voltage generating circuit in accordance with an exemplary embodiment of the present invention.
  • a first APL detection circuit 063 detects an APL of the first video signal (for example, parent picture signal) 061 and a second APL detection circuit 064 detects an APL of the second video signal (for example, child picture signal) 062.
  • a compensation voltage sharing circuit 066 shares a black stretch compensation voltage outputted from black stretch compensation voltage generating circuit 065 according to the ratio of the APL values detected at first APL detection circuit 063 and second APL detection circuit 064 and the shared black stretch compensation voltages are supplied to a first black stretch compensation circuit 067 and a second black stretch compensation circuit 068.
  • First black stretch compensation circuit 067 and second black stretch compensation circuit 068 add the compensation voltages shared at compensation voltage sharing circuit 066 to first and second video signals 061 and 062 and output a black stretch compensated video signal 071 for the first picture (parent picture) and a black stretch compensated video signal 072 for the second picture (child picture), respectively.
  • the black stretch compensated video signals of the first and the second pictures are synthesized at multipicture synthesizing circuit 025 shown in FIG. 4 and the synthesized video signal is supplied to CRT 027 after passing through amplification circuit 026 and is displayed on the screen of CRT 027 as a multipicture in which each picture is independently compensated.
  • an optimal compensation characteristic such as ABL/ACL compensation is obtained for each picture composing a multipicture by a configuration including a plurality of APL detection circuits for detecting APL values of pictures composing a multipicture and a compensation voltage sharing circuit for sharing a compensation voltage according to the ratio of the detected APL values.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Receiver Circuits (AREA)
  • Picture Signal Circuits (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP95309314A 1995-02-27 1995-12-20 Dispositif pour engendrer une tension de compensation pour un affichage à images multiples et appareil d'affichage vidéo utilisant un tel dispositif Withdrawn EP0729273A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP38327/95 1995-02-27
JP3832795 1995-02-27

Publications (2)

Publication Number Publication Date
EP0729273A2 true EP0729273A2 (fr) 1996-08-28
EP0729273A3 EP0729273A3 (fr) 1996-12-04

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EP95309314A Withdrawn EP0729273A3 (fr) 1995-02-27 1995-12-20 Dispositif pour engendrer une tension de compensation pour un affichage à images multiples et appareil d'affichage vidéo utilisant un tel dispositif

Country Status (5)

Country Link
US (1) US5841486A (fr)
EP (1) EP0729273A3 (fr)
KR (1) KR960033069A (fr)
CN (1) CN1135140A (fr)
AU (1) AU4056295A (fr)

Cited By (3)

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WO1998048571A1 (fr) * 1997-04-23 1998-10-29 Thomson Consumer Electronics, Inc. Regulation du niveau video selon la region et le contenu des informations affichees
EP1024663A2 (fr) * 1999-01-29 2000-08-02 Canon Kabushiki Kaisha Dispositif de traitement d'image
US6809776B1 (en) 1997-04-23 2004-10-26 Thomson Licensing S.A. Control of video level by region and content of information displayed

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US6008859A (en) * 1996-07-31 1999-12-28 Sanyo Electric Co., Ltd. Image data processing apparatus
KR100251543B1 (ko) * 1997-07-28 2000-04-15 구본준 계조보정용 전압공급장치
ES2207953T3 (es) 1998-07-20 2004-06-01 Thomson Licensing S.A. Sistema de navegacion para sistema de television digital multicanal.
US6556253B1 (en) * 1999-10-26 2003-04-29 Thomson Licensing S.A. Multi-window picture adjustment arrangement for a video display
US6753929B1 (en) * 2000-06-28 2004-06-22 Vls Com Ltd. Method and system for real time motion picture segmentation and superposition
KR100748493B1 (ko) * 2001-03-15 2007-08-13 엘지전자 주식회사 감마 조정을 통한 화질 최적화 방법
JP3987296B2 (ja) * 2001-03-21 2007-10-03 株式会社ソニー・コンピュータエンタテインメント 情報処理方法、情報処理プログラムを情報処理装置に実行させる媒体、プログラム実行装置、情報処理プログラム
US6876248B2 (en) * 2002-02-14 2005-04-05 Rambus Inc. Signaling accommodation
JP3720813B2 (ja) * 2003-02-26 2005-11-30 キヤノン株式会社 映像表示装置
KR100541731B1 (ko) * 2003-07-03 2006-01-10 삼성전자주식회사 Ｃｒｔ 디스플레이장치 및 그 제어방법
KR101362169B1 (ko) * 2008-09-24 2014-02-13 엘지디스플레이 주식회사 감마 보정 시스템 및 그의 보정방법
JP5221780B1 (ja) * 2012-02-03 2013-06-26 シャープ株式会社 映像表示装置およびテレビ受信装置

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PATENT ABSTRACTS OF JAPAN vol. 18, no. 369 (E-1576), 12 July 1994 & JP-A-06 098273 (HITACHI LTD), 8 April 1994, *
PATENT ABSTRACTS OF JAPAN vol. 95, no. 011 & JP-A-07 298096 (FUJITSU GENERAL LTD), 10 November 1995, *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998048571A1 (fr) * 1997-04-23 1998-10-29 Thomson Consumer Electronics, Inc. Regulation du niveau video selon la region et le contenu des informations affichees
US6809776B1 (en) 1997-04-23 2004-10-26 Thomson Licensing S.A. Control of video level by region and content of information displayed
EP1024663A2 (fr) * 1999-01-29 2000-08-02 Canon Kabushiki Kaisha Dispositif de traitement d'image
EP1024663A3 (fr) * 1999-01-29 2003-07-23 Canon Kabushiki Kaisha Dispositif de traitement d'image
US6831634B1 (en) 1999-01-29 2004-12-14 Canon Kabushiki Kaisha Image processing device
US7079129B2 (en) 1999-01-29 2006-07-18 Canon Kabushiki Kaisha Image processing device

Also Published As

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AU4056295A (en) 1996-09-05
US5841486A (en) 1998-11-24
EP0729273A3 (fr) 1996-12-04
KR960033069A (ko) 1996-09-17
CN1135140A (zh) 1996-11-06

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