EP0694899B1 - Anzeigevorrichtung zur Anzeige von Videosignalen aus verschiedenen Videonormen - Google Patents

Anzeigevorrichtung zur Anzeige von Videosignalen aus verschiedenen Videonormen Download PDF

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Publication number
EP0694899B1
EP0694899B1 EP19950305079 EP95305079A EP0694899B1 EP 0694899 B1 EP0694899 B1 EP 0694899B1 EP 19950305079 EP19950305079 EP 19950305079 EP 95305079 A EP95305079 A EP 95305079A EP 0694899 B1 EP0694899 B1 EP 0694899B1
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EP
European Patent Office
Prior art keywords
lines
video signal
display panel
display device
standard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19950305079
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English (en)
French (fr)
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EP0694899A1 (de
Inventor
Masumi C/O Sony Corporation Hirano
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Sony Corp
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Sony Corp
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Publication date
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Publication of EP0694899A1 publication Critical patent/EP0694899A1/de
Application granted granted Critical
Publication of EP0694899B1 publication Critical patent/EP0694899B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0414—Vertical resolution change

Definitions

  • the present invention relates to a display device which comprises a display panel, a decoder/driver for supplying a video signal thereto, and a timing generator for controlling the driving of the display panel. And more particularly, the invention relates to a display device capable of inputting a video signal, which conforms with the PAL standard, to a display panel designed in conformity with, e.g., the NTSC standard.
  • some other systems have been adopted in foreign countries, such as the PAL standard and the SECAM standard used in Europe.
  • the PAL system for example, one frame is composed of 625 lines.
  • EP 0,408,347-A discloses a display device in accordance with the pre-characterising portion of claim 1.
  • this display device when lines of a video signal are thinned out to be reduced at a predetermined rate in case a video signal of the PAL system for example is inputted to a display panel designed for the NTSC system, different lines are thinned out to be reduced every field to consequently alleviate an undesired phenomenon that the video image is seen to be discontinuous.
  • a display device comprising:
  • the display panel has a plurality of pixels arranged to form a matrix in conformity with the NTSC standard of a first video signal composed of 525 lines.
  • the signal source inputs to the display panel a second video signal of 625 lines conforming with the PAL standard.
  • the timing means reduces surplus lines at a rate of one per six or seven lines while changing the positions of the lines to be reduced.
  • the timing means alternately interchanges the positions of the lines reduced in a first field and a second field.
  • the timing means may be so modified as to cyclically shift the positions of the lines reduced in each cycle consisting of three or more fields.
  • an active matrix liquid crystal display panel which has a plurality of pixels each comprising a pixel electrode, a counter electrode disposed opposite to the pixel electrode with a gap, a liquid crystal held in the gap, and a switching element for driving the pixel electrode.
  • Fig. 1 is a block diagram showing a basic constitution of the display device according to the present invention.
  • this display device comprises a display panel 1, a signal source for supplying a video signal thereto, and a timing means for controlling the driving of the display panel 1.
  • a decoder/driver 2 is employed as the signal source, and a combination of a timing generator 3 and a line reduction sequencer 3a is employed as the timing means.
  • the display panel 1 has a plurality of pixels 4, a vertical driving circuit 5 and a horizontal driving circuit 6.
  • the plurality of pixels 4 are arranged to form a matrix in conformity with the standard (e.g., NTSC standard) of a first video signal including a predetermined number of lines per field.
  • the vertical driving circuit 5 sequentially selects the pixels of one row, and the horizontal driving circuit 6 writes a video signal of one line in the selected pixels of one row.
  • the decoder/driver 2 is capable of inputting to the display panel 1 a second video signal whose number of lines per field is greater than that of the first video signal.
  • the timing generator 3 controls the timing of the sequential selection performed by the vertical driving circuit 5 and reduces, at a predetermined rate, surplus lines included in the second video signal inputted to the display panel 1.
  • One of the characteristic requisites of the present invention is such that the line reduction sequencer 3a controls the timing generator 3 in such a manner as to change the positions of the lines to be reduced every field. More specifically, the line reduction sequencer 3a supplies to the timing generator 3 a reduction sequence signal which designates the positions of lines to be reduced every field. And in response to the reduction sequence signal, the timing generator 3 halts the operations of both the vertical driving circuit 5 and the horizontal driving circuit 6 under control to thereby interrupt display of the relevant line.
  • the display panel 1 has a plurality of pixels arranged to form a matrix in conformity with the NTSC standard of a first video signal composed of 525 lines.
  • the decoder/driver 2 inputs to the display panel 1 a second video signal of 625 lines conforming with the PAL standard.
  • the timing generator 3 reduces surplus lines at a rate of one per six or seven lines.
  • the line reduction sequencer 3a supplies a predetermined reduction sequence signal to the timing generator 3 and reduces the surplus lines while changing the positions thereof every field.
  • the display panel 1 is equipped with a screen conforming with the NTSC standard. And a multiplicity of pixels 4 are arranged to form a matrix on this screen.
  • the display panel 1 performs its ordinary display operation when a video signal of the NTSC standard is inputted thereto, or performs predetermined reduction display driving when a video signal Vsig of the PAL standard is inputted.
  • the display panel 1 is of full color type and receives a video signal Vsig separated into three primary colors R, G and B.
  • the display panel 1 has a vertical driving circuit 5 to sequentially select the pixels 4 row by row, and also has a horizontal driving circuit 6 to write the video signal Vsig of one line (one horizontal period) in the selected pixels 4 of one row.
  • the vertical driving circuit 5 performs an operation of reducing a predetermined number of surplus lines from the video signal Vsig of the PAL standard under timing control and then displays the signal thus processed.
  • the decoder/driver 2 has a decoder section to receive a supply voltage of, e.g., 5V and a driver section to receive a supply voltage of 12V.
  • the decoder section decodes a composite video signal VIDEO inputted from an external device and extracts a luminance signal and a chroma signal therefrom while transferring to the timing generator 3 a synchronizing signal SYNC separated from the composite video signal VIDEO.
  • the driver section separates the AC video signal Vsig into R, G and B components and supplies the same to the display panel 1 in response to an inversion signal FRP inputted from the timing generator 3.
  • the timing generator 3 On the basis of the synchronizing signal SYNC, the timing generator 3 generates various timing signals and supplies the same to the display panel 1 to control the timing thereof. More specifically, first timing signals (vertical start signal VST, vertical clock signals VCK1 and VCK2) are supplied to the vertical driving circuit 5 to sequentially select pixels row by row. Meanwhile second timing signals (horizontal start signal HST, horizontal clock signals HCK1 and HCK2) are supplied to the horizontal driving circuit 6 to write the video signal Vsig of one line in the selected pixels 4 of one row. And a third timing signal, which is a reduction mask signal ENB, is supplied to the vertical driving circuit 5 so as to be used for line reduction driving.
  • first timing signals vertical start signal VST, vertical clock signals VCK1 and VCK2
  • second timing signals horizontal start signal HST, horizontal clock signals HCK1 and HCK2
  • a third timing signal which is a reduction mask signal ENB, is supplied to the vertical driving circuit 5 so as to be used for line reduction driving.
  • the line reduction sequencer 3a supplies to the timing generator 3 a reduction sequence signal which designates the positions of lines to be reduced every field. Then, in response to this reduction sequence signal, the timing generator 3 adjusts the timing to apply each timing signal, such as VST, HST or ENB, to the display panel 1.
  • the display panel also receives a reference voltage VCOM applied to the counter electrode.
  • Fig. 2 is a typical diagram showing an exemplary operation of line reduction performed in the display device of the present invention.
  • the positions of lines to be reduced are alternately interchanged in a first field and a second field. More specifically, in a first field (odd field), there are reduced 2nd line, 8th line, 14th line and so forth. Thus, the reduction is executed at such a rate that one line is thinned out of six lines. And in a second field (even field), there are reduced 5th line, 11th line and so forth.
  • Fig. 3 typically shows another exemplary operation of line reduction.
  • the positions of lines to be reduced are cyclically shifted in three or more fields which constitute a unitary cycle. More specifically, the positions of lines to be reduced in a unitary cycle of six fields are shifted cyclically at such a rate that one line is thinned out of six lines.
  • a first field are reduced 1st line, 7th line, 13th line and so forth; in a second field are reduced 4th line, 10th line and so forth; in a third field are reduced 2nd line, 8th line, 14th line and so forth; in a fourth field are reduced 5th line, 11th line and so forth; in a fifth field are reduced 3rd line, 9th line and so forth; and in a sixth field are reduced 6th line, 12th line and so forth.
  • Each of such line reduction sequences is designated by a reduction sequence signal outputted from the line reduction sequencer 3a.
  • Fig. 4 is a block diagram showing a concrete constitution of the display panel included in Fig. 1.
  • the display panel 1 is equipped with a regular screen 11 where a multiplicity of pixels 4 are arranged to form a matrix.
  • This pixel 4 is composed of a minute liquid crystal cell LC.
  • a gate line X in a row and a signal line Y in a column are so disposed as to intersect each other, and an individual pixel 4 is provided at the intersection of such two lines.
  • a thin-film transistor Tr is also formed integrally to serve as a switching element for on/off driving the pixel.
  • a gate electrode of the thin-film transistor Tr is connected to a corresponding gate line X, while a source electrode thereof is connected to a corresponding signal line Y, and a drain electrode thereof is connected to a pixel electrode disposed at one end of a corresponding liquid crystal cell LC.
  • the other end of the liquid crystal cell LC is connected to a counter electrode, and a desired reference voltage VCOM is applied thereto.
  • Each gate line X is connected to the vertical driving circuit 5.
  • each signal line Y is connected via a horizontal switch HSW to a video line 7 and is supplied with the video signal Vsig.
  • the individual horizontal switch HSW is turned on or off under control of the horizontal driving circuit 6.
  • the vertical driving circuit 5 operates in accordance with the input signals VST, VCK1 and VCK2 received via a level converter circuit 8. That is, the vertical driving circuit 5 successively transfers vertical start signals VST in response to the vertical clock signals VCK1 and VCK2 of mutually opposite phases to thereby produce gate pulses ⁇ 1 , ⁇ 2 , ..., ⁇ N in individual stages and then supplies such pulses to the individual gate lines X respectively. And in response to such gate pulses ⁇ , the thin-film transistors Tr are switched on or off to sequentially select the pixels 4 of one row.
  • the horizontal driving circuit 6 operates in accordance with the input signals HST, HCK1 and HCK2 received also via the level converter circuit 8. That is, the horizontal driving circuit 6 successively transfers horizontal start signals HST in response to the horizontal clock signals HCK1 and HCK2 of mutually opposite phases to thereby produce sampling pulses.
  • the horizontal switch HSW is controlled to be turned on or off in accordance with the sampling pulses, whereby the video signal Vsig supplied via the video line 7 is sampled to each signal line Y.
  • the video signal Vsig thus sampled is written in the liquid crystal pixel 4 via the thin-film transistor Tr placed in its on-state. In this manner, the horizontal driving circuit 6 writes the video signal Vsig of one horizontal period sequentially in the selected pixels 4 of one row.
  • the display panel 1 is further equipped with a gate circuit 9 between the vertical driving circuit 5 and the gate line X.
  • the gate circuit 9 consists of a two-input one-output AND gate element 10 provided in each stage of the gate line X.
  • the output terminal of each AND gate element 10 is connected to the corresponding gate line X.
  • One input terminal of each AND gate element 10 is connected to the corresponding stage of the vertical driving circuit 5, while the other input terminal thereof is supplied with a mask signal ENB via the level converter circuit 8.
  • Fig. 5 shows an exemplary concrete constitution of the vertical driving circuit 5 included in Fig. 4.
  • the vertical driving circuit 5 consists of D-type flip flops (DFF) connected in multiple stages. In this diagram, merely two DFF corresponding to an Ath stage and an (A + 1)th stage are shown to facilitate understanding.
  • the vertical driving circuit 5 transfers a vertical start signal to each stage in response to the vertical clock signals VCK1 and VCK2, thereby outputting gate pulses.
  • a gate circuit 9 is inserted between the vertical driving circuit 5 and the gate line X.
  • the gate circuit 9 consists of an AND gate element 10 disposed in correspondence to each stage. One input terminal of each AND gate element 10 is supplied with a pulse from the corresponding DFF, while the other input terminal thereof is supplied with a mask signal ENB. And the output terminal of each AND gate terminal 10 is connected to the corresponding gate line X.
  • Fig. 7 is a timing chart showing the waveforms of gate pulses outputted successively from the vertical driving circuit 5.
  • the vertical scanning is brought to a temporal halt only during a period of 1H after output of the gate pulse ⁇ A from the Ath stage, and then line reduction is performed. During this period, the video signal is transferred ineffectively and is therefore not written in any pixel. And after the lapse of such line reduction period, a gate pulse ⁇ A+1 is outputted from the next stage.
  • the video signal can be reduced by temporarily halting the vertical scanning at a predetermined rate.
  • Fig. 8 is a timing chart of signals showing an operation to write a video signal.
  • a vertical start signal VST is inputted to the vertical driving circuit from the timing generator.
  • the vertical start signal VST is sequentially transferred every 1H in synchronism with a vertical clock signal VCK1, whereby the aforementioned gate pulse is outputted.
  • a horizontal start signal HST is inputted every 1H to the horizontal driving circuit from the timing generator, so that a video signal of one line can be sequentially written in the pixels of one row.
  • a vertical start signal VST is inputted to the vertical driving circuit from the timing generator.
  • the vertical start signal VST is sequentially transferred every 1H in synchronism with a vertical clock signal VCK1, whereby a gate pulse is outputted.
  • a horizontal start signal HST is inputted every 1H to the horizontal driving circuit from the timing generator, so that 1st to 3rd lines of the video signal are written successively in the pixels of 1st to 3rd rows.
  • the clock signal VCK1 is temporarily interrupted and, in response thereto, the mask signal ENB is turned to a low level only during a period of 1H. Due to the timing control described above, the vertical scanning is brought to a temporal halt, and the 4th line is transferred ineffectively during such a halt. Thereafter the ordinary operation is resumed, and then 5th, 6th, 7th and 8th lines are written successively in the pixels of the corresponding rows. And an inversion signal FRP is synchronized with such line reduction timing, so that accurate 1H inversion driving is rendered possible even after the line reduction.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Television Systems (AREA)

Claims (7)

  1. Anzeigevorrichtung mit einem Flüssigkristallanzeigefeld (1), welches eine Vielzahl von Pixeln (4) aufweist, die zur Bildung einer Matrix gemäß dem Standard eines ersten Videosignals angeordnet sind, das eine bestimmte Anzahl von Zeilen pro Teilbild aufweist,
    mit einer Vertikal-Treiberschaltung (5) zur sequentiellen Auswahl der Pixel (4) einer Zeile,
    mit einer Horizontal-Treiberschaltung (6) zum Schreiben des Videosignals in den ausgewählten Pixeln (4) einer Zeile,
    mit einer Signalquelle zur Abgabe des ersten Videosignals an das genannte Flüssigkristallanzeigefeld (1), wobei die betreffende Signalquelle imstande ist, dem genannten Flüssigkristallanzeigefeld (1) ein zweites Videosignal zuzuführen, dessen Anzahl an Zeilen pro Teilbild größer ist als jene, die in dem Standard des genannten ersten Videosignals vorgeschrieben ist,
    und mit einer Einrichtung (3) zur Steuerung der Ansteuerung des betreffenden Flüssigkristallanzeigefeldes (1), wobei die betreffende Einrichtung (3) zur Steuerung des Zeitpunkts bzw. der Zeit der sequentiellen Auswahl durch die genannte Vertikal-Treiberschaltung (5) dient, um dadurch in dem zweiten Videosignal, welches dem genannten Anzeigefeld zugeführt ist, enthaltene überschüssige Zeilen zu verringern, und ferner dazu dient, die Positionen der je Teilbild zu verringernden Zeilen zu ändern,
    dadurch gekennzeichnet,
    dass die genannte Einrichtung (3) ein Teilbild-Umkehr-Impuls-Signal (FRP) zur Umkehr der Polarität des genannten Videosignals zwischen aufeinanderfolgenden horizontalen Zeilen abgibt
    und dass die genannte Einrichtung (3) das genannte Teilbild-Umkehr-Impuls-Signal (FRP) in Synchronismus mit der Zeilenverringerungszeit abgibt, derart, dass eine genaue 1H-Umkehr-Steuerung sogar nach der Zeilenverringerung hervorgerufen wird.
  2. Anzeigevorrichtung nach Anspruch 1, wobei die genannte Vertikal-Treiberschaltung (5) und die genannte Horizontal-Treiberschaltung (6) in dem genannten Anzeigefeld (1) integral gebildet sind.
  3. Anzeigevorrichtung nach Anspruch 1 oder 2, wobei das genannte Anzeigefeld (1) eine Vielzahl von Pixeln (4) aufweist, die gemäß dem Standard eines ersten Videosignals angeordnet sind, welches aus 525 Zeilen besteht,
    dass die genannte Signalquelle dem genannten Anzeigefeld (1) ein zweites Videosignal aus 625 Zeilen gemäß einem bestimmten Standard zuführt
    und dass die genannte Steuereinrichtung (3) die überschüssigen Zeilen mit einer Rate von 1 pro 6 oder 7 Zeilen verringert, während die Positionen der zu verringernden Zeilen geändert werden.
  4. Anzeigevorrichtung nach Anspruch 3, wobei der Standard des genannten ersten Videosignals der NTSC-Standard ist und wobei der Standard des genannten zweiten Videosignals der PAL- oder SECAM-Standard ist.
  5. Anzeigevorrichtung nach Anspruch 1, 2, 3 oder 4, wobei die genannte Steuereinrichtung (3) abwechselnd die Positionen der in einem ersten Teilbild und in einem zweiten Teilbild verringerten Zeilen vertauscht.
  6. Anzeigevorrichtung nach Anspruch 1, 2, 3 oder 4, wobei die genannte Steuereinrichtung (3) die Positionen der in jedem aus drei oder mehr Teilbildern bestehenden Zyklus verringerten Zeilen zyklisch verschiebt.
  7. Anzeigevorrichtung nach einem der vorhergehenden Ansprüche, wobei das genannte Anzeigefeld (1) ein aktives Matrix-Flüssigkristallfeld ist, welches eine Vielzahl von Pixeln (4) mit einer Vielzahl von Pixelelektroden, Gegenelektroden (VCOM), die unter Bildung eines Spaltes gegenüber den genannten Pixelelektroden angeordnet sind, einem in dem betreffenden Spalt enthaltenen Flussigkristall (LC) und Schaltelementen (Tr) zur Ansteuerung der betreffenden Pixelelektroden aufweist.
EP19950305079 1994-07-22 1995-07-20 Anzeigevorrichtung zur Anzeige von Videosignalen aus verschiedenen Videonormen Expired - Lifetime EP0694899B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP192876/94 1994-07-22
JP19287694A JPH0836374A (ja) 1994-07-22 1994-07-22 表示装置
JP19287694 1994-07-22

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Publication Number Publication Date
EP0694899A1 EP0694899A1 (de) 1996-01-31
EP0694899B1 true EP0694899B1 (de) 2002-03-27

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EP (1) EP0694899B1 (de)
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DE (1) DE69526001T2 (de)

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Publication number Priority date Publication date Assignee Title
JP5014711B2 (ja) * 2006-09-05 2012-08-29 三菱電機株式会社 液晶表示装置
JP2008164934A (ja) * 2006-12-28 2008-07-17 Kenwood Corp 表示装置
JP2010091588A (ja) * 2007-01-22 2010-04-22 Mitsubishi Electric Corp 液晶表示装置および液晶表示モジュールの駆動方法

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DE3836558A1 (de) * 1988-10-27 1990-05-03 Bayerische Motoren Werke Ag Verfahren und einrichtung zum erzeugen eines fernsehbildes auf einem digitalen bildschirm, insbesondere einer matrixanzeige
JPH088674B2 (ja) * 1989-07-11 1996-01-29 シャープ株式会社 表示装置
JPH0537909A (ja) * 1991-07-30 1993-02-12 Sharp Corp 液晶映像表示装置

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JPH0836374A (ja) 1996-02-06
EP0694899A1 (de) 1996-01-31
DE69526001T2 (de) 2002-11-28

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