EP0686981B1 - Procédé de test de grands réseaux de mémoire pendant l'initialisation de système - Google Patents

Procédé de test de grands réseaux de mémoire pendant l'initialisation de système Download PDF

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Publication number
EP0686981B1
EP0686981B1 EP95303770A EP95303770A EP0686981B1 EP 0686981 B1 EP0686981 B1 EP 0686981B1 EP 95303770 A EP95303770 A EP 95303770A EP 95303770 A EP95303770 A EP 95303770A EP 0686981 B1 EP0686981 B1 EP 0686981B1
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EP
European Patent Office
Prior art keywords
address
array
testing
contents
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP95303770A
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German (de)
English (en)
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EP0686981A3 (fr
EP0686981A2 (fr
Inventor
Stephen J. Sicola
Wayne H. Umland
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Compaq Computer Corp
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Compaq Computer Corp
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Publication of EP0686981A3 publication Critical patent/EP0686981A3/fr
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 

Definitions

  • the invention relates generally to digital computer systems, and more specifically to a method for testing a large memory array of a digital computer system.
  • the entire system memory is usually tested for both address line and data faults. This is typically accomplished by writing a unique data pattern to every memory location starting at the lowest address and ending at the highest address. The contents of each location are then read and compared to the expected data to determine if the stored data pattern is correct. The inverse of the pattern may then be written to each memory location in the same ascending or even descending sequential order. Again, the data pattern is read and compared to ensure correct addressing and data integrity.
  • EP-A-0 442 651 discloses a system which, when powered up, initially performs a memory test only on a subblock of the system memory. Once that subblock has been tested, an operating system is loaded into that subblock and the remaining system memory is tested during normal system operation.
  • the invention in its broad form resides in a method for testing a large memory array during system initialization, as recited in claim 1.
  • Described hereinafter is a method to test a large memory array of a digital computer system by an improved method which checks the whole array for critical stuck-at faults in address lines that could conceivably cause undetected errors in the operational firmware.
  • Also taught herein is a method for verifying the integrity of individual memory cells of the entire array without significant delay to the start of system operation.
  • a memory test method which tests first the addressing hardware of the whole memory array, and then a first portion of the memory array. While operational firmware is loaded into and begins to execute from the tested first portion, the remaining address locations of the array are tested in a background task. Sequential portions of memory, beginning at the last address of the first portion, are tested and turned over to the functional code when testing is completed.
  • the improved test method of the present invention offers several advantages. It is sequenced in time such that any potential stuck-at faults in address lines of the array are detected before the more extensive (and time-consuming) testing of the individual memory cells is performed. The latter test is performed on a first portion of the array large enough to enable startup of the functional code and the remainder is tested in a background task, which turns over successfully tested pieces of the memory array to the operational firmware over time.
  • the test method is designed to reduce the delay associated with a system startup sequence due to memory testing and, in so doing, accelerate the availability of system memory for use by functional software.
  • FIG. 1 is a block diagram of a simplified computer system which includes a read/write memory array that may be tested by a test method according to the present invention.
  • FIG. 2 is a flow diagram of a test method according to an embodiment of the present invention.
  • FIG. 3 is a block diagram of a computer system having a storage controller subsystem which includes a cache memory that may be tested by a test method according to a preferred embodiment of the present invention.
  • FIG. 4 is a detailed block diagram of the storage controller subsystem shown in FIG. 3.
  • FIG. 5 is a detailed flow diagram of test method steps 34 and 36 of FIG. 2.
  • FIG. 6 is a detailed flow diagram of test method step 42 of FIG. 2.
  • FIG. 7 is a detailed flow diagram of test method step 48 of FIG. 2.
  • a computer system 10 includes a nonvolatile memory 12, a read/write memory array 14 and a mass storage unit 16, all of which connect to a CPU 18 via a host bus 20.
  • System peripherals eg. printers, terminals, network devices, etc.
  • the nonvolatile memory 12 is where permanent programs are executed and unchanging data is contained. It will also store fundamental operating system I/O routines and unchanging system parameter data.
  • the read/write memory array 14 is where temporary data is stored and variable (eg. applications) programs are executed by the CPU 18 when loaded from the mass storage unit 16.
  • the nonvolatile memory 12 and read/write memory array 14 are directly executable by the CPU 18, while the mass storage unit 16, which is used for short/long-term and archival storage, is considered a secondary source of programs and data.
  • a hierarchical system of mass storage devices within the mass storage unit 16 may include hard disks supplemented with more specialized storage systems such as removable cartridges, RAM disks, cache memory, local processor memory, optical disks and tape drives.
  • Initialization of the computer system 10 can occur by way of a power cycle, a software reset or may be user-invoked.
  • FIG. 2 a flow diagram illustrates the preferred steps of initialization utilized by the present invention.
  • the CPU 18 Upon power-up or reset 30, the CPU 18 begins initialization 32 by performing a self-test and executing a bootstrap program resident within the nonvolatile memory 12. Once completed, the CPU then tests the whole read/write memory array for addressing-related faults according to step 34. When the address line fault testing has been completed, a first portion of the read/write memory array is tested for address line and data faults in step 36. After the testing according to step 36 has been performed, the CPU invokes concurrent processes 38.
  • the operating system is loaded into the fully tested first portion according to step 40 and the remaining portion of the read/write memory array not tested in step 36 is tested in a background task in step 42.
  • the applications software is downloaded and begins to execute in step 44.
  • the next portion of the array tested in the background task is released after testing for use by the functional code 46 and the background memory test repeats for sequential portions of the remainder of the array in step 48 and until the remainder has been tested in its entirety.
  • the background memory testing terminates 50, thus concluding the initialization process for the computer system 10 of FIG. 1. Further details of the test method will be discussed later.
  • a DSSI-based computer system 60 has a DSSI bus 62 interconnecting host CPUs 64, and storage controller subsystems 66 in dual (and failover) configuration.
  • the host interconnect could be another style of bus (eg. CI, SCSI, FDDI, etc.)
  • the storage controller subsystem 66 of Fig. 3 includes a cache memory (shown here as a module in dash lines). The storage controller subsystem 66 is illustrated in further detail in FIG. 4.
  • a storage controller subsystem 66 bridges the DSSI bus 62 of FIG. 3 (single path) via a host port interface 70 to one or more SCSI-2 device ports 72.
  • the controller subsystem further includes a policy processor 74 and its external instruction/data cache 76. Sharing a native bus 78 used by the policy processor are several memory devices - diagnostic registers 80, a program memory 82, a nonvolatile RAM 84 - and a communications port 86.
  • the program memory 82 contains the firmware for the controller and is used each time the controller subsystem boots.
  • the NV RAM 84 stores parameter information entered by a user and by the controller software.
  • the communications port 82 is used for a controller console terminal.
  • the controller subsystem also includes a share memory 86, which comprises a memory controller and buffer memory, and a cache memory 88.
  • the cache memory 88 includes a large memory array. Using twenty Mbit DRAMs (organized as 4M x4) would give a capacity of 16 Mbytes/bank or 32Mbytes per module, by way of example. DRAM memory circuitry is well known in the art; hence, the internal memory array, along with the address/data and control lines, are not shown.
  • the separate busses containing the share memory 86 and cache memory 88 are interconnected to the native bus 78 and a bus 90 used to access the DSSI host port interface and serial device ports via a bus exchanger 92.
  • the bus exchanger is a crossbar which provides fast access by all entities to all parts of the controller subsystem. Additionally residing on bus 90 are a bus interface logic element 94, a port processor 96 to support low level device port and host port operations, a port processor memory 98 and a miscellaneous glue-logic element 100.
  • the initialization of the controller subsystem 66 commences in much the same manner as the computer system of FIG. 1. It can occur via a power cycle, a software reset, or by a user pressing a button on the controller subsystem's control panel (not shown). It may be delayed long enough to allow for cache management to take place and ensure customer data integrity. Once the controller subsystem has booted, it is ready to communicate with a host CPU 64 (shown in FIG. 3.)
  • Controller subsystem initialization begins with the policy processor 74, which executes a self-test and reads a boot record containing addresses for hardware setup parameters and process control information. Following the processor's initialization, the code in the program memory 82 performs self-test diagnostics on all of the components on the native bus, as well as the shared memory 86. Once completed, code is downloaded from the program memory to the shared memory, where it is then verified. The remaining initialization tests will test the I/D cache 76, SCSI device and host ports, and the cache memory. The cache memory is tested according to the test method of the present invention because of the possible large size of its memory array, the testing of which will greatly increase boot time.
  • the testing of the potentially large memory array of the cache memory 88 is performed in two parts. Referring once again to steps 34 through 50 of the flow diagram in FIG. 2, the first part includes steps 34 and 36. The second part includes steps 42, 46, 48 and 50.
  • step 34 begins by testing first for addressing-related failures (eg. faults in address lines/decoder circuitry) in the entire array.
  • the contents of each address location of the array are written in a sequential order from lowest to highest address with an address corresponding to the address location being written 110.
  • the contents of each address location are read 112 and compared to the data written for verification 114. If the contents of address location read out are not the same as the address written, an error is flagged. If they are the same, the testing continues with step 36.
  • Step 36 tests for addressing-related and data faults in a first portion of the array addressed sequentially from the lowest address to a last address, where the last address is lower than the highest address.
  • the last address (which defines the size of the first portion) should be selected to give the operating firmware enough memory, such as a first megabyte, to begin execution.
  • the contents of each address location of the array are written in sequential order from lowest address to the last address with a first data pattern 118. Again, the contents are read back 120 to verify that the first data pattern is as written 122. If no error is detected, the contents are written with a second data pattern 124. Again, the contents are read back 126 to verify that the second data pattern is as written 128. If no errors are detected as a result of step 36, then this first portion of the array is ready for use by the operational firmware of the computer system.
  • step 38 of FIG. 2 concurrent processes are invoked, as in step 38 of FIG. 2. While the operational firmware is loaded into and begins executing out of the tested first portion of the array in the foreground (step 40 of FIG. 2), the remainder of the testing is executed in a thread or background task 42.
  • a next portion of the array addressed sequentially from the last address to a last address + N is tested for addressing and data faults by writing each address location in a sequential order from the last address to the last address + N with the first data pattern 130 and reading out the contents of each location 132 to verify the first data pattern 134. If no errors are detected, the second data pattern is then written 136 and read back 138 to verify that it remains as written 140. If no errors are detected as a result of the step 42, then this tested "next portion" is released to the operational firmware for use. Referring now to FIG.
  • Steps 42 and 46 are then repeated in the background task for a next portion of the array where the last address is updated with the last address + N (eg. the current address) 144 until the last address equals the highest address 142. Once the highest address has been reached, the memory testing is complete.
  • the above example demonstrates the benefit (eg. time savings) associated with the use of the test method according the present invention.
  • T (prior method) 49.2 seconds
  • T (improved method) 26 seconds.
  • the boot time savings can keep pace relative to ever-increasing memory capacity requirements by using the test method according to the present invention.

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  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Claims (3)

  1. Procédé de test d'un grand réseau de mémoire d'un système de traitement numérique, comprenant les étapes de :
    premièrement, recherche des défaillances relatives à l'adressage de tout le réseau dans un ordre séquentiel à partir d'une adresse la plus basse jusqu'à une adresse la plus élevée, pour détecter ainsi des erreurs d'adresse sur blocage dans le réseau avant d'exécuter une recherche d'erreurs de ligne d'adresses et de données pour tout le réseau ;
    deuxièmement, recherche d'erreurs de ligne d'adresses et de données dans une première partie du réseau à laquelle on accède séquentiellement à partir de l'adresse la plus basse jusqu'à une dernière adresse, la dernière adresse étant plus basse que l'adresse la plus élevée, par l'écriture à chaque emplacement adressé du réseau du contenu d'une première configuration de données et la lecture du contenu à l'emplacement adressé pour vérifier que la première configuration de données reste telle qu'écrite, ensuite l'écriture à l'emplacement adressé du contenu d'une deuxième configuration de données et la lecture du contenu à l'emplacement adressé pour vérifier que la deuxième configuration de données reste telle qu'écrite ;
    mise en disponibilité de la première partie du réseau pour l'utiliser par le microprogramme d'exploitation du système de traitement s'il n y a pas d'erreurs détectées à la suite de l'étape de recherche d'erreurs de ligne d'adresses et de données ;
    lancement de l'exécution du microprogramme d'exploitation de la première partie du réseau ;
    troisièmement, recherche des erreurs de ligne d'adresses et de données dans une tâche de fond dans une partie suivante du réseau à laquelle on accède séquentiellement à partir de la dernière adresse jusqu'à une dernière adresse + N, où N est le nombre d'emplacements adressés dans la partie suivante du réseau à tester, par l'écriture à chaque emplacement adressé du contenu de la première configuration de données et la lecture du contenu à l'emplacement adressé pour vérifier que la première configuration de données reste telle qu'écrite, ensuite l'écriture à l'emplacement adressé du contenu de la deuxième configuration de données et la lecture du contenu à l'emplacement adressé pour vérifier que la deuxième configuration de données reste telle qu'écrite ; et,
    mise en disponibilité pour le microprogramme d'exploitation de la partie du réseau entre la dernière adresse et la dernière adresse + N s'il n'y a pas d'erreurs détectées à la suite de l'étape de test de la partie suivante du réseau ; et,
    répétition dans la tâche de fond de l'étape de test de la partie suivante du réseau où la dernière adresse est mise à jour avec la dernière adresse + N jusqu'à ce que la dernière adresse soit égale à l'adresse la plus élevée.
  2. Procédé de test d'un grand réseau de mémoire d'un système de traitement numérique selon la revendication 1, dans lequel l'étape de première recherche de défaillances relatives à l'adressage dans tout le réseau comprend les étapes de :
    écriture à chaque emplacement adressé du contenu d'une adresse correspondant à l'emplacement adressé qui est écrit ; et,
    lecture du contenu à l'emplacement adressé pour vérifier que l'adresse de lecture est la même que l'adresse d'écriture.
  3. Procédé de test d'un grand réseau de mémoire d'un système de traitement numérique selon la revendication 1, dans lequel la première configuration de données est une configuration binaire '0101' de répétition et la deuxième configuration de données est une configuration binaire '1010' de répétition.
EP95303770A 1994-06-06 1995-06-01 Procédé de test de grands réseaux de mémoire pendant l'initialisation de système Expired - Lifetime EP0686981B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US254816 1994-06-06
US08/254,816 US5479413A (en) 1994-06-06 1994-06-06 Method for testing large memory arrays during system initialization

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EP0686981A2 EP0686981A2 (fr) 1995-12-13
EP0686981A3 EP0686981A3 (fr) 1996-02-07
EP0686981B1 true EP0686981B1 (fr) 2000-08-23

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US6412082B1 (en) * 1997-12-17 2002-06-25 Sony Corporation Method and apparatus for selecting computer programs based on an error detection mechanism
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US7085973B1 (en) * 2002-07-09 2006-08-01 Xilinx, Inc. Testing address lines of a memory controller
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US7418636B2 (en) * 2004-12-22 2008-08-26 Alcatel Lucent Addressing error and address detection systems and methods
EP2063432B1 (fr) * 2007-11-15 2012-08-29 Grundfos Management A/S Procédé destiné à vérifier une mémoire de travail
JP2010044635A (ja) * 2008-08-14 2010-02-25 Hitachi Ltd ファイルサーバシステム及びファイルサーバシステム起動方法
US10409698B2 (en) * 2010-04-09 2019-09-10 Advantest Corporation Method and automatic test equipment for performing a plurality of tests of a device under test
DE102010027287A1 (de) * 2010-07-16 2012-01-19 Siemens Aktiengesellschaft Verfahren und Vorrichtung zum prüfen eines Hauptspeichers eines Prozessors
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DE69518468T2 (de) 2001-05-23
EP0686981A3 (fr) 1996-02-07
EP0686981A2 (fr) 1995-12-13
US5479413A (en) 1995-12-26
DE69518468D1 (de) 2000-09-28

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