EP0684686B1 - Spannungserhöhungsschaltung und ihre Verwendung in einer Festkörper-Bildaufnahmevorrichtung - Google Patents

Spannungserhöhungsschaltung und ihre Verwendung in einer Festkörper-Bildaufnahmevorrichtung Download PDF

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Publication number
EP0684686B1
EP0684686B1 EP95303587A EP95303587A EP0684686B1 EP 0684686 B1 EP0684686 B1 EP 0684686B1 EP 95303587 A EP95303587 A EP 95303587A EP 95303587 A EP95303587 A EP 95303587A EP 0684686 B1 EP0684686 B1 EP 0684686B1
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EP
European Patent Office
Prior art keywords
power supply
solid
state image
voltage
boosting
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP95303587A
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English (en)
French (fr)
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EP0684686A3 (de
EP0684686A2 (de
Inventor
Yasuhito C/O Intellectual Property Division Maki
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Sony Corp
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Sony Corp
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Publication of EP0684686A2 publication Critical patent/EP0684686A2/de
Publication of EP0684686A3 publication Critical patent/EP0684686A3/de
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type

Definitions

  • the present invention relates to a a solid-state image-sensing device comprising a boosting circuit.
  • FIG. 10 is a view showing an example of a previously proposed pulse-boosting type boosting circuit.
  • MOSFET's N-channel type MOSFET's (hereinafter referred to simply as MOS transistors) M10n with their gates and drains connected in common are connected in series in, for example, three stages across the positive pole of a power supply 101 and a circuit output terminal 102.
  • a clock pulse ⁇ 11 is then applied to an output end N101 of the first stage MOS transistor M101 via the capacitor C11 and a clock pulse ⁇ 12 of a phase which is opposite to that of the clock pulse ⁇ 11 is applied to the output end N102 of the second stage MOS transistor M102.
  • a load capacitor CL is connected across the output end N103 (circuit output terminal 12) of the third stage MOS transistor M103 and ground.
  • the boosting circuit of the above construction is used as a Vsub generation boosting circuit which boosts the power supply voltage in image-sensing devices known as linear sensors (line sensors) or area sensors and takes this boosted voltage Vout as a substrate voltage Vsub.
  • the whole of the solid-state image-sensing device substrate becomes a load capacitance and large capacitance driving and a current capacitances become necessary. This causes the rising characteristic of the boosting voltage Vout to be poor, as shown in FIG. 11.
  • the current Ids across the drain and source of each of the MOS transistors M101 to M103 may be made large so as to make the rise time for the boosting voltage Vout shorter. In order to achieve this it is necessary to lower the threshold voltage Vth of each of the MOS transistors M101 to M103, make the channel width larger, or make the channel length L shorter.
  • this boosting circuit when used, for example, as a Vsub generation boosting circuit of a solid-state image-sensing apparatus, a large amount of space is required on the substrate of the solid-state image-sensing circuit in order to make (on-chip) this boosting circuit, which impedes the miniaturization of the solid-state image-sensing apparatus.
  • US Patent No. US-A-5,276,646 discloses a boosting circuit comprising:
  • a solid-state image-sensing device comprising:
  • the one-way element for charging may be a MOS transistor or a diode.
  • the solid-state image-sensing device may comprise a charge detector for detecting and converting to electrical signals charges transferred by the charge transfer register.
  • the boosting circuit boosts a power supply voltage and generates a substrate voltage.
  • the sensor, charge transfer register, charge detector and boosting circuit are preferably formed on the same substrate.
  • a load capacitor may be connected across the output terminal of the final stage of the one-way element and earth.
  • a load is charged via the one way element due to this one-way element for charging connected in the forward direction from the power supply side to the circuit output terminal side going into a forward biased state so as to conduct.
  • the plurality of stages of the one-way element for boosting also go into forward bias so as to conduct due to the power supply going on, so that the charging operation which accompanies the boosting operation of the plurality of stages of the one-way element is also carried out in parallel and the load charging voltage therefore rapidly rises up to the power supply voltage.
  • the one-way element for charging which has been carrying out charging up until this point goes into reverse bias so as to be in an non-conducting state.
  • Charging due to the one-way element is therefore not carried out after this and a boosting operation is performed by the plurality of stages of the one-way element for boosting in synchronization with a reverse phase clock pulse.
  • Embodiments of the present invention provide a solid-state image-sensing device comprising a boosting circuit which have improved boosting voltage rise characteristics without it being necessary to change the size of the circuit elements.
  • FIG. 1 is a circuit diagram showing a first embodiment of a booster circuit arranged in a solid-state image-sensing device according to the present invention.
  • FIG. 1 for example, three stages of MOS transistors Mn for boosting having their gates and drains connected in common are connected in series in the forward direction from the side of the power supply 1 to the circuit output element 2 as a one-way element across the positive pole side of the power supply 1 and the circuit output element 2.
  • a clock pulse ⁇ 1 is applied to the output end N1 of the first stage MOS transistor M1 via a capacitor C1.
  • a clock pulse ⁇ 2 having a phase which is the opposite of that of the clock pulse ⁇ 1 is applied to the output end N2 of the second MOS transistor M2.
  • a load capacitor CL is connected between the output N3 (circuit output terminal 2) of the third stage MOS transistor M3.
  • a MOS transistor M4 for charging is connected across the positive pole side of the power supply 1 and the circuit output terminal 2 in a forward direction going from the side of the power supply 1 to the side of the circuit output terminal 2. i.e. the gate and drain of the MOS transistor for charging are wired to the positive pole side of the power supply 1 and the source is wired to the circuit output terminal 2.
  • This MOS transistor M4 for charging is provided for promptly charging the load capacitor CL at the time of power supply start-up and the drain-source current Ids is set to be large.
  • the drain-source current Ids of the MOS transistor M4 is set to be large by lowering the threshold voltage Vth of the MOS transistor M4, making the channel width W large, or shortening the channel length L.
  • the power supply goes on (power supply on), the MOS transistor M4 for charging conducts so as to become forward-biased and the charging of the load capacitor CL via the MOS transistor M4 for charging therefore commences. Further, by turning on the power supply 1, the MOS transistors M1 to M3 for boosting also become forward biased and conduct (go on) so that the charging which accompanies the boosting operation of the transistors M1 to M3 for boosting can be carried out simultaneously.
  • the booster voltage Vout can be made to rise quickly, as shown by the solid line in FIG. 2, because the load capacitor CL can be rapidly charged via the MOS transistor M4 for charging at the time of turning on.
  • the dashed line in FIG. 2 shows the response waveform at the time of turning on for a previously proposed example.
  • the gate and drain of the MOS transistor M1 are connected to the positive pole side of the power supply 1.
  • the voltage V1 of this output end N1 is therefore lower than the power supply voltage Vdd by an amount Vx 1 .
  • This Vx 1 is the voltage drop portion due to the threshold voltage Vth 1 of the MOS transistor M1.
  • the clock pulse ⁇ 2 is of an opposite phase to that of the clock pulse ⁇ 1. Therefore, when the level of the clock pulse ⁇ 2 is low, the voltage V2 at the output end N2 of the MOS transistor M2 becomes lower than the voltage V1 of the output end N1 by just Vx 2 .
  • the voltage Vx 2 is the voltage drop portion due to the threshold voltage Vth 2 of the MOS transistor M2.
  • the voltage V2 at the output end N2 is smoothed by the MOS transistor M3 and the load capacitor CL and derived from the circuit output terminal 2 as the boosting voltage Vout.
  • the boosting voltage Vout is lower than the voltage V2 of the output end N2 by an amount Vx 3 .
  • Vx 3 is the lowering of the voltage due to the threshold voltage Vth 3 of the MOS transistor M3.
  • the MOS charging transistor M4 of which the gate and drain are connected to the positive pole side of the power supply 1 and source is connected to the circuit output terminal 2 in a pulse boosting-type boosting circuit when the power supply is turned on, the boosting voltage Vout can be made to rise rapidly because the load capacitor CL is rapidly charged via the MOS charging transistor M4.
  • a boosting circuit for which the boosting voltage Vout rises rapidly when the power supply is turned on can be provided without making the size of the MOS boosting transistors M1 to M3 and the capacitance values of the capacitors C1 and C2 large by setting the drain-source current Ids of the MOS charging transistor M4 to be large.
  • the space that goes with having small-sized transistors and small-capacitance capacitors can be saved within the circuit structure.
  • a diode D1 the anode of which is connected to the positive pole side of the power supply 1 and the cathode of which is connected to the circuit output terminal 2, may also be used.
  • FIG. 5 is a structural view showing an example of a solid-state image-sensing device employing a boosting circuit of the aforementioned construction as a Vsub generator boosting circuit.
  • An application in a CCD linear sensor is shown as the solid-state image-sensing apparatus in this example, but applications are by no means limited to CCD linear applications and applications in solid-state image-sensing apparatus including area sensors other than CCDs are also possible.
  • the CCD linear sensor comprises a sensor row 12 consisting of a plurality of light receivers 11 made up from photodiodes etc. which convert and accumulate incident light into a charge corresponding to the amount of light and a charge transmitting register 14 made up of a CCD for transmitting signal charges outputted from each of the light receivers 11 of the sensor row 12 via a read-out gate 13.
  • the read-out gate 13 immediately reads out to the charge transfer register 14 the signal charges accumulated at each of the light receivers 11 of the sensor row 12 using the application of the read-out pulse ⁇ ROG.
  • the signal charge is transferred using two-phase driving employing two-phase transmission clocks ⁇ H1 and ⁇ H2.
  • a charge voltage converter (charge detector) 15, of, for example, a floating diffusion structure for detecting the transmitted signal charge and converting it to a voltage is formed at the final stage of the charge transfer register 14.
  • the output voltage for this charge voltage converter 15 is outputted from the output terminal 17 via the buffer 16 as the CCD output.
  • the boosting circuit described above is used as a Vsub generator booster circuit 18 for boosting the power supply voltage Vdd and generating a substrate voltage Vsub.
  • This Vsub generator booster circuit 18 is made (on chip) on the same substrate 19 as the sensor row 12 and the charge transfer register 14 and uses two-phase clocks ⁇ H1 and ⁇ H2 as the clock pulses ⁇ 1 and ⁇ 2.
  • the boosting circuit not just as the Vsub generator booster circuit 18 but also for providing the operating power supply voltages to other circuits such as the buffer 16.
  • FIG. 6 is a cross-sectional structural drawing showing the essential parts of the Vsub generator booster circuit 18 formed on-chip with the CCD linear sensor.
  • a light receiver 11 comprised of a P + type hole accumulation layer 22 on an N + type load accumulation layer 21 is formed within a P-well on an N-type silicon substrate 19.
  • a read-out gate 13 comprised of an N-type impurity region 23 with a gate electrode 24 provided at it's upper end and a charge transfer register 14 comprised of an N + type impurity region with a transfer electrode 24 provided at it's upper end are formed next to the light receiver 11.
  • a final stage MOS transistor (the MOS transistor M3 in FIG. 1) taking an N-type impurity region 28 as it's source region, an N-type impurity region 29 as it's drain region, with a gate electrode 30 being provided above and between regions 28 and 29, is formed within a separate P-well 27 which is formed separately from the P-well 20.
  • a boosting voltage is derived from the source region 28 of the final stage MOS transistor M3. This boosting voltage is then taken as the substrate voltage Vsub and applied to the N+ type non-volatile region 31 formed on the surface side of the N-type silicon substrate 19.
  • the boosting circuit can charge a large capacitance with a small MOS transistor and can therefore achieve this on-chip and the chip-size can also be made small.
  • FIG. 7 is a circuit diagram showing a second embodiment of a boosting circuit arranged in a device according to the present invention.
  • this diagram portions which are the same as portions in FIG. 1 will be given the same numerals.
  • a structure is adopted where the number of MOS boosting transistor stages is increased so that, for example, MOS transistors Mn are connected in 5 stages in series, with the intention of generating a higher boosting voltage Vout.
  • MOS boosting transistors M11 to M15 with their gates and drains connected in common are connected across the positive pole side of the power supply 1 and the output circuit terminal 2 so as to be in series in the forward direction from the power supply 1 side to the circuit output terminal 2 side as a one-way element.
  • a clock pulse ⁇ 1 is applied to each of the output ends N11 and N13 of the first and third stage (odd numbered stages with the final stage excluded) MOS transistors M11 and M13 via capacitors C1 and C3.
  • a clock pulse ⁇ 2 of opposite phase to the clock pulse ⁇ 1 is applied via a capacitor C2 to each of the output ends N12 and N14 of the second and fourth stage (even numbered stages) MOS transistors M12 and M14.
  • a load capacitor CL is then connected across the output end N15 (circuit output terminal 2) of the fifth-stage MOS transistor M15 and earth.
  • a MOS transistor M16 for charging which has it's gate and drain connected in common is connected across the positive pole side of the power supply 1 and the circuit output terminal 2 as a one way element and is connected in the forward direction going from the side of the power supply 1 to the side of the circuit output terminal 2. i.e. the gate and drain of the MOS transistor M16 for charging are wired to the positive electrode side of the power supply 1 and the source is wired to the circuit output terminal 2.
  • the power supply goes on (power supply on), the MOS transistor M16 for charging conducts so as to become forward-biased and the charging of the load capacitor CL via the MOS transistor M16 for charging therefore commences. Further, by turning on the power supply 1, the MOS transistors M11 to M15 for boosting also become forward biased and conducts (goes on) so that the charging which accompanies the boosting operation of the transistors M11 to M15 for boosting can be carried out simultaneously.
  • the booster voltage Vout can be made to rise quickly, as shown by the solid line in FIG. 8, because the load capacitor CL can be rapidly charged via the MOS transistor M6 for charging at the time of turning on.
  • the speed of the rising of the boosting voltage Vout can be seen to increase as the number of MOS transistors M1 to M5 for charging is made large.
  • the boosting operation using the MOS boosting transistors M11 to M15 is carried out under fixed conditions.
  • the boosting operation under these fixed conditions will be described with reference to the timing chart in FIG. 9.
  • the voltage V11 at the output end N11 of the first stage MOS transistor M11 is lower than the power supply voltage Vdd by the voltage Vx 11 , which is the voltage drop due to the threshold voltage Vth 11 of the MOS transistor M11.
  • the voltage V12 at the output end N12 of the second stage MOS transistor M12 is lower than the voltage V11 at the output end N11 by the voltage Vx 12 , which is the voltage drop due to the threshold voltage Vth 12 of the MOS transistor M12.
  • the voltage V13 at the output end N13 of the third stage MOS transistor M13 is lower than the voltage V12 at the output end N12 by the voltage Vx 13 , which is the voltage drop due to the threshold voltage Vth 13 of the MOS transistor M13.
  • the voltage V14 at the output end N14 of the fourth stage MOS transistor M14 is lower than the voltage V13 at the output end N13 by the voltage Vx 14 , which is the voltage drop due to the threshold voltage Vth 14 of the MOS transistor M14.
  • the voltage V14 at the output end N14 is smoothed by the MOS transistor M15 and the load capacitor CL and derived from the circuit output terminal 2 as the boosting voltage Vout.
  • the boosting voltage Vout is lower than the voltage V14 of the output end N14 by an amount Vx 15 .
  • Vx 15 is the lowering of the voltage due to the threshold voltage Vth 15 of the MOS transistor M15.
  • a higher-voltage boosting voltage Vout can be derived by increasing the number of stages of MOS transistors for boosting.
  • the necessary substrate voltage Vsub of about 5V for realizing the performance of the solid-state image-sensing device can be easily obtained even if the power supply voltage for the solid-state image sensing device is reduced by about, for example, 1.5V.
  • diode D1 as the one-way element in place of the diode connection MOS transistor M6 in the example modification of the first embodiment shown in FIG. 4.
  • the number of stages of MOS transistors for boosting is by no means limited to the three stages and five stages shown in the first and second embodiments. Two stages, four stages or six stages or more are also possible, whereby the larger the number of MOS transistor stages for boosting, the higher the boosting voltage which can be extracted.
  • the rising characteristic of the boosting voltage can be improved without it being necessary to adapt the size of the circuit elements because the load can be rapidly charged via the one-way elements at the time of turning on the power supply.
  • an on-chip construction can be adopted and the chip-size can be made small in applications in solid-state image-sensing devices because a large capacitance can be charged using compact circuit elements.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Dc-Dc Converters (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Claims (7)

  1. Festkörper-Bildabtastvorrichtung
       mit einer Spannungserhöhungsschaltung (18), die aufweist:
    einen Stromversorgungsanschluß,
    einen Ausgangsanschluß (Vout),
    ein Ventilelement mit mehreren Stufen (M1-M3), die in Reihe zwischen dem Stromversorgungsanschluß und dem Ausgangsanschluß angeordnet sind, wobei ihre Durchlaßrichtung von dem Stromversorgungsanschluß zu dem Ausgangsanschluß verläuft,
    Mittel zum Anlegen eines ersten und eines zweiten Taktimpulssignals (1, 2) mit entgegengesetzten Phasen zwischen jede der Stufen des Ventilelements,
    und ein Ventilelement (M4; D1; M16) zum Aufladen, das parallel zu dem erstgenannten Ventilelement in Durchlaßrichtung angeordnet ist,
       ferner mit einem Sensor (12) mit einer Mehrzahl von in einem Array angeordneten Lichtempfängern (11) zur Umwandlung von auftreffendem Licht in Ladungen, die der Menge des auftreffenden Lichts entsprechen, und zum Akkumulieren der Ladungen
       und mit einem Ladungstransfer-Register (14) zum Übertragen der aus den einzelnen Lichtempfängern (11) ausgelesenen Ladungen, wobei das Ladungstransfer-Register so angeordnet ist, daß es die ersten und die zweiten Taktimpulssignale aufnimmt, so daß diese als Übertragungs-Taktsignale für die Ansteuerung des Ladungstransfer-Registers (14) wirken.
  2. Festkörper-Bildabtastvorrichtung nach Anspruch 1, mit einem Ladungsdetektor (15) zum Detektieren der von dem Ladungstransfer-Register (1) übertragenen Ladungen und zu deren Umwandlung in elektrische Signale.
  3. Festkörper-Bildabtastvorrichtung nach Anspruch 2, bei der der Sensor (12), das Ladungstransfer-Register (14), der Ladungsdetektor (15) und die Spannungserhöhungsschaltung (18) auf dem gleichen Substrat ausgebildet sind.
  4. Festkörper-Bildabtastvorrichtung nach Anspruch 1, 2 oder 3, bei der die Spannungserhöhungsschaltung (18) eine Versorgungsspannung (Vdd) erhöht und eine Substratspannung (Vsub) erzeugt.
  5. Festkörper-Bildabtastvorrichtung nach einem der Ansprüche 1 bis 5, bei der das Ventilelement für das Aufladen ein MOS-Transistor (M4, M16) ist.
  6. Festkörper-Bildabtastvorrichtung nach einem der Ansprüche 1 bis 4, bei der das Ventilelement für das Aufladen eine Diode ist.
  7. Festkörper-Bildabtastvorrichtung nach einem der vorgehenden Ansprüche, mit einem Lastkondensator (CL), der zwischen dem Ausgangsanschluß der letzten Stufe des Ventilelements und Erde angeordnet ist.
EP95303587A 1994-05-27 1995-05-26 Spannungserhöhungsschaltung und ihre Verwendung in einer Festkörper-Bildaufnahmevorrichtung Expired - Lifetime EP0684686B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP138150/94 1994-05-27
JP6138150A JPH07322606A (ja) 1994-05-27 1994-05-27 昇圧回路及びこれを用いた固体撮像装置
JP13815094 1994-05-27

Publications (3)

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EP0684686A2 EP0684686A2 (de) 1995-11-29
EP0684686A3 EP0684686A3 (de) 1997-09-24
EP0684686B1 true EP0684686B1 (de) 2002-12-04

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US (1) US5777317A (de)
EP (1) EP0684686B1 (de)
JP (1) JPH07322606A (de)
KR (1) KR100527606B1 (de)
DE (1) DE69529017T2 (de)
MY (1) MY113172A (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3346273B2 (ja) * 1998-04-24 2002-11-18 日本電気株式会社 ブースト回路および半導体記憶装置
TW503620B (en) * 2000-02-04 2002-09-21 Sanyo Electric Co Drive apparatus for CCD image sensor
EP1158654B1 (de) 2000-02-15 2006-05-03 STMicroelectronics S.r.l. Ladungspumpenschaltung und Spannungserhöhungsanordnung mit Übertragung und Gewinnung der Ladung
DE10051936B4 (de) 2000-10-19 2004-10-14 Infineon Technologies Ag Spannungspumpe mit Einschaltsteuerung
TW529178B (en) * 2001-02-06 2003-04-21 Sanyo Electric Co Charge pump device
JP5203562B2 (ja) * 2004-11-08 2013-06-05 三星電子株式会社 Ｃｍｏｓイメージセンサー及びその駆動方法
JP2006158157A (ja) * 2004-12-01 2006-06-15 Toshiba Matsushita Display Technology Co Ltd Ｄｃ−ｄｃ変換回路
JP2007060872A (ja) * 2005-08-26 2007-03-08 Rohm Co Ltd 昇圧回路とそれを用いた電気機器
WO2007066587A1 (ja) 2005-12-08 2007-06-14 Rohm Co., Ltd. チャージポンプ回路、ｌｃｄドライバｉｃ、電子機器
JP4837519B2 (ja) * 2006-10-16 2011-12-14 株式会社 日立ディスプレイズ 表示装置の駆動回路
US8030988B2 (en) * 2009-12-31 2011-10-04 Stmicroelectronics Asia Pacific Pte. Ltd. Method for generating multiple incremental output voltages using a single charge pump chain

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH614837B (fr) * 1977-07-08 Ebauches Sa Dispositif pour regler, a une valeur determinee, la tension de seuil de transistors igfet d'un circuit integre par polarisation du substrat d'integration.
JPS62150597A (ja) * 1985-12-25 1987-07-04 Nissan Motor Co Ltd 昇圧回路
JPS62233064A (ja) * 1986-04-02 1987-10-13 Nec Corp Ｃｍｏｓ電圧変換回路
NL8701278A (nl) * 1987-05-29 1988-12-16 Philips Nv Geintegreerde cmos-schakeling met een substraatvoorspanningsgenerator.
JP2805210B2 (ja) * 1989-06-09 1998-09-30 日本テキサス・インスツルメンツ株式会社 昇圧回路
JPH07123163B2 (ja) * 1989-07-21 1995-12-25 日本電気株式会社 電荷転送装置
US5059815A (en) * 1990-04-05 1991-10-22 Advanced Micro Devices, Inc. High voltage charge pumps with series capacitors
KR920006991A (ko) * 1990-09-25 1992-04-28 김광호 반도체메모리 장치의 고전압발생회로
US5081371A (en) * 1990-11-07 1992-01-14 U.S. Philips Corp. Integrated charge pump circuit with back bias voltage reduction
JP2575964B2 (ja) * 1991-03-27 1997-01-29 株式会社東芝 固体撮像装置
WO1993013705A1 (en) * 1992-01-11 1993-07-22 Paul Toleman Tonometer

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Publication number Publication date
MY113172A (en) 2001-12-31
JPH07322606A (ja) 1995-12-08
KR950034810A (ko) 1995-12-28
EP0684686A3 (de) 1997-09-24
KR100527606B1 (ko) 2006-06-07
DE69529017T2 (de) 2003-10-09
DE69529017D1 (de) 2003-01-16
US5777317A (en) 1998-07-07
EP0684686A2 (de) 1995-11-29

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