EP0681274B1 - Carte de valeur avec unités de valeur binaires et méthode pour décaler sur la carte une quantité, exprimée en unités de valeur binaires - Google Patents

Carte de valeur avec unités de valeur binaires et méthode pour décaler sur la carte une quantité, exprimée en unités de valeur binaires Download PDF

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Publication number
EP0681274B1
EP0681274B1 EP95105700A EP95105700A EP0681274B1 EP 0681274 B1 EP0681274 B1 EP 0681274B1 EP 95105700 A EP95105700 A EP 95105700A EP 95105700 A EP95105700 A EP 95105700A EP 0681274 B1 EP0681274 B1 EP 0681274B1
Authority
EP
European Patent Office
Prior art keywords
value
register
value register
binary
marking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP95105700A
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German (de)
English (en)
Other versions
EP0681274A3 (fr
EP0681274A2 (fr
Inventor
Youssef Cammoun
Etienne Cambois
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IPM INTERNATIONAL SA
Original Assignee
IPM International SA
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Publication date
Application filed by IPM International SA filed Critical IPM International SA
Publication of EP0681274A2 publication Critical patent/EP0681274A2/fr
Publication of EP0681274A3 publication Critical patent/EP0681274A3/fr
Application granted granted Critical
Publication of EP0681274B1 publication Critical patent/EP0681274B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/0866—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means by active credit-cards adapted therefor

Definitions

  • the invention relates to a prepaid card with binary value units and to a method for Moving a value represented by binary units of value on the prepaid card according to The preambles of claims 1 and 2.
  • Such prepaid cards are advantageous in service machines - for example in telephone machines - used, for example, the prepaid cards comply with the standard ISO 7816.
  • a value card of this type is known (EP 0 519 847 A1), in which binary value units are in one Number p ordered registers are stored.
  • a register has a certain number n equal Value units whose valency is dependent on the rank of the register.
  • the entire value of a Register is the same size as a single unit of value of the register immediately higher Register.
  • the invention is based on the object, a value card whose value is reliably changed, so to and to provide a method that has little of the space available on the prepaid card Memory space for means to achieve reliability required in modifying the value is consumed.
  • a value card has a memory module denoted by 1 in FIG. 1 and an access module 2 which is connected via signal lines 3 to the memory module 1.
  • the signal lines 3 comprise data and control lines, through which a stored in the memory module 1 information from the access module is readable and / or changeable.
  • the access module 2 advantageously has an input 4 and a Output 5, wherein the input 4 together with the output 5 as a bidirectional data channel is executable.
  • the access module 2 advantageously has a microprocessor.
  • the memory module 1 comprises a register block 6 and a marker register 7.
  • the register block 6 has a first number N of value registers W 1 to W N , which each comprise a second number n of binary memory cells E 1 to E n for each binary non-lossable value unit.
  • the first number N is three and the second number n is eight.
  • the first number N and the second number n are natural numbers that are adaptable to the purpose of the prepaid card.
  • the second number n for a value register W 1 or W 2 or W N is freely selectable, in the illustrated example, the second number n for each value register W 1 to W N of the register block 6 is the same size.
  • the variable which can be stored in a memory cell E k of the ith value register W i depends on the valid value unit of the memory cell E k and the binary value or the logic state of the memory cell E k .
  • the value unit of the memory cell E k of the value register W i depends on the rank of the value register W i in the valid order of the register block 6.
  • the value registers W 1 to W N are ranked such that for an index i from 2 to N the value register W i is superordinate to the value register W i-1 , or in other words, for an index i of 2 until N the value register W i-1 is subordinate to the value register W i .
  • a variable here comprises a binary value and a unit of values, whereby the unit of value comprises a Numerical value and a numerical value assigned unit or meaning has.
  • Value units are here called 8 kWh, 16 tax pulses, 10 francs and 64 m.
  • the i-1 storable maximum size k is equal to the value unit of a single memory cell in an E value register W of the value register W i-1 immediate parent value register W i.
  • the maximum size which can be stored in the value register W i-1 is advantageously set to 8 tax pulses, while the maximum size which can be stored in the value register W i is advantageously 64 tax pulses.
  • the memory cryology of the memory module 1 is selected so that a current state or binary value of the memory cell E 1 or E 2 or E n of the register block 6 in case of failure or removal of the supply of the memory module 1 is not lost and also a current state or binary Value of the memory cells M 2 , or M N of the marker register 7 is not lost in case of failure or removal of the power of the memory module 1.
  • the memory module 1 is, for example, an EEPROM (electrically erasable programmable read only memory) or an EAPROM (electrically alterable programmable read only memory).
  • a quantity G is stored in the second value register W 2 , which is represented by n memory cells E 1 to E n set to logic "1".
  • FIG. 2b shows the register block 6 and the marker register 7 after the completion of the first action, whereby the memory cells changed in the first action are shown hatched.
  • Fig. 2c shows the register block 6 and the marker register 7 after the completion of the second action, wherein the memory cells changed in the second action are shown hatched.
  • the described method is applicable for shifting a further variable G 'from the first value register W 1 into the value register W 2 , which is superordinate to the first value register W 1 , wherein in the first action the binary state of a memory cell E 1 of the superordinate one has the value logical "0" Value register W 2 and the bit M 2 of the marker register 7 assigned to the higher-order value register W 2 are inverted or set to logical "1" in a non-interruptible execution step and the binary states of the memory cells E 1 to E having the size G 'in the second action n of the value register W 1 and the value register W 1 superordinate value register W 2 associated bit M 2 of the marker register 7 are inverted in a further non-interruptible execution step or set to logic "0".
  • FIG. 2d shows the register block 6 and the marker register 7 after the completion of the first action to shift the quantity G '
  • FIG. 2e shows the register block 6 and the marker register 7 after the completion of the second action Actions modified memory cells are shown hatched.
  • the memory module 1 and the access module 2 are designed such that the value register W i associated memory cell M i of the marking register 7 together with a memory cell E k of the value register W i are settable to a first binary value and that the value register W i associated memory cell M i of the mark register 7 together with the n memory cells E 1 to E n of the value register W i subordinate value register W i-1 can be set to the value inverse to the first binary value.
  • FIG. 3a the memory module 1 in a state in which the Nth bit M N of the marker register 7 has the value logical "1", in which case the bit indicates that a shift has been performed incompletely.
  • the state may occur, for example, when the value card having the memory module 1 is deliberately or unintentionally pulled out of a card reader just when the size G is to be shifted.
  • the shifting can be completely locked in this state by a correction cycle to be carried out.
  • the correction cycle comprises inverting the n memory cells E 1 to E n of the value register W N-1 associated with the Nth bit M N of the marker register 7, and at the same time also resetting the Nth bit M N of the marker register to logic "0"
  • FIG. 3b shows the state of the memory module 1 after the correction cycle.
  • a test sequence for detecting an incomplete shift with a conditionally performed correction cycle on the prepaid card is writable in a pseudocode similar to the Pascal programming language as follows:
  • test sequence is advantageously carried out after inserting the prepaid card into a card reader.
  • the test sequence is performed by a processor of the prepaid card.
  • the prepaid card Since the prepaid card has a mark register 7, which performed incomplete Shifts of values G and G 'in the test sequence can be identified and corrected by the Card readers are dispensed with mechanical transport devices and expensive closures, as a duch Extracting the prepaid card in the operating state for the user with regard to the value of the prepaid card neither advantages nor disadvantages can be achieved.
  • the memory module 1 is advantageously programmable via the input 4, that is, one on the Value card stored value via the input 4 is variable, with at least one advantage Status information - for example, empty or not empty - the value card is available at the output 5.
  • the method shown is to shift a quantity represented by binary value units advantageous in reliable methods for counting or adding up units of value on the prepaid card used.
  • the method is simple on corresponding variants in negative logic and / or for Debiting units of value on the prepaid card transferable. It goes without saying that one in the Register block 6 incomplete shift in one bit of the marker register 7 either as shown in FIGS. 2 and 3, with logic "1" or markable with logic "0".
  • the storable in a bit of a value register W i variable is to the value register W i of immediately subordinate value register W to transfer inevitably i-1, when the subordinate value register W is empty I-1.
  • an offset carried out incompletely in the register block 6 in the marker register 7 is marked by logic "0".
  • a certain size G can be stored.
  • a first action the binary state of a memory cell E 4 having the value "1" of the N-th value register W N and the bit M N of the marking register 7 assigned to the value register W N are inverted in a non-interruptible execution step, or logically " 0 "set.
  • Fig. 4b shows the register block 6 and the marker register 7 after the completion of the first action, wherein the memory cells changed in the first action are shown hatched.
  • Fig. 4c shows the register block 6 and the marker register 7 after the completion of the second action, wherein the memory cells changed in the second action are shown hatched.
  • the memory module 1 in a state in which the Nth bit M N of the marker register 7 has the value of logical "0", in which case the bit indicates that a shift has been performed incompletely.
  • the state may occur, for example, if the value card having the memory module 1 is deliberately or unintentionally pulled out of a card reader just when the size G "is to be shifted Inverting the n memory cells E 1 to E n of the value register W N-1 , which is subordinate to the value register W N assigned to the Nth bit M N of the marker register 7.
  • the Nth bit M N of the marker register is also reset to logic "1."
  • the state of the memory module 1 after the correction cycle is shown in FIG.
  • the value card has N * n memory cells for representing its value, then there are additionally N-1 Memory cells required to mark a shift.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Credit Cards Or The Like (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Control Of Vending Devices And Auxiliary Devices For Vending Devices (AREA)
  • Recording Measured Values (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Image Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Magnetic Ceramics (AREA)

Claims (3)

  1. Carte de valeur avec unités de valeur binaires comprenant un premier nombre N de registres de valeur W1, W2, ..., WN ordonnés et un registre de marquage (7), chaque registre de valeur W1, W2, ..., WN comportant un second nombre n de cellules mémoire (E1, E2, ..., En), ledit second nombre étant supérieur à un, contenant chacune une valeur binaire non volatile et les n cellules mémoire (E1, E2, ..., En) de chaque registre de valeur W1, W2, ..., WN sont inscriptibles en même temps par au moins une première valeur, caractérisée en ce    que le registre de marquage (7) comprend un troisième nombre M de cellules mémoire (M2, ..., MN) contenant chacune une unité de valeur non volatile, ledit troisième nombre étant plus petit d'une unité que le premier nombre N.
       qu'à un registre de valeur Wi de rang supérieur à un registre de valeur Wi-1 n'est associée qu'une seule cellule mémoire (Mi) du registre de marquage (7),
       que les cellules mémoire (Mi) du registre de marquage (7) associées au registre dé valeur Wi sont inscriptibles en même temps qu'une cellule mémoire (Ek) du registre de valeur Wi par une seconde valeur et
       que les cellules mémoire (Mi) du registre de marquage (7) associées au registre de valeur Wi sont inscriptibles en même temps que les n cellules mémoire (E1, E2, ..., En) du registre de valeur Wi-1 de rang inférieur au registre de valeur Wi par la première valeur.
  2. Procédé de décalage d'une grandeur (G, G') représentée par des unités de valeur binaires sur une carte de valeur à partir d'un premier registre de valeur Wi vers un second registre de valeur Wi+1 directement de rang supérieur au premier registre de valeur Wi, chaque registre de valeur Wi, Wi+1 comprenant un nombre n de cellules mémoire (E1, E2, ..., En), où le nombre n est plus grand que un, contenant chacune une valeur binaire non volatile, une grandeur maximale mémorisable dans le premier registre de valeur Wi étant équivalente à une seule unité de valeur du second registre de valeur Wi+1 , la grandeur (G, G') à décaler étant équivalente à la grandeur maximale mémorisable dans le premier registre de valeur Wi, la grandeur (G, G') à décaler étant mémorisée dans le premier registre de valeur Wi, dans le second registre de valeur Wi+1 encore au moins une unité de valeur étant mémorisable et la grandeur (G, G') étant à décaler à partir du premier registre de valeur Wi vers le second registre de valeur Wi+1 caractérisé en ce    qu'au second registre de valeur Wi+1 est associé exactement un bit (Mi+1) d'un registre de marquage (7)
       que l'état binaire d'une cellule mémoire déterminée (Ek) du second registre de valeur Wi+1 et le bit (Mi+1) associé au second registre de valeur Wi+1 du registre de marquage (7) sont inversés selon un processus d'exécution ininterruptible et
       que les états binaires des (n) cellules mémoire (E1, E2, ... , En) du premier registre de valeur Wi et le bit (Mi+1) associé au second registre de valeur Wi+1 du registre de marquage (7) sont inversés selon un processus d'exécution ininterruptible complémentaire.
  3. Procédé de décalage d'une grandeur (G") représentée par des unités de valeur binaires sur une carte de valeur à partir d'un premier registre de valeur Wi vers un second registre de valeur Wi-1 directement de rang inférieur au premier registre de valeur Wi, chaque registre de valeur Wi, Wi-1 comprenant un nombre n de cellules mémoire (E1, E2, ..., En), où le nombre n est plus grand que un, contenant chacune une valeur binaire non volatile, une grandeur maximale mémorisable dans le second registre de valeur Wi-1 étant équivalente à une seule unité de valeur du premier registre de valeur Wi , la grandeur (G") à décaler étant équivalente à la grandeur maximale mémorisable dans le second registre de valeur Wi-1, la grandeur (G") à décaler étant mémorisée dans un bit du premier registre de valeur Wi, le second registre de valeur Wi-1 étant vide et la grandeur (G") étant à décaler à partir du premier registre de valeur Wi vers le second registre de valeur Wi-1 caractérisé en ce    qu'au premier registre de valeur Wi est associé exactement un bit (Mi) d'un registre de marquage (7)
       que l'état binaire d'une cellule mémoire déterminée (Ek) du premier registre de valeur Wi et le bit (Mi) associé au premier registre de valeur Wi du registre de marquage (7) sont inversés selon un processus d'exécution ininterruptible et
       que les états binaires des (n) cellules mémoire (E1, E2, ... , En) du second registre de valeur Wi-1 et le bit (Mi) associé au premier registre de valeur Wi du registre de marquage (7) sont inversés selon un processus d'exécution ininterruptible complémentaire.
EP95105700A 1994-05-06 1995-04-15 Carte de valeur avec unités de valeur binaires et méthode pour décaler sur la carte une quantité, exprimée en unités de valeur binaires Expired - Lifetime EP0681274B1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
CH142594 1994-05-06
CH1425/94 1994-05-06
CH142594 1994-05-06
CH3052/94 1994-10-11
CH305294 1994-10-11
CH305294 1994-10-11

Publications (3)

Publication Number Publication Date
EP0681274A2 EP0681274A2 (fr) 1995-11-08
EP0681274A3 EP0681274A3 (fr) 1998-06-03
EP0681274B1 true EP0681274B1 (fr) 2005-06-08

Family

ID=25687619

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95105700A Expired - Lifetime EP0681274B1 (fr) 1994-05-06 1995-04-15 Carte de valeur avec unités de valeur binaires et méthode pour décaler sur la carte une quantité, exprimée en unités de valeur binaires

Country Status (7)

Country Link
EP (1) EP0681274B1 (fr)
AT (1) ATE297577T1 (fr)
CZ (1) CZ286328B6 (fr)
DE (1) DE59511003D1 (fr)
FI (1) FI952166A (fr)
NO (1) NO307633B1 (fr)
PT (1) PT681274E (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0321727B1 (fr) * 1987-12-17 1992-03-18 Siemens Aktiengesellschaft Méthode et circuit de protection contre la manipulation de dévalorisation de mémoires EEPROM
FR2678094B1 (fr) * 1991-06-20 1993-10-08 France Telecom Carte a memoire de comptage de donnees et appareil de lecture.
FR2698468B1 (fr) * 1992-11-20 1995-03-10 Monetel Procédé de gestion de cartes à mémoire de type Boullier.

Also Published As

Publication number Publication date
PT681274E (pt) 2005-10-31
CZ117795A3 (en) 1996-02-14
EP0681274A3 (fr) 1998-06-03
DE59511003D1 (de) 2005-07-14
NO951777D0 (no) 1995-05-05
FI952166A0 (fi) 1995-05-05
NO307633B1 (no) 2000-05-02
NO951777L (no) 1995-11-07
CZ286328B6 (cs) 2000-03-15
FI952166A (fi) 1995-11-07
ATE297577T1 (de) 2005-06-15
EP0681274A2 (fr) 1995-11-08

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