CZ117795A3 - Value card with binary value units and procedure of shifting the value represented by the binary value units disposed on the value card - Google Patents

Abstract

A storage module (1) and an access module (2) are interconnected by data and control signal lines (3). The register block (6) of the storage module comprises N value registers (W1-WN) each contg. n binary storage cells (E1-En). These are nonvolatile and any failure or removal of the power supply results in no loss of data from either the register block cells or those (M2-MN) of the mark register (7). Data can be shifted to the next higher register (e.g. W2) where the state of a particular cell and the associated bit of the mark register are inverted in uninterruptable execution steps. <IMAGE>

Description

Value card with binary value units and the procedure for moving a value represented by binary value units to a value card - 'f 5

Technical field

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The invention relates to a value card with binary value units and to a method for moving a value represented by binary value units on a value card.

BACKGROUND OF THE INVENTION

Such value cards are preferably used in vending machines for a wide variety of services - for example, in payphones, where the value cards comply, for example, with ISO 7816.

A value card of this kind is known from EP 0 519 847 A1 and has binary value units stored in a number p in arranged registers. One register has a certain number of n equal value units whose quality depends on the class of the register. The total value of one register is as large as the individual value unit of a register that is immediately superior to that register. When transferring the total value of a register to the value unit of the register immediately superior to that register, it is necessary to perform several successive steps in the known storage techniques, which must be performed perfectly in order to maintain the value card value stability. In order to be able to recognize imperfect transmission, the known value card additionally has p -1 marker registers, each with a capacity of n bits, each bit of the parent register being assigned one bit of the marker register. The transmission of the total value of a register to the value unit of a register that is superior to that register is marked in the bit assigned to the value unit of the parent register for the duration of the transmission sequence. If the value card has p * n bits to display its value, additional (p-1) * n bits are required to mark.

It is an object of the present invention to provide a value card whose value is reliably changeable, and at the same time to provide a procedure so that little space is consumed from the space available on the value card to achieve the desired reliability in value change.

SUMMARY OF THE INVENTION

Said object is achieved by a value card with binary value units having a first number of ordered value registers, the value register having a second number of memory cells, each of which can be set together for at least one binary lost value unit and the value register memory cells. one first value according to the invention, characterized in that the value card further has a marker register, that the marker register has a third number of memory cells for binary lost values, that the third number is one less than the first number that the value register, which is superior to the other value register, the marker register memory cell is assigned that the marker register memory cell associated with the value register together with the value register memory cell can be set to a second value, and e memory cell marking registry of values assigned to the register memory cells together with the register value can be set to the first value.

A method for moving a value represented by binary value units on a value card from a first value register to a second value register that is immediately superior to the first value register, the value register having a number of n memory cells, each of which is for one binary lost value unit, wherein the maximum storable quantity in the first value register is as large as the individual value unit of the second value register, the quantity to be moved is the same as the maximum storable quantity in the first value register, the quantity to be moved is stored in the first value register, at least one value unit can be stored in the second value register and the quantity to be moved can be moved from the first value register to the second value register according to the invention characterized in that exactly one bit of the marker register is assigned to the second value register, that the binary state of a particular memory cell of the second value register is inverted and the marker register bit assigned to the second value register in one uninterruptible execution register; The binary states of the memory cells of the first value register and the marker register bit associated with the second value register are inverted in a further uninterruptible execution step.

Overview of the drawings

Examples of embodiments of the invention will be explained below with reference to the drawings, in which the figures show:

Giant. 1: block diagram of part of the value card,

Fig. 2: registration block and tag register of the value card memory module,

Fig. 3: Registration block and marker register before and after the correction cycle

Fig. 4: variant of using the registration block a

Fig.5: variant of application before and after the correction cycle.

DETAILED DESCRIPTION OF THE INVENTION

The value card (Fig. 1) has a memory module 1 and an access module 2, which is connected by the signal line 3 to the memory module L The signal lines 3 comprise data and control lines through which the information stored in the memory module can be read and / or changed. The access module preferably has one input 4 and one output 5, wherein the input 4 together with the output 5 can also be implemented as a bi-directional data channel. The access module 2 is preferably provided with a microprocessor.

The memory module 1 comprises a registration block 6 and a markup register 7. The registration block 6 has a first number of N value registers Wj to Wpp each containing a second number n of memory cells Ej to E _n , each for one binary lost value unit. In the example shown, the first number N is equal to three and the second number n is equal to eight. The first number N and the second number n are essentially natural numbers which are adaptable to the purpose of the value card. In general, the second number n for the value register Wj and / or the value register W1, respectively. Wg resp. Wpj is freely selectable, wherein in the example shown, the second number n for each value register Wj to Wpj of registration block 6 is equally large.

The quantity stored in one memory cell of the i-th value register Wj is dependent on the valid value unit of the memory cell Ej and the binary value or value. the logical state of the memory cell. Preferably, the value unit of the memory cell E1 of the value register Wj is dependent on the degree of the value register Wj in the valid order of the registration block 6. In the preferably dimensioned registration block 6, the value registers Wj to Wfq are ordered in such a way value register W; or else expressed that for index i from 2 to N, the value register W1i is subordinate to the value register Wj.

The quantity herein includes a binary value and a value unit, wherein the value unit has a numerical value expressing the unit of measure or has a meaning assigned to that numerical value. Examples of value units include 8 kWh, 16 tax pulses, 10 francs and 64 m.

Preferably, the maximum storable variable in one value register Wj-i is as large as the value unit of a single memory cell Ej of the value register Wj of the immediately superior value register Wj-i.

If, in one example, the value unit of the memory cell E W of the value register Wj is eight rate pulses, and if n = 8, then when the memory cell has a logical state of 1, the quantity stored in the memory cell E ^ is interpreted as 8 rate pulses. when the memory cell has a logical state of 0, the quantity stored in the memory cell Ek is interpretable as zero rate pulses. Further, for example, the maximum storage quantity in the value register Wj is preferably set at 8 rate pulses, while the maximum storage quantity in the value register Wj is preferably 64 rate pulses.

The memory technology of the memory module i is selected so as not to lose the current state or the binary value of the memory cell Ej, respectively. E2 resp. E _{n of the} registration block 6 in the event of a power failure or disconnection of the memory module I as well as to not lose the current state or the binary value of the memory cells M2 or the memory cells. M] \ f markup registry failure or disconnection of the power supply I. Memory Module The memory module as well-EERR-OM (eleetr-ieal capable of associating erasahle-programmable-read-only-memory) ^- or 'EAPROM (Electrically Programmable Read alterable only memory).

During the process of reading the value units on the value card, it is necessary to transfer the maximum storable quantity in the memory register to one bit of the value register Wf + j, which is immediately superior to the value register Wj when the maximum storable quantity in the value register Wj has to be exceeded.

In Fig. 2a, in the second value register Wg is stored the quantity G, which is represented by n memory cells Ej to ^ E _n , set to logic 1,

Hereinafter, the procedure by which the variable G is moved in a favorable manner in two actions to be performed in succession to the value register Wjg, immediately superior to the second value register Wg, will be described, assuming that they have at least one of cells Ej to E _{n of the} parent value register Wjg, and also a marker register memory cell assigned to the parent value register a logical value of 0.

In the first operation, the binary state of the memory cell E4 of the parent value register Wyj, which has a logical value of 0, is inverted and the bit Mjg of the marker register 7 assigned to the parent value register is transformed in one uninterruptible execution step. 2b shows the registration block 6 and the marker register 7 after the first operation, wherein the memory cells changed during the first operation are shaded.

In the second operation, the binary states of the memory cells E {to E _{n of the} value register Wg, which exhibit the quantity G, are transformed and the bit of the marker register 7 assigned to the value register W 6, the parent value register Wp, is changed in another uninterruptible execution step. optionally logic 0 is used. 2c shows the registration block 6 and the marker register 7 after the second operation, wherein the memory cells changed during the second operation are shown shaded.

The described procedure is applicable to transfer another quantity G from the first value register Wj to the value register W2, which is superior to the value register Wj, the first operation inverting the binary state of the memory cell Ej of the higher value register W2, which has a logical value 0, the bit M2 of the marker register 7, which is assigned to the parent value register W2, in one uninterruptible execution step, or both logic 1 are deployed and the binary states of the memory cells Ej to E _{n of the} value register Wj are reversed in the second operation. having the value G, and the bit M2 of the marker register 10, which is assigned to the value register W2, the parent value register W1, is converted in a further uninterruptible execution step, or logic 0 is applied. 2d shows the registration block 6 and the marker register 7 after the first operation to move the variable G, while FIG. 2e shows the registration block 6 and the marker register 7 after the second operation, the memory cells changed in both operations are shown in shaded.

The memory module i and the access module 2 are arranged such that the value register Wj associated with the memory cell Mj of the register register 7 together with the memory cell Ej of the value register Wj are adjustable to the first binary value and cells Ej to E _{n of the} value register Wj, subordinate to the value register Wj, are adjustable to a value inverse to the first binary value.

If the procedure to move the variable G or the input is deliberately interrupted. G 'on the value card between the first and the second activity, the incomplete transfer is later recognizable by the evaluation of the marker register 7 and thus also correctable, which makes the transfer absolutely reliable.

Giant. 3a shows the memory module 1 in a state in which the Nth bit Mjq of the marker register 7 shows a logical value of 1, whereby the bit in this case indicates that the transfer was incomplete. For example, this state can occur when a value card that has a memory module i is deliberately or unintentionally pulled out of the reader at the moment when the quantity G is to be moved. —You — doU-Correction — eyklus — involves inverting^-rr memory cells Ej to E_n The value register W1 is assigned to the nth bit Myj of the marker register 7, and at the same time the nth bit of the My marker marker is reset to logic 0. FIG. 3b shows the state of the memory module I after the correction cycle.

The test sequence for recognizing an incomplete move with a conditional correction cycle on a value card can be described in a pseudocode similar to the Pascal programming language as follows:

for i = 2 to N to begin if M [1] - 1 then

W [i-1] = 0 {clear registry Wj.j} end

The test sequence is preferably performed after inserting the value card into the reader, preferably the test sequence is performed by the value card processor.

Since the value card has a marker register 7, which makes the transfer of the G or the values of the G-value incomplete. G 'recognizable and correctable in the test sequence, it is possible to omit machinery and expensive locking systems from the reader because pulling a value card in operating condition does not give the user any advantages or disadvantages regarding the value of the value card.

The memory module 1 is preferably programmable via input 4, i.e. the value stored on the value card can be changed via input 4, preferably at least one card status information at output 5 being provided, e.g. non-empty.

Said process for moving a quantity represented by a binary value unit is preferably applicable in reliable methods of adding or reading value units on a value card. The procedure is simply transferable to the corresponding variants in the negative logic and / or to delete the value units on the value card. It goes without saying that an incomplete transfer in the registration block 6 can be marked in one bit of the marker register 7 either as shown in FIG. 3, logical 1 or then logical 0.

During the process of deleting the value units of a value card, it is necessary to transfer quantities that can be stored in a "one bit". the value register Wj, to the value register Wy_y immediately subordinate to the value register Wj when the sub-value register Wy_y is empty.

In one variation of the use of the memory module 1 shown in Fig. 4, the incomplete transmission in the registration block 6 is marked in logic 7 in the register register 7. The state of the register 7 shown in Fig. 4a in which all bits are set to logical 1. therefore, there is no incomplete move in register block 6. In one bit of the Nth value register Wy ^ y it is possible to store a certain quantity G.

Hereinafter, the procedure for transferring the value G in two successive operations to the value register Wyj.y, which is immediately subordinate to the Nth value register Wyy, will be described, assuming that the memory cells have Ey before the move to E _n child value register Wy \ [- 1 logical value 0.

In the first operation, the binary state of the memory cell E4 of the Nth value register Wy-j having a value of logic 1 is inverted and the bit Myj of the register register 7 associated with the value register Wyq is inverted in one continuous execution step. Giant. 4b shows the registration block 6 and the marking register 7 after. terminating the first operation, wherein the memory cells that have changed during the first operation are shown in shaded form.

In the second operation, the memory cells Ey to E _{n of the} value register Wyy_i and the bit My \ y of the marker register 7 associated with the value register Wy \ y to the value register Wyj.y are transformed into a further uninterruptible execution step or logic 1 is set. . 4c shows the registration block 6 and the mark-up register 7 after the second operation has been completed, with the memory cells changed during the second operation being shown in shaded form.

Giant. 5a shows the memory module J in a state in which the Nth bit Mjg of the marker register 7 has a logical value of 0, whereby the bit in this case indicates that an incomplete transfer has taken place. This state can occur, for example, when a value card having a memory module 7, whether intentionally or unintentionally, is pulled out of the reader just when the quantity G is to be moved. The move can be terminated in this state by means of a correction cycle. The correction cycle involves inverting n memory cells E1 to E _{n of the} value register W ^ _ |, which is immediately subordinate to the value register Wj <f, which is assigned to the Nth bit of the marker register 7. Simultaneously with inverting n memory cells E} to E _{n of the} value register W ^ _ | also, the Nth bit of the marker register is put back on the logic 1. FIG. 3b shows the state of the memory module even after the correction cycle.

If a value card has N * n memory cells to represent its value, then additional memory cells of N - 1 are required to indicate the move.

Since the marker register 7 has only one bit for each value register W2-Wjg, which is superior to another value register W1-W1g, it is possible to achieve a relatively large saving of E memory cells, which can be achieved with the first N and the second number n can be calculated using the formula:

Ε = η * (N-1) - (N-1) = (N-1) * (η-1) [Fl]

It can be clearly seen in formula F1 that the saving E is greatest for N = n. The saving E is the memory space necessary for a reliable change of the value stored on the value card relatively small relative to the memory space available in the registration block 6 for storing values.

Claims (3)

A value card with binary value units having a first number (N) of ordered value registers (Wj, W2> W ^), the value register (Wj; Wg; Wpj) having a second number (n) of memory cells (Ej, Eg) , E _n ), each of which is for one binary lost value unit and (n) memory cells (E j, Eg, E _n ) the value register (Wj; Wg; Wpp) can be set together to at least one first value, characterized in that the value card further has a marker register (7), the marker register (7) has a third number (M) of memory cells (M2, Mp> j) for binary lost values that the third count (M) is one less than the first count (N) that the value register (Wj), which is superior to the next value register (Wj_i), is assigned a memory cell (Mj) of the marker register (7), that the memory cell (Mj) of the marker register (7) associated with the value register (Wj) together with the memory cell (Ep) of the value register (Wj) can be set to a second value; the marker register cell (Mi) associated with the value register (Wj), together with the (n) memory cells (Ej, Eg, E _n ) of the value register (Wj), can be set to the first value. A method for moving a value (G; G ') represented by binary value units on a value card from a first value register (Wj) to a second value register (Wj + j) that is immediately superior to the first value register (Wj), the value register (Wj; Wj + j) has a number (n) of memory cells (Ej, Eg, ..., E _n ), each of which is for one binary lost value unit, the maximum storable quantity in the first value register (Wj) ) is as large as the individual value unit of the second value register (Wj + j), the quantity (G; G ') to be shifted is the same as the maximum storable quantity in the first value register (Wj), the quantity (G; G ') to be moved is stored in the first value register (Wj), in the second value register (Wj + j) it is possible to store at least one value unit and the quantity (G; G') move, it is possible to move from the first -hodnotového-registru- (Wjj-to-registry druhého'hoďnOťového ^ ^_ (Wp) rj) 7Tvž «ACA / 7éz'5E that the second register of values (Wj + j) is assigned exactly one bit (Mi + j) marking a register (7) that inverts the binary state of a particular memory cell (E0 of the second value register (Wj + j) and a bit (Mj + j) of the marker register (7) that is assigned to the second value register (Wj + j) in one and that the binary states (n) of the memory cells (Ej, Ey, · E _n ) of the first value register (Wj) and the bit (Mj + j) of the marker register (7) associated with the second value register (Wj +) are inverted. j), in a further uninterruptible implementation step. A method for moving a value (G) represented by binary value units on a value card from a first value register (Wj) to a second value register (Wj.j) that is immediately subordinate to the first value register (Wj), wherein the value register ( Wj; Wj.j) has a number (n) of memory cells (Ej, Ey, ···, E _n ), each of which is intended for one lost value unit, the maximum storable quantity in the second value register is as large as the individual the value unit of the first value register (Wj), the quantity (G) to be moved is the same as the maximum storable quantity in the second value register (Wj.j), the quantity (G) to be moved is stored in one bit the first value register (Wj), the second value register (Wj.j) is empty and the quantity (G) to be moved can be moved from the first value register (Wj) to the second value register (Wj), characterized in that the first value register (Wj) is assigned exactly one bit (Mj) of the marker register (7), such that the binary state of a particular memory cell (E0) of the first value register (Wj) ) and bit (Mj) of the marker register (7) associated with the first value register (Wj) in one uninterruptible execution step and that the binary states (n) of the memory cells (Ej, Ey, ··., E _n ) of the second value a register (Wj) and a bit (Mj) of the marker register (7) associated with the first value register (Wj) in the next uninterruptible execution step.