EP0681274B1 - Value card with binary value units and method to shift on the value card a quantity, expressed in binary value units - Google Patents

Abstract

A storage module (1) and an access module (2) are interconnected by data and control signal lines (3). The register block (6) of the storage module comprises N value registers (W1-WN) each contg. n binary storage cells (E1-En). These are nonvolatile and any failure or removal of the power supply results in no loss of data from either the register block cells or those (M2-MN) of the mark register (7). Data can be shifted to the next higher register (e.g. W2) where the state of a particular cell and the associated bit of the mark register are inverted in uninterruptable execution steps. <IMAGE>

Description

The invention relates to a prepaid card with binary value units and to a method for Moving a value represented by binary units of value on the prepaid card according to The preambles of claims 1 and 2.

Such prepaid cards are advantageous in service machines - for example in telephone machines - used, for example, the prepaid cards comply with the standard ISO 7816.

A value card of this type is known (EP 0 519 847 A1), in which binary value units are in one Number p ordered registers are stored. A register has a certain number n equal Value units whose valency is dependent on the rank of the register. The entire value of a Register is the same size as a single unit of value of the register immediately higher Register. When transferring the entire value of a register to a unit of value of the Registers immediately above register are several sequential in known memory techniques Steps are necessary, which must be carried out completely, so that the consistency of the value of the Value card is retained. For an incomplete transfer can be made visible, points the known prepaid card additionally has the number p-1 marker registers of n bits each, each bit a parent register is assigned a bit of a tag register. Transferring the The total value of a register on a unit of value of a registry superordinate register is in the bit assigned to the value unit of the higher-order register for the duration of the transmission sequence marked. If the value card has p * n bits to represent its value, then additionally (p-1) * n Bits required for marking.

The invention is based on the object, a value card whose value is reliably changed, so to and to provide a method that has little of the space available on the prepaid card Memory space for means to achieve reliability required in modifying the value is consumed.

The stated object is achieved according to the invention by the features of claims 1 and 2.

Embodiments of the invention will be explained in more detail with reference to the drawing.

Fig. 1

ein Blockschaltbild eines Teils einer Wertkarte,

Fig. 2

einen Registerblock und ein Markierungsregister eines Speichermoduls der Wertkarte,

Fig. 3

der Registerblock und das Markierungsregister vor und nach einem Korrekturzyklus,

Fig. 4

eine Anwendungsvariante des Registerblocks und

Fig. 5

die Anwendungsvariante vor und nach dem Korrekturzyklus.

Show it:

Fig. 1

a block diagram of part of a prepaid card,

Fig. 2

a register block and a tag register of a memory module of the prepaid card,

Fig. 3

the register block and the tag register before and after a correction cycle,

Fig. 4

an application variant of the register block and

Fig. 5

the application variant before and after the correction cycle.

A value card has a memory module denoted by 1 in FIG. 1 and an access module 2 which is connected via signal lines 3 to the memory module 1. The signal lines 3 comprise data and control lines, through which a stored in the memory module 1 information from the access module is readable and / or changeable. The access module 2 advantageously has an input 4 and a Output 5, wherein the input 4 together with the output 5 as a bidirectional data channel is executable. The access module 2 advantageously has a microprocessor.

The memory module 1 comprises a register block 6 and a marker register 7. The register block 6 has a first number N of value registers W ₁ to W _N , which each comprise a second number n of binary memory cells E ₁ to E _n for each binary non-lossable value unit. In the example shown, the first number N is three and the second number n is eight. Basically, the first number N and the second number n are natural numbers that are adaptable to the purpose of the prepaid card. In general, the second number n for a value register W ₁ or W ₂ or W _{N is} freely selectable, in the illustrated example, the second number n for each value register W ₁ to W _{N of} the register block 6 is the same size.

The variable which can be stored in a memory cell E _{k of} the ith value register W _i depends on the valid value unit of the memory cell E _k and the binary value or the logic state of the memory cell E _k . Advantageously, the value unit of the memory cell E _{k of} the value register W _i depends on the rank of the value register W _i in the valid order of the register block 6. In an advantageously designed register block 6, the value registers W ₁ to W _{N are} ranked such that for an index i from 2 to N the value register W _i is superordinate to the value register W _i-1 , or in other words, for an index i of 2 until N the value register W _{i-1 is} subordinate to the value register W _i .

A variable here comprises a binary value and a unit of values, whereby the unit of value comprises a Numerical value and a numerical value assigned unit or meaning has. As examples of Value units are here called 8 kWh, 16 tax pulses, 10 francs and 64 m.

Advantageously, the _i-1 storable maximum size _k is equal to the value unit of a single memory cell in an E value register W of the value register W _i-1 immediate parent value register W _i.

If the value unit of the memory cell E _{k of} the value register W _{i is} eight tax pulses in one example and n = 8, then if the memory cell E _{k has} the logic state "1", the quantity stored in the memory cell E _{k is} 8 tax pulses, and, if the memory cell E _{k has} the logic state "0", the value stored in the memory cell E _k can be interpreted as zero tax pulses. Further, in the example, the maximum size which can be stored in the value register W _{i-1 is} advantageously set to 8 tax pulses, while the maximum size which can be stored in the value register W _{i is} advantageously 64 tax pulses.

The memory cryology of the memory module 1 is selected so that a current state or binary value of the memory cell E ₁ or E ₂ or E _{n of} the register block 6 in case of failure or removal of the supply of the memory module 1 is not lost and also a current state or binary Value of the memory cells M ₂ , or M _{N of} the marker register 7 is not lost in case of failure or removal of the power of the memory module 1. The memory module 1 is, for example, an EEPROM (electrically erasable programmable read only memory) or an EAPROM (electrically alterable programmable read only memory).

Is within a method for summing up of units of value to the value card in a value register W _i maximum storable size inevitably a bit of the value register W _i immediate parent value register W _{i +} to be transferred ₁ when exceeding the maximum storable size in the value register W _i is.

In FIG. ₂ a, a quantity G is stored in the second value register W ₂ , which is represented by n memory cells E ₁ to E _n set to logic "1".

The following describes a method by which the quantity G is advantageously shifted in two successive actions to the value register W _N immediately above the second value register W ₂ , it being assumed that at least one of the memory cells E ₁ before the displacement to E _{n of} the parent value register W _N and further also the memory cell M _{N of} the marker register assigned to the higher-order value register W _{N have} the value logical "0".

In a first action, the binary state of a memory cell E ₄ having the value logical "0" of the higher-order value register W _N and the bit M _{N of} the marker register 7 assigned to the higher-order value register W _N are inverted in a non-interruptible execution step, or to logic "1 " set. FIG. 2b shows the register block 6 and the marker register 7 after the completion of the first action, whereby the memory cells changed in the first action are shown hatched.

In a second action, the binary states of the size of G having memory cells E ₁ to E _n of the value register W ₂ and the value register W ₂ parent value register W _N assigned bit M _N of the marking register 7 in a further uninterruptible execution step inverted respectively to logic Set to "0". Fig. 2c shows the register block 6 and the marker register 7 after the completion of the second action, wherein the memory cells changed in the second action are shown hatched.

The described method is applicable for shifting a further variable G 'from the first value register W ₁ into the value register W ₂ , which is superordinate to the first value register W ₁ , wherein in the first action the binary state of a memory cell E _{1 of} the superordinate one has the value logical "0" Value register W ₂ and the bit M _{2 of} the marker register 7 assigned to the higher-order value register W ₂ are inverted or set to logical "1" in a non-interruptible execution step and the binary states of the memory cells E ₁ to E having the size G 'in the second action _{n of} the value register W ₁ and the value register W ₁ superordinate value register W ₂ associated bit M _{2 of} the marker register 7 are inverted in a further non-interruptible execution step or set to logic "0". FIG. 2d shows the register block 6 and the marker register 7 after the completion of the first action to shift the quantity G ', while FIG. 2e shows the register block 6 and the marker register 7 after the completion of the second action Actions modified memory cells are shown hatched.

The memory module 1 and the access module 2 are designed such that the value register W _i associated memory cell M _i of the marking register 7 together with a memory cell E _k of the value register W _i are settable to a first binary value and that the value register W _i associated memory cell M _{i of} the mark register 7 together with the n memory cells E ₁ to E _n of the value register W _i subordinate value register W _{i-1 can be set} to the value inverse to the first binary value.

If the method for shifting a size G or G 'on the prepaid card between the first Action and the second action intentionally or interrupted by a fault, so is the incomplete Shift later by evaluating the marker register 7 recognizable and thus also correctable, so that the shifting is reliably completely executable.

In Fig. 3a, the memory module 1 in a state in which the Nth bit M _{N of} the marker register 7 has the value logical "1", in which case the bit indicates that a shift has been performed incompletely. The state may occur, for example, when the value card having the memory module 1 is deliberately or unintentionally pulled out of a card reader just when the size G is to be shifted. The shifting can be completely locked in this state by a correction cycle to be carried out. The correction cycle comprises inverting the n memory cells E ₁ to E _n of the value register W _{N-1 associated} with the Nth bit M _{N of} the marker register 7, and at the same time also resetting the Nth bit M _{N of} the marker register to logic "0" , FIG. 3b shows the state of the memory module 1 after the correction cycle.

A test sequence for detecting an incomplete shift with a conditionally performed correction cycle on the prepaid card is writable in a pseudocode similar to the Pascal programming language as follows:

The test sequence is advantageously carried out after inserting the prepaid card into a card reader. Preferably, the test sequence is performed by a processor of the prepaid card.

Since the prepaid card has a mark register 7, which performed incomplete Shifts of values G and G 'in the test sequence can be identified and corrected by the Card readers are dispensed with mechanical transport devices and expensive closures, as a duch Extracting the prepaid card in the operating state for the user with regard to the value of the prepaid card neither advantages nor disadvantages can be achieved.

The memory module 1 is advantageously programmable via the input 4, that is, one on the Value card stored value via the input 4 is variable, with at least one advantage Status information - for example, empty or not empty - the value card is available at the output 5.

The method shown is to shift a quantity represented by binary value units advantageous in reliable methods for counting or adding up units of value on the prepaid card used. The method is simple on corresponding variants in negative logic and / or for Debiting units of value on the prepaid card transferable. It goes without saying that one in the Register block 6 incomplete shift in one bit of the marker register 7 either as shown in FIGS. 2 and 3, with logic "1" or markable with logic "0".

Within a method for debiting monetary units of value map the storable in a bit of a value register W _i variable is to the value register W _i of immediately subordinate value register W to transfer inevitably _i-1, when the subordinate value register W is empty _I-1.

In an application variant of the memory module 1 shown in FIG. 4, an offset carried out incompletely in the register block 6 in the marker register 7 is marked by logic "0". The state of the marker register 7 shown in FIG. 4a, in which all bits are set to logic "1", thus does not indicate any incompletely performed shifts in the register block 6. In one bit of the Nth value register W _N , a certain size G "can be stored.

The following describes a method by which the quantity G "is advantageously shifted in two successive actions to be performed in the value register W _N-1 immediately following the N-th value register W _N , it being assumed that before the shift Memory cells E ₁ to E _{n of} the subordinate value register W _{N-1 have} the value logical "0".

In a first action, the binary state of a memory cell E ₄ having the value "1" of the N-th value register W _N and the bit M _{N of} the marking register 7 assigned to the value register W _N are inverted in a non-interruptible execution step, or logically " 0 "set. Fig. 4b shows the register block 6 and the marker register 7 after the completion of the first action, wherein the memory cells changed in the first action are shown hatched.

In a second action, the memory cells E ₁ to E _n of the value register W _N-1 and the value register W _N-1 higher-level value register W _N assigned bit M _N of the marking register 7 in a further uninterruptible execution step inverted respectively to logic "1" set. Fig. 4c shows the register block 6 and the marker register 7 after the completion of the second action, wherein the memory cells changed in the second action are shown hatched.

In Fig. 5a, the memory module 1 in a state in which the Nth bit M _{N of} the marker register 7 has the value of logical "0", in which case the bit indicates that a shift has been performed incompletely. The state may occur, for example, if the value card having the memory module 1 is deliberately or unintentionally pulled out of a card reader just when the size G "is to be shifted Inverting the n memory cells E ₁ to E _{n of} the value register W _N-1 , which is subordinate to the value register W _N assigned to the Nth bit M _{N of} the marker register 7. Simultaneously with the inversion of the n memory cells E ₁ to E _{n of} the value register W _N-1 , the Nth bit M _{N of} the marker register is also reset to logic "1." The state of the memory module 1 after the correction cycle is shown in FIG.

If the value card has N * n memory cells for representing its value, then there are additionally N-1 Memory cells required to mark a shift.

Characterized in that the marking register 7 has only one bit for each value register W ₂ to W _N having a different value register W ₁ to W _N-1, a relatively large saving E of memory cells can be achieved with the advantageous method compared with the prior art, which can be calculated with the first number N and the second number n according to a formula F1: E = n * (N-1) - (N-1) = (N-1) * (n-1). In the formula F 1 it is clear that the saving E is greatest for N = n. By saving E, the memory required to reliably change a value stored on a prepaid card is relatively small to the storage space available in register block 6 for storing the value.

Claims (3)

1. Value card with binary value units comprising a first number N of ordered value registers W₁, W₂, ..., W_N and a marking register (7), each value register W₁, W₂, ..., W_N including a second number n of memory cells (E₁, E₂, ..., E_n), said second number being greater than one, containing each a non volatile binary value and the n memory cells (E₁, E₂, ..., E_n) of each value register W₁, W₂, ..., W_N are writable together by at least a first value, characterized in that
      the marking register (7) comprises a third number M of memory cells (M₂, ..., M_N) containing each a non volatile value unit, said third number being smaller of an unit than the first number N,
      to a value register W_i of a rank higher than a value register W_i-1 is associated only one memory cell (M_i) of the marking register (7),
      the memory cell (M_i) of the marking register (7) associated to the value register W_i are writable together with a memory cell (E_k) of the value register W_i by a second value and
      the memory cell (M_i) of the marking register (7) associated to the value register W_i are writable together with the n memory cells (E₁, E₂, ..., E_n) of the value register W_i-1 of a rank lower than the value register W_i by the first value.
2. Process for shifting a magnitude (G, G') represented by binary value units on a value card from a first value register W_i to a second value register W_i+1 directly of a higher rank than the first value register W_i ,each value register W_i, W_i+1 comprising a number n of memory cells (E₁, E₂, ..., E_n), where the number n is greater than one, containing each a non volatile binary value, a maximum magnitude storable in the first value register W_i being equivalent to only one value unit of the second value register W_i+1 , the magnitude (G, G') to shift being equivalent to the maximum magnitude storable in the first value register W_i the magnitude (G, G') to shift being stored in the first value register W_i , in the second value register W_i+1 still at least one value unit being storable and the magnitude (G, G') to be shifted from the first value register W_i to the second value register W_i+1 characterized in that
      to the second value register W_i+1 is associated exactly one bit (M_i+1) of a marking register (7),
      the binary state of a determined memory cell (E_k) of the second value register W_i+1 and the bit (M_i+1) associated to the second value register W_i+1 of the marking register (7) are inverted according to an uninterruptible execution process and
      the binary states of the (n) memory cells (E₁, E₂, ... , E_n) of the first value register W_i and the bit (M_i+1) associated to the second value register W_i+1 of the marking register (7) are inverted according to a further uninterruptible execution process.
3. Process for shifting a magnitude (G") represented by binary value units on a value card from a first value register W_i to a second value register W_i-1 directly of a lower rank than the first value register W_i ,each value register W_i, W_i-1 comprising a number n of memory cells (E₁, E₂, ..., E_n), where the number n is greater than one, containing each a non volatile binary value, a maximum magnitude storable in the second value register W_i-1 being equivalent to only one value unit of the first value register W_i , the magnitude (G") to shift being equivalent to the maximum magnitude storable in the second value register W_i-1 , the magnitude (G") to shift being stored in a bit of the first value register W_i , the second value register W_i-1 being empty and the magnitude (G") to be shifted from the first value register W_i to the second value register W_i-1 characterized in that
      to the first value register W_i is associated exactly one bit (M_i) of a marking register (7),
      the binary state of a determined memory cell (E_k) of the first value register W_i and the bit (M_i) associated to the first value register W_i of the marking register (7) are inverted according to an uninterruptible execution process and
      the binary states of the (n) memory cells (E₁, E₂, ... , E_n) of the second value register W_i-1 and the bit (M_i) associated to the first value register W_i of the marking register (7) are inverted according to a further uninterruptible execution process.

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