CZ286328B6 - Value card with binary value units - Google Patents

Abstract

The invented value card with binary value units has a first number N of arranged value registers (Wi1, Wi2, WiN), whereby the value register (Wi1, Wi2, WiN) has a second number n of memory cells (Ei1, Ei2, ... Ein) from which each is for one binary unlosable value unit and n number of memory cells (Ei1, Ei2, ... Ein) of the value register (Wi1, Wi2, WiN) is together adjustable to at least one first value. The value card is further provided with a marking register (7) having a third number of M memory cells (Mi2, MiN) for the binary unlosable values, wherein the third number M is by one less than the first number N. A memory cell (Mi) of the marking register (7) being assigned to the value register (Wi) that is in turn superior to another value register (Wi-1). The value card is further provided with a means for simultaneous storage of the first value into both n memory cells (Ei1, Ei2 ...., Ein) of the value register (Wi-1) that is in turn inferior to the value register (Wi) and into the memory cell (Mi) of said marking register (7) that is assigned to the value register (Wi).

Description

Value card with binary value units

Technical field

The invention relates to a value card with binary value units. A value card with binary value units having a first number of ordered value registers, the value register having a second number of memory cells, each of which is for one binary lost value unit, and the value register memory cells are collectively adjustable for at least one first value.

BACKGROUND OF THE INVENTION

Such value cards are preferably used in vending machines for a variety of services - for example, in payphones, where the value cards conform, for example, to ISO 7816.

A value card of this kind is known from EP 0 519 847 A1 and has binary value units stored in a number p in arranged registers. One register has a certain number of n equal value units whose quality depends on the class of the register. The total value of one register is as large as the individual value unit of a register that is immediately superior to that register. When transferring the total value of a register to the value unit of the register immediately superior to that register, several known steps need to be performed with known storage techniques, which must be performed perfectly in order to maintain the value value of the value card. In order to be able to recognize imperfect transmission, the known value card additionally has p -1 marker registers, each with a capacity of n bits, each bit of the parent register being assigned one bit of the marker register. The transmission of the total value of a register to the value unit of a register that is superior to that register is marked in the bit assigned to the value unit of the parent register for the duration of the transmission sequence. If the value card has p * n bits to display its value, additional (p-1) * n bits are required to mark.

It is an object of the invention to provide a value card whose value is reliably changeable.

SUMMARY OF THE INVENTION

This object is achieved by a value card with binary value units having a first number of ordered value registers, the value register having a second number of memory cells, each of which is for one binary lost value unit and the value register memory cells collectively adjustable for at least one first The value card according to the invention, characterized in that the value card further has a marker register having a third number of memory cells for binary lost values, wherein the third number is one less than the first number. A value register that is superior to another value register is assigned a marker cell memory cell. The value card is further provided with means for simultaneously storing the first value in the memory cells of the value register, which is subordinate to the value register, and in the memory cell of the marker register, which is assigned to the value register.

-1 CZ 286328 B6

Overview of the drawings

Examples of embodiments of the invention will be explained below with reference to the drawings, in which the figures show:

Giant. 1: block diagram of part of the value card,

Fig. 2: registration block and tag register of the value card memory module,

Fig. 3: Registration block and marker register before and after the correction cycle

Fig. 4: variant of using a registration block,

Fig.5: variant of application before and after the correction cycle.

DETAILED DESCRIPTION OF THE INVENTION

The value card (FIG. 1) has a memory module 1 and an access module 2 which is connected by the signal line 3 to the memory module 1. The signal lines 3 comprise data and control lines through which the information module 2 can read and / or change information, The access module preferably has one input 4 and one output 5, wherein the input 4 together with the output 5 can also be implemented as a bi-directional data channel. The access module 2 is preferably provided with a microprocessor.

The memory module 1 comprises a registration block 6 and a marker register 7. The registration block 6 has a first number of N value registers W _x to W _n , each containing a second number n of memory cells E 1 to En each for one binary lost value unit. In the example shown, the first number N is equal to three and the second number n is equal to eight. The first number N and the second number n are essentially natural numbers which are adaptable to the purpose of the value card. Generally, the second number n for the value register W1 and W2 is respectively. W? or. Wn is freely selectable, wherein in the example shown, the second number n for each value register to Wn of the registration block 6 is equally large.

A quantity storable in one memory cell E _{to the} i-th value register W; it is dependent on the valid value unit of the memory cell Ej <and on the binary value, respectively. the logical state of the memory cell E ^. Preferably, the value unit of the memory cell Ek is a value register W; depending on the degree of the value register W, in the valid order of the registration block 6. In the preferably dimensioned registration block 6, the value registers W1 to Wn are arranged in such a way that for index i from 2 to N the value register Wj is superior to the value register Wjj or that for index i from 2 to N, the value register Wu is subordinate to the value register Wf

The quantity herein includes a binary value and a value unit, wherein the value unit has a numeric value, expressing a unit of measure, or has the meaning assigned to that numerical value. Examples of value units include 8 kWh, 16 tax pulses, 10 francs and 64 m.

Preferably, the maximum storable variable in one value register W1 is as large as the value unit of a single memory cell of the value register W1, immediately superior to the value register W1.

If the value unit of the memory cell Er is a value register W, in one example eight rate pulses and if n = 8, then when the memory cell has a logical state of 1, the quantity stored in the memory cell Ek can be interpreted as 8 rate pulses a, when the memory cell has a logical state of 0, the quantity stored in the memory cell Ek can be interpreted as zero rate pulses. Furthermore, for example, the maximum storable quantity in the value register W ^ is preferably set at 8 rate pulses, while the maximum storable quantity in the value register W; it is preferably 64 rate pulses.

-2GB 286328 B6

The memory technology of the memory module 1 is selected so as not to lose the current state or the binary value of the memory cell Ei, respectively. E? or. E ^ of the registration block 6 in the event of a power failure or disconnection of the memory module 1, as well as not to lose the current state or binary value of the memory cells M? or. The memory module 1 is, for example, an EEPROM (electrically erasable programmable read only memory) or an EAPROM (electrically alterable programmable read only memory).

During the process of reading the value units on the value card, it is necessary to transfer the maximum storable quantity in the memory register to one bit of the value register Wj + i, which is immediately superior to the value register Wj. when it is necessary to exceed the maximum storable quantity in the value register Wj.

Fig. 2a shows in the second value register W? the quantity G, which is represented by n memory cells Ei to E ^ set to logic 1, is stored.

Hereinafter, the process by which the variable G is moved in a favorable manner in two actions to be performed successively to the value register Wn, immediately superior to the second value register W?, Will be described, starting from having at least one of memory cells Ε _χ to E _{n of the} parent value register Wn, and also a memory cell Mn of the marker register associated with the parent value register Wn, a logical value of 0.

In the first operation, the binary state of the memory cell E4 of the parent value register Wn is inverted. which shows a logic value of 0, and the bit Mn of the marker register 7 associated with the parent value register Wn is transformed in one uninterruptible execution step, or logic 1 is inserted therein. 2b shows the registration block 6 and the marker register 7 after the first operation, wherein the memory cells changed during the first operation are shaded.

In the second operation, the binary states of the memory cells E1 to En of the value register W1, which exhibit the quantity G, are transformed and the bit Mn of the marker register 7, which is assigned to the value register Wn, is changed. in the next uninterruptible execution step, or logic 0 is deployed. 2c shows the registration block 6 and the marker register 7 after the second operation, wherein the memory cells changed during the second operation are shown shaded.

The described procedure is useful for moving another quantity G from the first value register W] to a value register W ₂ which is superior to the value register W], the first operation inverting the binary state of the memory cell E _{r of the} higher value register W ₂ value 0, and bit Mj of the marker register 7, which is assigned to the parent value register W ₂ , is changed. in one uninterruptible execution step, or both logic 1 is deployed, and in the second operation, the binary states of the memory cells E ₂ to E of the "value register W" having the value G are reversed and bit M? The marking register 7, which is assigned to the value register W ₂ , the superior value register W 1, in a further uninterruptible execution step, optionally logic 0 is deployed. 2d shows the registration block 6 and the marker register 7 after the first operation to move the variable G, while FIG. 2e shows the registration block 6 and the marker register 7 after the second operation, the memory cells changed in both operations are shown in shaded.

The memory module 1 and the access module 2 are arranged such that the value register W, the associated memory cell Mi of the register register 7, together with the memory cell Er of the value register W; they are adjustable to the first binary value and that the register Wj is assigned

The memory cell Mi of the marker register 7 together with the memory cells E to Ej of the value register Wh, subordinate to the value register Wj, is adjustable to an inverse value of the first binary value.

If the procedure to move the variable G or the input is deliberately interrupted. G 'on the value card between the first and the second operation, so that the incomplete transfer is later recognizable by evaluating the marker register 7 and thus also correctable, whereby the transfer can be performed absolutely reliably.

Giant. 3a shows the memory module 1 in a state in which the Nth bit Mn of the marker register 7 shows a logical value of 1, in which case the bit indicates that the transfer was incomplete. This state can occur, for example, when a value card having a memory module 1, whether intentionally or unintentionally, is pulled out of the reader at the moment when the variable G is to be moved. In this state, the move is terminated by a correction cycle to be performed. . The correction cycle involves inverting n memory cells Ei to value register Wn-i associated with nth bit Mn of marker register 7, while also nth bit Mn of the marker register is reset to logic 0. Fig. 3b shows the state of the memory module 1 after the correction cycle.

The test sequence for recognizing an incomplete movement with a conditional correction cycle on a value card can be described in a pseudocode, similar to the Pascal programming language, as follows:

for i = 2 to N to begin if M [i] -1 then W [i-1] = 0 {clear register Wh} end.

The test sequence is preferably performed after inserting the value card into the reader, preferably the test sequence is performed by the value card processor.

Since the value card has a marker register 7, which makes the transfer of the G or the values of the G-value incomplete. G 'recognizable and correctable in the test sequence, it is possible to omit the machine conveyor and expensive locking systems from the reader because, by pulling the value card in operating condition, neither advantages nor disadvantages for the value card value are achievable for the user.

The memory module 1 is preferably programmable via input 4, i.e. the value stored on the value card can be changed via input 4, preferably at least one card status information at output 5 being, for example, empty or blank. non-empty.

Said method for moving a quantity represented by a binary value unit is advantageously applicable in reliable methods of adding or reading value units on a value card. The procedure is simply transferable to the corresponding variants in the negative logic and / or to delete the value units on the value card. It goes without saying that an incomplete transfer in the registration block 6 can be marked in one bit of the marking register 7 either as shown in FIG. 3, logic 1, or logic 0.

During the process of deleting the value units of the value card, it is necessary to forcefully transfer the quantities which can be stored in one bit of the value register Wj. to a value register Wh immediately subordinate to a value register Wj. when the child value register Wh is empty.

-4GB 286328 B6

In one variation of the use of the memory module 1 shown in Fig. 4, the incomplete transmission in the registration block 6 is marked in the register 7 by the logical 0. The state of the register 7 shown in Fig. 4a in which all bits are set to logical 1. therefore, there is no incomplete move in the registration block 6. In one bit of the Nth value register Wn it is possible to store a certain quantity G.

Hereinafter, the procedure for transferring the variable G in two successive operations to the value register W _N- i, which is immediately subordinate to the N th value register Wn, will be described, assuming that the memory cells have E] to Ε "subordinate value register Wnj. logical value 0.

In the first operation, the binary state of the memory cell E _{4 of the} N-th value register Wn having a value of logic 1 and the bit register Mn 7 assigned to the value register Wn are inverted in one uninterruptible execution step or logic 0 is set. 4b shows the registration block 6 and the marker register 7 after the first operation, wherein the memory cells that have changed during the first operation are shown in shaded form.

In the second operation, the memory registers Ej to En of the value register and the bit Mn of the marker register 7 associated with the value register Wn to the higher value register Wn are converted in the next uninterruptible execution step, or logic 1 is set. 4c shows the registration block 6 and the marker register 7 after the second operation, wherein the memory cells changed during the second operation are shown shaded.

Giant. 5a shows the memory module 1 in a state in which the Nth bit Mn of the marker register 7 has a logical value of 0, whereby the bit in this case indicates that an incomplete transfer has been performed. This state can occur, for example, when a value card having a memory module 1, whether intentionally or unintentionally, is pulled out of the reader at the moment when the quantity G is to be moved. The move can be terminated in this state by a correction cycle. The correction cycle involves inverting n memory cells Εχ to Ej, a value register Wn ^ i, which is immediately subordinate to a value register Wn, which is assigned to the nth bit Mn of the marker register 7. At the same time as inverting n memory cells E | aEj, the value register W1 is also put back on the Nth bit Mn of the marker register to logic 1. FIG. 3b shows the state of the memory module 1 after the correction cycle.

If a value card has N * n memory cells to represent its value, then additional memory cells of N - 1 are required to indicate the move.

By having the register register 7 for each value register W? to Wn, superior to another value register W W to Wnj, with only a single bit, a relatively large saving of E memory cells can be achieved by a preferred method over the prior art, which can be calculated with the first number N and second number n using the formula:

E = η * (N-1) - (N-1) = (N-1) * (η-1) [Fl]

It can be clearly seen in formula F1 that the saving E is greatest for N = n. The saving E is the memory space necessary for a reliable change of the value stored on the value card relatively small relative to the memory space available in the registration block 6 for storing values.

Claims (1)

A value card with binary value units having a first number of N arranged value registers (W _b W ₂ , W _N ), wherein the value register (W); W ₂ ; W _N ) has a second number of n memory cells (E _b E ₂ , ..., E _n ), each of which is for one binary lost value unit an of memory cells (E _t , E ₂ , ..., E _n ) the value register (Wi; W ₂ ; Wn) is collectively adjustable to at least one first value, characterized in that the value card further has a marker register (7) having a third number of M memory cells (M ₂ , Mn) for a binary non-lost value, wherein the third number M is one less than the first number N and a value register (W m) that is superior to the next value register (W m) is assigned a memory cell (M 1) of the marker register (7), is provided with means for simultaneously storing the first value in n memory cells (Ei, E ₂ , ..., E _n ) of the value register (W _h |), which is subordinate to the value register (Wj), and in the memory cell (Mj) ) of the marker register (7) which it assigns n value register (Wj).