CN107358974A - Multiple independent serial link memories - Google Patents

Multiple independent serial link memories Download PDF

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Publication number
CN107358974A
CN107358974A CN201710560551.7A CN201710560551A CN107358974A CN 107358974 A CN107358974 A CN 107358974A CN 201710560551 A CN201710560551 A CN 201710560551A CN 107358974 A CN107358974 A CN 107358974A
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China
Prior art keywords
data
memory
serial
memory bank
address
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CN201710560551.7A
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Chinese (zh)
Inventor
金镇祺
潘弘柏
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Examine Vincent Zhi Cai Management Co
Mosaid Technologies Inc
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Examine Vincent Zhi Cai Management Co
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Priority claimed from US11/324,023 external-priority patent/US7652922B2/en
Application filed by Examine Vincent Zhi Cai Management Co filed Critical Examine Vincent Zhi Cai Management Co
Publication of CN107358974A publication Critical patent/CN107358974A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch

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  • Information Transfer Systems (AREA)
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Abstract

The present invention discloses a kind of devices, systems, and methods for being used in semiconductor memory control data transmission between serial data link interfaces and memory bank.In one embodiment, the invention discloses a kind of flash memory with multiple serial data links and multiple memory banks, wherein, the link is independently of the multiple body.The flash memory can be cascaded with daisy chain configuration, and echo-signal line serial communication is used between memory devices.In addition, the present invention describes a kind of virtual multi-link configuration, wherein fetching simulation multi-link using single chain.

Description

Multiple independent serial link memories
The application is Application No. 200680036462.2, the applying date to be September in 2006 29, be entitled " multiple The divisional application of the application of independent serial link memory ".
Technical field
The present invention relates to semiconductor memory devices, more particularly it relates to which a kind of be used for improving semiconductor flicker The speed of memory devices and/or the memory construction of capacity.
Background technology
The mobile electricity of such as digital camera, portable digital-assistant, portable audio/video player and mobile terminal Sub- equipment requires mass storage all the time, preferably has and is continuously increased capacity and the non-volatile of speed ability is deposited Reservoir.For example, the audio player used at present can have between 256M bytes to 40G bytes be used for store audio/regard The memory of frequency evidence.Because nonvolatile memory can preserve data in the event of a power failure, prioritizing selection is such as The nonvolatile memory of flash memory and hard disk drive, therefore extend battery life.
At present, hard disk drive has the high density that can store 20-40G byte datas, but volume is relatively bulky.But Flash memory, also referred to as solid-state drive, due to its high density, non-volatile and relative hard disk drive it is smaller Size and receive an acclaim.Flash memory technology is based on EPROM and EEPROM technology.It is due to it to select term " flicker " The a large amount of memory cells of one time erasable, this is different from the EEPROM that can only individually wipe each byte.Multilevel-cell (MLC) Occur further increasing flash memory density relative to single layer cell.Those skilled in that art know clearly that flicker is deposited Reservoir can be configured as or non-(NOR) flashes or flashed with non-(NAND), wherein, NAND flickers are due to its closer storage Device array structure and relatively given area has more high density.In order to discussed further, the mentioned flash memory arrived can be with It is understood to NOR, NAND or other type flash memorys.
Although existing flashing memory module for current consumer-elcetronics devices there is enough speed to run, use May and it be insufficient in the other equipment for require high data rate.For example, the more matchmakers of movement of record high-resolution mobile image Body equipment, which may require memory module, has at least 10MB/s programming handling capacity, and existing flash memory technology is difficult to reach Arrive, because the typical programming data rate of existing flash memory technology is 7MB/s.The multi-step programming needed due to programming unit Sequence, multilevel-cell flash memory have 1.5MB/s lower speed.
By increasing the running frequency of flash memory, it can directly increase the programming of flash memory and reading is handled up Amount.For example, about 20-30MHz running frequency can be increased an order of magnitude to about 200MHz at present.Although this solution Certainly scheme seems simple and direct, but signal quality has prominent question under so high frequency, and this is just to flash memory Running frequency be provided with limitation in practical application.Especially, flash memory uses one group of parallel input/output (I/O) pin communicates with other elements, according to it is expected configure, the pin number be 8 or 16, for receive command instruction, Receive input data and output data is provided.This is commonly referred to as parallel interface.High-speed cruising will cause well-known all As crosstalk, signal skew and signal attenuation communication degrading effect, so as to reduce signal quality.
Above-mentioned parallel interface reads and write data using a large amount of pins.With the increase of input pin and circuit, permitted More undesirable effect is also increasing.These effects include intersymbol interference, signal skew and crosstalk.Intersymbol interference comes from edge The decay of the signal of line transmission and the reflection caused when multiple element is connected to circuit (reflection).Work as signal Along the line transmission with different length and/or characteristic and when different time reaches end points, signal skew is produced.Crosstalk Refer to the undesirable coupling of the signal on very close circuit.With the speed of service increase of memory devices, crosstalk Increasingly become a problem.
Therefore, need such memory module should for mobile electronic device and solid-state drive in the art In, it has increased memory capacity and/or the speed of service, and minimizes the input pin needed for access memory module With the quantity of circuit.
The content of the invention
Illustrate being briefly summarized for some embodiments of the present invention below, for providing recognizing substantially to many aspects of the present invention Know.This summary is not the detailed general overview of the present invention, and it is not intended to be mark crucial or important portion of the invention Point, nor defining the scope of the present invention.Its sole purpose is to provide some embodiments of the present invention in simplified form, as under The preamble described in more detail stated.
According to many aspects of the present invention, the invention discloses with multiple memory banks and multiple serial data link interfaces Semiconductor memory devices.In one embodiment, memory devices are included between independent control link interface and memory bank Data transfer control circuit.In some instances, the memory bank is nonvolatile memory.The control circuit of the present invention Can be with the multiple modules and other circuit communications in memory devices.For example, the control circuit generation driving is multiple described The control signal of module.
Invention also discloses the method that concurrent storage operation is carried out in semiconductor flash memory.It further comprises For each serial data link interfaces and the positioning indicator of memory bank.When the memory bank is busy (or returning ready) When, and when link interface busy (or returning ready), update these positioning indicators.In addition, virtual multi-link feature Allow with the memory devices for reducing pin number to be run higher than the handling capacity of equipment in the prior art.
According to many aspects of the present invention, the invention discloses a kind of memory system with multiple cascaded memory devices System.The memory devices can be connected in series, and external memory controller can receive and provide data and control Signal gives the accumulator system.In other embodiments of the invention, for realizing the executable instruction quilt of disclosed method It is stored as computer-readable instruction of the control logic either on the computer readable medium of such as CD or disk.In the present invention Some embodiments in, each flash memory can include a unique device identifier.It can configure described Equipment is used for parsing target device information domain in serial input data, by the described unique of target device information and the equipment Equipment identification number is associated, to judge whether the equipment is the target device.This specification also discloses that this hair Other bright multiple aspects.
Brief description of the drawings
The present invention is illustrated by exemplary embodiment, but the present invention is not limited to respective drawings, wherein identical accompanying drawing mark Number represent the same part.
Figure 1A, 1B, 1C are the height for the example memory device for illustrating permission concurrent operations according to many aspects of the present invention Level schematic diagram；
Fig. 2A is the high level block diagram according to the example memory device of many aspects of the present invention；
Fig. 2 B are the schematic diagram of the serial data link according to Fig. 2A of one embodiment of the present of invention；
Fig. 2 C are incoming serial the showing to parallel block of registers according to Fig. 2A of one embodiment of the present of invention It is intended to；
Fig. 2 D are the schematic diagram of the path switching circuit according to Fig. 2A of one embodiment of the present of invention；
Fig. 2 E are the signal of the parallel-to-serial block of registers of output according to Fig. 2A of one embodiment of the present of invention Figure；
Fig. 3 A, Fig. 4, Fig. 5 A, Fig. 6 A and Fig. 7 are the memory performed by memory devices according to many aspects of the present invention The timing diagram of operation；Fig. 3 B, Fig. 5 B and Fig. 6 B are to illustrate Fig. 3 A, 5A and 6A respectively in the equipment according to many aspects of the present invention The flow chart of the storage operation；
Fig. 8 A, 8B and 8C be the concurrent storage operation that is performed in memory devices according to many aspects of the present invention when Sequence figure；
Fig. 9 and Figure 10 be according to the multiple serial data link interfaces of control of many aspects of the present invention and multiple memory banks it Between data transfer method flow chart；
Figure 11 is that the output pin of memory devices in the equipment according to many aspects of the present invention configures block diagram；
Figure 12 is being performed in the memory devices of many aspects equipped with virtual multi-link feature according to the present invention The timing diagram of storage operation；
Figure 13 describes the high level block diagram of the cascade configuration of multiple memory devices according to many aspects of the present invention；
Figure 14 is the storage operation performed on the memory devices in the cascade configuration according to some aspects of the present invention Simplified timing diagram.
Embodiment
The invention discloses the serial data interface of the semiconductor memory with least two memory banks.This serial data Interface can include one or more serial data link to be communicated with central control logic, wherein, each serial data Link can serially provide output data with serial received order and data.Each serial data link can access Any memory bank in reservoir is used for programming and reading data.At least one advantage of serial line interface is that have under different densities Standard output pin and the few equipment of number of pins, therefore, it is allowed to be mutually compatibly upgraded to more high density without setting again in the future Count circuit board.
Figure 1A and 1B be according to many aspects of the present invention illustrate support concurrent operations example memory device it is advanced Schematic diagram.Figure 1A shows the memory with multiple serial data link interfaces 102 and 104 and multiple memory banks 106 and 108 Equipment.Arrangement shown here is referred to as dual-port and configured.There is each serial data link interfaces the input/output being connected to draw Pin and data input and data output circuit, and will be described in further detail with reference to Fig. 2A.Pass through serial data link interfaces The data of transmission in a serial fashion transmit by (such as data flow with individual bit width), each in the memory devices Data Link Interface 102 and 104 is all independent, can transmit any one in data discrepancy memory bank 106 and 108.For example, Serial data link 102 can transmit data discrepancy memory bank 106 or 108.Similarly, serial data link 104 can pass Transmission of data discrepancy memory bank 106 and 108.Because shown dual serial Data Link Interface is independent, so they can be simultaneously The single memory bank of transmission data discrepancy of hair." link " described herein refers to circuit, and the circuit can be that data come in and go out One or more of memory banks provide path, and control its transmission.Control module 110 can be configured using order, with Control data exchanges between each serial data link interfaces 102 and 104 and each memory bank 106 and 108.For example, Control module 110 can be configured as allowing serial data link interfaces 102 to read the data from memory bank 106, permit simultaneously Perhaps serial data link interfaces 104 are write data in memory bank 108.This feature enhance the flexibility of system design and raising Utilization rate of equipment and installations (for example, bus utilization and core utilization rate).As follows, control module 110 can include control electricity Road, register and on-off circuit.
Figure 1B shows one embodiment, wherein, single serial data link interfaces 120 are linked to by control module 126 Multiple memory banks 122 and 124.Arrangement shown here is referred to here as single port configuration, and relative to the dual-port shown in Figure 1A Configuration, uses the input/output pin of less memory devices.Configuration control module 126 runs or performed two behaviour Make process or thread so that serial data link interfaces 120 can exchange number in a pipeline fashion with memory bank 122 and 124 According to.For example, when data are written into memory bank 122, Data Link Interface 120 can read the data of memory bank 124 simultaneously.Root According to many aspects and described in further detail of the present invention, memory devices use the singular link configuration mould shown in Figure 1B Multi-link operation is intended.Configured using this singular link combination multibank, be referred to as virtual multi-link herein, can be at other Memory bank accesses any available memory bank when being likely to be at busy condition.Therefore, by connecting arbitration circuit, to access other available Memory bank, this memory devices can lift the utilization rate of singular link configuration.
Memory devices shown in Figure 1A and Figure 1B include two memory banks being for illustration purposes only.Technology in the art Personnel can be appreciated that many aspects of invention disclosed herein can scale, and allow using multiple memory banks and Multiple serial data link interfaces.For example, single memory equipment can include such as 2,4 or multiple memory banks.Fig. 1 C show Go out one embodiment, wherein, under the control of control module 150, be configured with four independent serial data links 132,134, 136 and 138, for exchanging data with four memory banks 140,142,144 and 146.Configured when using virtual multi-link, only one It is individual link be it is necessary, remaining link (such as the double-strand in Figure 1A connect or Fig. 1 C in four link output pins configuration) simultaneously Without using, and be considered as not connect (NC).Compared to traditional parallel interface structure, serial data link interfaces at least one Individual advantage, it is exactly while link flexibility and big density is kept, reduces the pin number on memory devices.For example, When there is 48 pins on multiple faces that traditional flash memory may be required in encapsulation, according to the memory of the present invention Equipment can use seldom pin (for example, 11 pins) on the one side of standard packaging 1100, as shown in figure 11.Or It is, due to needing less inner bondpad, it is possible to use different, smaller types encapsulation.
According to the specific embodiment of the present invention, memory devices shown in Fig. 2A exemplary illustrations Figure 1A it is more detailed Schematic diagram.The structure of each memory bank in memory devices 200 can be the same as or similar to NAND flash memorys Core texture.Fig. 2A shows these circuits related to the present invention, and purposefully eliminates some circuit blocks and carry out simplification figure 2A, for example, will include circuit for producing high voltage using the memory devices 200 of Flash memory core structure, this circuit is to storage The programmed and erased of unit is necessary.Core texture (or core circuit) used herein refers to include memory cell array With the circuit of associated access circuit (such as decoding and data transmission circuit).Because standard memory structure is well-known , therefore the primitive operation associated with selected structure is also known, this point those skilled in that art should Solution.Those skilled in the art are more it should be appreciated that any of non-volatile or volatile memory structures can be used in In the alternate embodiment of the present invention.
Memory devices 200 include multiple same memory banks with respective data, control and addressing circuit, such as deposit Body A 202 and memory bank B 204 is stored up, address and data path switching circuit 206 are connected to memory bank 202 and 204, and connect It is used to provide to on-off circuit 206 and receive from switch to the same interface circuit 205 and 207 associated with each memory bank The data of circuit 206.For example, memory bank 202 and 204 is preferably nonvolatile memory, such as flash memory.Logic On, the signal for being received and being provided by memory bank 202 is marked by alphabetical " A ", while the signal quilt for being received and being provided by memory bank 204 It is marked with alphabetical " B ".Similarly, the signal for being received and being provided by interface circuit 205 is labeled with numbers " 0 ", is connect by interface circuit 207 The signal received and provided is labeled with numbers " 1 ".Each interface circuit 205/207 receives access data with serial data stream, wherein For example, the access data can include order, address information and the input data for programming operation.In read operation, Interface circuit will be responsive to reading order and address date provides output data as serial data stream.Memory devices 200 enter One step includes global circuit (global circuit), such as control interface 208 and state/ID register circuits 210, for carrying For such as clock signal sclki and reset circuit and respective interface of the overall signal to both memory banks 202 and 204 Circuit 205 and 207.Aforementioned circuit will be discussed further below.
Memory bank 202 includes known memory peripheral circuit, such as providing output data DOUT_A and for connecing Receive input programming data DIN_A induction amplifier and page buffer circuit block 212, also row decoding block 214.Skill in the art Art personnel will be it will be appreciated that block 212 will also include column decoding.Control and predecode circuit block 216 are via signal wire ADDR_A Address signal and control signal are received, and pre-decoded address signal is provided and delayed to row decoder 214, induction amplifier and the page Rush circuit block 212.
The peripheral circuit of memory bank 204 is identical with the peripheral circuit of previously described memory bank 202.Memory bank B circuit Including the induction amplifier and page buffer electricity for providing output data DOUT_B and for receiving input programming data DIN_B Road block 218, also row decoding block 220 and control and predecode circuit block 222.Control and predecode circuit block 222 are via letter Number line ADDR_B receives address signal and control signal, and provides pre-decoded address signal to row decoder 220, sensing amplification Device and page buffer circuit block 222.Each memory bank and corresponding peripheral circuit can use known structure to configure.
In general operation, each memory bank is to specific order and address response, and if necessary, to inputting number According to response.For example, memory bank 202 will provide output data DOUT_A in response to reading order and reading address, and can ring Answer program command and program address and input data is programmed.For example, each memory bank can respond such as erasing order Other orders.
In presently shown embodiment, path switch 206 is two-port circuit, can be in one of both of which Operation is used for transmitting signal between memory bank 202 and 204 and interface circuit 205 and 207.The first is direct transmission mode, Wherein, the signal of memory bank 202 and interface circuit 205 transmits mutually.Meanwhile in the directly transmission mode, memory bank 204 Transmitted mutually with the signal of interface circuit 207.Second is Cross transfer (cross-transfer) pattern, wherein, memory bank 202 and the signal of interface circuit 207 transmit mutually, meanwhile, the signal of memory bank 204 and interface circuit 205 transmits mutually.Later The single port that path switch 206 is discussed is configured.
As mentioned above, interface circuit 205 and 207 is received and provided data in a manner of serial data stream, this be in order to While total signal throughput is improved under high running frequency, the demand of the output pin of chip is reduced.Due to the He of memory bank 202 204 circuit is typically configured as being used for parallel address and data, so needing change-over circuit.
Interface circuit 205 includes serial data link 230, and incoming serial to parallel register block 232 and output are arrived parallel Serial register block 234.Serial data link 230, which receives serial input data SIP0, input enable signal IPE0 and output, to be made Energy signal OPE0, and SOD serial output data SOP0, the enabled echo-signal IPEQ0 of input and the enabled echo-signal of output are provided OPEQ0.Signal SIP0 (and SIP1) is serial data stream, wherein, each signal can include address, order and input data. Serial data link 230 provides the serial input data SER_IN0 corresponding to SIP0 buffering and received parallel from output To the SOD serial output data SER_OUT0 of serial register block 234.Incoming serial receives SER_IN0 to parallel register block 232 And it is converted into one group of parallel signal PAR_IN0.Export parallel-to-serial block of registers 234 and receive one group of parallel output number According to PAR_OUT0 and SOD serial output data SER_OUT0 is converted into, it is thereafter provided as data flow SOP0.Output Parallel-to-serial block of registers 234 can also receive the data from state/ID register circuits 210, wherein be deposited for exporting The data of storage, rather than PAR_OUT0 data.The details of this special characteristic will be further described then.In addition, serial number The cascade of another offer control signal of memory devices 200 and the daisy chain of data-signal is provided according to link 230.
Serial interface circuit 207 configures identically with interface circuit 205, and including serial data link 236, input string Row is to parallel register block 240 and exports parallel-to-serial block of registers 238.Serial data link 236 receives serial input number According to SIP1, input enable signal IPE1 and output enable signal OPE1, and provide SOD serial output data SOP1, input enable back The ripple signal IPEQ1 and enabled echo-signal OPEQ1 of output.The offer of serial data link 236 is corresponding to the serial of SIP1 buffering Input data SER_IN1, and receive from the SOD serial output data SER_OUT1 for exporting parallel-to-serial block of registers 238. Incoming serial receives SER_IN1 to parallel register block 238 and is converted into one group of parallel signal PAR_IN1.Output is simultaneously Row receives one group of parallel output data PAR_OUT1 to serial register block 240 and is converted into SOD serial output data SER_ OUT1, it is thereafter provided as data flow SOP1.Export parallel-to-serial block of registers 240 can also receive from state/ The data of ID register circuits 210, for exporting the data wherein stored, rather than PAR_OUT1 data.Such as serial number According to as link 230, serial data link 236 is configured as another memory devices 200 and provides control signal and data-signal Daisy chain cascade.
Control interface 208 includes standard input buffer circuit, and produces and correspond respectively to CS#, SCLK and RST# Inside chip selection signal chip_sel, internal clock signal sclki and internal reset signal reset.Although signal chip_ Sel mainly by serial data link 230 and 236 use, but reset and sclki by memory devices 200 by many circuits Use.
Fig. 2 B are the schematic diagram according to the serial data link 230 of one embodiment of the present of invention.Serial data link 230 Including the input buffer 242 for receiving input signal OPE0, IPE0 and SIP0, for drive signal SOP0, IPEQ0 and OPEQ0 output driver 244, the flip-flop circuit 246 for exporting (clocking) signal out_en0 and in_en0 by bat And phase inverter 248 and multiplexer (MUX) 250.Response signal chip_sel carrys out enabling signal OPE0 and SIP0 input Buffer, respond the anti-phase chip_sel enabling signals SOP0 of inverted device 248 output driver.Signal out_en0 starts Output buffer (being shown in subsequent figures 2E) and provide signal SER_OUT0.Signal in_en0 starts incoming serial to posting parallel Storage block 232 latches SER_IN0 data.Signal in_en0, out_enO and SER INO.
Serial data link 230 includes the daisy chain that startup cascades memory devices 200 and other memory devices Circuit.More specifically, input serial data stream SIP0 and enable signal OPE0 and IPE0 can be passed by serial data link 230 It is delivered to the respective pins of another memory devices.When high logical levels of the in_en0 in activation, SER_IN0 by and gate 252 receive and are delivered to corresponding trigger 246.At the same time, the in_en0 of the high logical level in activation will control MUX 250 transmit Si_next0 to output driver 244.Similarly, IPE0 and OPE0 can also pass through the respective quilt of trigger 246 IPEQ0 and OPEQ0 are output to by bat.Although it is described herein as serial data link 230, it should be clear that serial data link 236 Including similar elements, they are connected with each other according to the identical mode of serial data link 230 shown in Fig. 2 B.
Fig. 2 C are schematic diagram of the incoming serial to parallel register block 232.This block of registers reception clock signal sclki, Enable signal in_en0 and input traffic SER_IN0, and SER_IN0 is changed as one group of parallel data.Especially, Ke Yizhuan SER_IN0 is changed to provide order CMD_0, column address C_ADD0, row address R_ADD0 and input data DATA_IN0.It is of the invention public The embodiment opened preferably is run in high frequency, such as in 200MHz.With this speed, input serial data stream can solve in fast cross Received under the speed for the order that code is received.Just because of this reason, input serial data stream is initially buffered in one group of deposit In device.It should be understood that the schematic diagram shown in the present invention is also applied for incoming serial to parallel register block 240, unique difference Place is that the label of signal name is different.
Incoming serial includes input controller 254, command register 256, temporary register to parallel register block 232 258 and serial data register 260, wherein, input controller 254 is used for receiving in_en0 and sclki.Due to serial input number Data structure according to stream is predetermined, it is possible to which the input traffic of particular number of bits is assigned to foregoing register In.For example, can be stored in command register 256 with the corresponding position of order, position corresponding with row address and column address can To be stored in temporary register 258, position corresponding with input data can be stored in serial data register 260. The bit allocation of input serial data stream can be controlled by input controller 254, and it can include counter, for receiving often Suitable register is produced after one predetermined digit and starts control signal.In other words, each of three registers By sequence starting serial input number can be received and store with predetermined data structure according to input serial data stream According to the data bit of stream.
Command interpreter (interpreter) 262 receives the command signal from command register 256 parallel, and produces A raw order CMD_0 by decoding.Command interpreter 262 is the standard of the gate or firmware realization by interconnecting Circuit, for decoding the order received.As shown in figure 4, CMD_0 can include signal cmd_status and cmd_id.Switch Controller 264 receives one or more signal from CMD_0, for controlling a simple on-off circuit 266.Switch electricity Road 266 concurrently receives all data being stored in temporary register 258, and is added according to the order CMD_0 by decoding Data are carried to one or both of column address register 268 and row/body register 270.Due to temporary register not always Including both columns and rows/body address dates, it is advantageous to progress this decoding.For example, with the serial defeated of block erasing order Enter data flow and will use only row address, in this situation, the corresponding positions being only stored in temporary register 258 are loaded into row/body Register 270.Column address register 268 provides parallel signal C_ADD0, and row/body address register 270 provides parallel signal R_ ADD0, and data register 272 provides parallel signal DATA_IN0, for programming operation.CMD_0, C_ADD0, R_ADD0 and Data_IN0 (optional) is collectively forming parallel signal PAR_IN0.The bit wide of each parallel signal is not yet designated, because required Width is a kind of design parameter, can customize or design according to specific criteria.
Example for the certain operations for the memory devices 200 for flashing core texture realization is as shown in table 1 below.Table 1 arranges Go out possible operation (OP) code for CMD_0 and column address (C_ADD0), row/body address (R_ADD0) and input data (DATA_IN0) corresponding state.
The command set of table 1
In addition, table 2 shows the preferable list entries of input traffic.Order, address and serial mode are movable into and out Memory devices 200, since highest significant position.Command sequence is started (in table 2 with the command code of a byte " cmd "), according to the order, column address byte (" ca " in table 2), OK can be followed after the command code of a byte Address byte (" ra " in table 2), body address byte (" ba " in table 2), data byte (" data " in table 2), it is combined Or equal nothing.
The list entries of the byte mode of table 2
Fig. 2 D are the schematic diagram of the path switch 206 shown in Fig. 2A.Switch 206, which is logically divided into two, has identical match somebody with somebody The switch sub-circuit 274 and 276 put.Switch sub-circuit 274 includes four input multiplexers 278, biography that can be selective Pass order, address and the circuit for inputting data into memory bank 202 of interface circuit 205 or interface circuit 207.For example, these Signal had previously been combined to as PAR_IN0 in such as Fig. 2 C.Switch sub-circuit 274 includes an output multiplexer 280, for optionally transmitting the output data from memory bank 202 or memory bank 204 to interface circuit 205.Switch Circuit 276 includes four input multiplexer (not shown)s, delivering interface circuit 205 or interface circuit that can be selective 207 order, address and the circuit for inputting data into memory bank 204.Switch sub-circuit 276 includes an output multiplexer (not shown), for optionally transmitting the output data from memory bank 202 or memory bank 204 to interface circuit 207.
According to switch controlling signal SW_CONT state, switch both sub-circuits 274 and 276 can passed directly simultaneously Run in defeated pattern or Cross transfer pattern.Path switching circuit 206 is currently shown to be configured for dual-port, it is meant that by connecing Mouth circuit 205 or 207 can access memory bank 202 and 204 simultaneously.
According to another embodiment of the present invention, as described in preceding Figure 1B, path switch 206 can be transported in single-port mode OK, wherein, interface circuit 205 and 207 only has an activation.It is defeated due to no longer needing to be connected with untapped interface circuit Enter/o pads, this configuration can further reduce the output pin area needed for memory devices 200.Match somebody with somebody in single port In putting, in addition to each output multiplexer 280 that can be kept in response to SW_CONT selection signals, sub-circuit is switched 274 and 276 are arranged to only run in direct transmission mode.
In a single port embodiment, wherein, only interface circuit 205 activates, and is inputting parallel-to-serial block of registers 232 (or blocks 234) include secondary path switch (not shown), are posted for optionally transmitting switch 266 and serial data Corresponding column and row/body and data register of the output data of storage 260 to incoming serial to parallel register block 232 or 240 Device.In fact, this secondary path switch can be identical with switch 206.Therefore, incoming serial is to parallel register block 232 and 240 Column and row/the body and data register of the two can be loaded data, access for alternate memory banks or substantially concurrently deposit Take.
Fig. 2 E are the schematic diagram for exporting parallel-to-serial block of registers 234.It will be noted that export parallel-to-serial deposit Device block 238 and same configuration.Export parallel-to-serial block of registers 234 and the data accessed from memory block, Huo Zheti are provided For prestoring status data in a register.More particularly, user or system can ask serial data link 230 or 236 state.The value of designated bit places (for example, the 4th) is that " 1 " can indicate specific serial in the status data exported Data Link Interface is busy.The data of the fixation may further include chip identification data, its can together with status data, Preloaded when memory devices 200 power up with default conditions.Status data can be configured with any to be known by system Other pre-selection bit pattern.Although it is not shown, Fig. 2 E can include additional control circuit, for based on one or more Preparatory condition, update one or more position being stored in register 284.For example, based on the counting for using the clock cycle, or The combination of one or more marking signal of the person based on the different circuit blocks reception from memory devices 200, thus it is possible to vary one Individual or multiple mode bits.
It is parallel-to-serial including the first parallel-to-serial register 282 and second to export parallel-to-serial block of registers 234 Register 284, the first parallel-to-serial register 282 are used to receive the output data PAR_OUT0 from path switch 206, the Two parallel-to-serial registers 284 are used to receive the fixed data from multiplexer 286.Response signal cmd_id, multichannel Converter 286 optionally transmits the status data being stored in status register 288 or is stored in ID registers 290 One of chip identification data.Respond the cmd_id or cmd_status of the activation through OR gate 294, output multiplexer The data of data or second parallel-to-serial register 284 of 292 transmission from the first parallel-to-serial register 282.Most Afterwards, SER_OUT0 is provided by the Serial output control circuit 296 of out-en0 startups.
According to various aspects of the invention, those skilled in that art can be appreciated that the chi that can change positioning indicator Very little and position.(such as stored for example, serial data link interfaces positioning indicator can combine other kinds of positioning indicator Body positioning indicator) and/or it is physically located at the outer of block of registers (such as in link arbitration modules or control module 238) Side.In another embodiment, serial data link interfaces positioning indicator is a bit register.
Fig. 3 A, Fig. 4, Fig. 5 A, Fig. 6 A and Fig. 7 are according to performed by memory devices 200 the one of many aspects of the present invention The exemplary timing chart of a little storage operations.Some memory commands performed by memory devices 200 include but is not limited to：Page Face reading, random data reading, the page reading for duplication, the destination address input for duplication, serial date transfer, with Machine data input, page program, block erasing, reading state, read ID, write configuration register, write device name entry, reset and/ Or bank selection.Timing diagram discussed below by the specific embodiment with reference to the memory devices 200 shown in prior figures and Table 1 and table 2.
In the example that Fig. 3 A timing diagram describes, according to the present invention, " page reading " memory command 314 is in memory Received at the serial data link 230 of equipment 200.Further, Fig. 3 B show in Fig. 3 A timing diagram that " page reading " stores The simplified flowchart of the parallel work-flow of device order 314.As practical problem, the step shown in Fig. 3 B will combine Fig. 3 A timing diagram Discuss.By this example, in step 324, at the serial data link 230 of memory devices 200 read " page reading " and deposit Reservoir order 314.
In this instance, the data flow of input is 6 byte serial data flows (that is, serial input data), including order data (the 1st byte), column address data (the 2nd, 3 bytes) and row and body address date (the 4th, 5,6 bytes).Body address can be used for true It is fixed to access memory bank 202 or 204 through path switch 206.Those skilled in that art are appreciated that different memory commands There can be different data flows.For example, " random data reading " memory command has the data flow of default only 3 bytes： Order data (the 1st byte) and column address data (the 2nd, 3 bytes).In latter example, the address field of serial input data is only Comprising column address data and it is 2 byte longs.Meanwhile in prior example, address field is 5 byte longs.Technology people in the art After member is it is to be appreciated that seen entire disclosure, according to many aspects of the present invention, many memory commands and default number It is obvious according to stream.
The example about " page reading " memory command shown in Fig. 3 A is gone on to say, when chip selects (CS#) signal 302 Low level is set as, and response input port enables (IPEx) signal 306 and is set as high level, serial input (SIPx) port 308 it is sampled that (wherein, ' x ' is a placeholder, represents chain at first rising edge of serial clock (SCLK) signal 304 Connection interface number, for example, 1 interface 234 of 0 interface 232 of link or link).Data read-out (step 328) is one and " page reading Take " the corresponding data flow of memory command.CS# signals 302 are an input signals of memory devices 200, except can be with Outside in other respects, it can also be used to indicate whether memory devices 200 activate (for example, when CS# is low level). IPEx signals 306 indicate whether input traffic will be received (for example, when IPEx is high level) at specific link interface, Or whether specific link interface will ignore input traffic (for example, when IPEx is low level).Input traffic is storing Received at the SIPx308 of the link interface of device equipment.Finally, system clock (SCLK) signal 304 is memory devices 200 One input signal, and it is used to the various operations that synchronous multiple circuits by memory devices 200 perform.For this area Interior technical staff it is evident that according to the memory devices of many aspects of the present invention can with this clock signal (for example, operation and Rising edge and/or trailing edge in clock signal occurs for data transfer) synchronous or asynchronous (that is, asynchronous).Either, double During haplotype data speed (DDR) is realized, the rising edge and trailing edge of SCLK clock signals may serve to latch information.But In Fig. 3 A example, input data is latched in SCLK trailing edge, and after SCLK rising edge, output data 322 is Appear on serial output pin 312SOPx.
As shown in Figure 3A, " page reading " state can check on SOPx pins 312, therefore, will be provided on SOPx The result of " memory bank is busy ", when there is " ready " instruction at time point 318, and it will go out soon during the time 322 Existing output data.It should be noted that although Fig. 3 A illustrate " page reading " with subsequent " reading state ", but can also basis One aspect of the invention is susceptible to " page reading " for not having " reading state ".In this embodiment, will not be on SOPx pins Data are provided, untill output data is ready.
The order data of SIPx samplings is written to the suitable register (for example, command register 256) shown in Fig. 2 C.If It is order data to count first character section in input traffic, and selecting at least one benefit of such design input data stream is, institute Command register can be transferred to without additional step by stating data.According to the type of memory command, in data flow Subsequent byte can be address date and/or input data.Those skilled in that art are appreciated that according to the multiple of the present invention Aspect, the memory command collection that memory devices can identify can be by the width based on word (that is, 16) or any I/O width Defined.In figure 3 a, the address date followed by five bytes of order data (that is, 00h represents " page reading " 314)：Two Byte column address data and three byte lines/body address date.Address date is written in the address register 258 shown in Fig. 2 C. Address date is used to position the data stored in the memory bank 202 that will be read.During selection is read data herein, make With the column decoder in predecoder circuits 216, row decoder 214 and circuit 212.For example, pre decoder module 214 is used for Pre-decoded address information.Then, the column decoder in row decoder 214 and circuit 212 is used to activate corresponding to address date Bit line and wordline.In the example of " page reading " order, corresponding to a wordline, multiple bit lines are activated.Then, it is stored in Data in memory bank 202 are transferred in the page register in circuit 212 after the sensing of sensed amplifier.In Fig. 3 A Before shown time point 318, the data in page register possibly can not be used, i.e., output pin SOPx will be shown " busy ". It is referred to as transmission time (t with the total amount of timeR).Transmission time periods terminate at time point 318 (Fig. 3 A), and continue one tRCycle.
Before transmission time periods terminate, memory bank status displays be set to show specific memory bank (for example, Memory bank 202) it is " busy ".Exemplary memory body positioning indicator in Fig. 3 A is the domain of a byte, using in these positions One (for example, the 4th) indicate memory bank 202 (that is, memory bank 0) be " busy " or " ready ".Memory bank state instruction Device is stored in Fig. 2 E status register 288.After memory bank is identified by input traffic, memory bank state instruction is updated Device (for example, the 4th is set to ' 0 ').Once storage operation is completed, renewal memory bank positioning indicator is (for example, the 4th is set to ' 1 ') memory bank no longer " busy " (that is, " ready ") is indicated.It should be noted that memory bank positioning indicator and SOPx output pins The two will indicate " busy " state together, will be described in detail below.Scheming although those skilled in that art should be aware that Memory bank positioning indicator is described as 1 byte field in 3A, but its size is not necessarily to so limit.Bigger positioning indicator It is that can monitor the state of more memory banks with least one benefit.In addition, positioning indicator can be other for monitoring (for example, after such as storage operation of " page program " is performed, memory bank is in " passing through " or " failure " shape to the state of type State).In addition, for those skilled in that art it will be evident that the positioning indicator used in this each represent different storages The state of body is given for example only.For example, the combined value of position may also be used for indicating the state of memory bank (for example, by using patrolling Collect door or other circuits).The operation of " reading state " corresponding with memory bank positioning indicator order will be below in conjunction with Fig. 7 Discuss.
" reading state " memory command 316 is used to read the memory bank positioning indicator (step 328) in Fig. 3 examples. Sometimes during transmission time, " reading state " order 316 is sent to the command register of block of registers 224." read shape State " order indicates memory devices 200 to monitor the state of memory bank 202, so as to determine when complete from memory bank 202 to page The data transfer of face register 216.By data path control module 230 from control module 238 or directly by data path Control module 230 sends " reading state " order." once reading state " order is issued (for example, being sent to command interpreter 228 and/or control module 238), output port enables (OPEx) signal 310 and driven as high level, and passes through Serial output (SOPx) port 312 exports the content of memory bank positioning indicator.It is similar with IPEx signals 306, when being set to high level, OPEx signals 310 start serial output port buffer (for example, data output register).Time point 318 in figure 3 a, Positioning indicator data instruction memory bank 202 in SOPx is changed into (step 330) " ready " state from " busy " state.By In the content for no longer needing positioning indicator, OPEx signals 310 return to low level.
Then in figure 3 a, IPEx signals are set as high level, and do not follow " page reading " of address date to order 320 are possibly retransmission (step 332) to the command register in block of registers 224, for being provided data to from data register Output pin SOPx.Then, OPEx signals are set as high level (and IPEx returns to low level), and page register 216 Content be transferred to SOPx 312.Output data (the step 334) provided is left memory and set by link interface 230 Standby 200.Error correction circuit (not shown) can check output data and show read error if detecting a mistake.This Art personnel understand that the monitoring of state and the establishment again of page read command can be automatically performed by system.Fig. 3 A are only It is the example operated according to the memory devices of many aspects of the present invention, and the invention is not restricted to this.For example, according to this The many aspects of invention are contemplated that other memory commands and timing diagram.
For example, illustrate the simplified timing diagram of " random data reading " order after " page reading " order in Fig. 4." with Machine digital independent " order starts one or more row ground after " page reading " order or " random data reading " order The reading of excessive data at location.The data stream packets of " random data reading " order 402 contain three bytes：Order data (first Byte) and column address data (second and the 3rd byte).By the data read are selected in " page reading " order Same a line, so not needing row address data.Normally " the random data reading sent afterwards is completed in " page reading " order Take " order some data 404 for causing current page (page read during i.e. relatively early order) to be output.Due to corresponding to depositing The data stored up in the page register of the circuit 212 of body 202 have been present, at least one advantage of " random data reading " order It is to improve the efficiency from preselected pages output data.
Reference picture 5A, illustrate the timing diagram of " page program " order.Because Fig. 2A embodiments illustrated have used serial number According to inputting and exporting link structure, so before starting to page program, it is necessary to programming data is loaded into memory bank first In page register, it uses " serial date transfer order " to complete." serial date transfer " order 502 adds including serial data During load, the data of up to one page (for example, 2,2112 bytes) are loaded into the page buffer in circuit 212 during this period. After the completion of the step of loading data register, " page starts " order 504 is sent so that the data from memory bank register to be passed It is defeated to arrive appropriate memory bank.Once sending order 504, internal write state machine performs appropriate algorithm and control sequential programs And verification operation.Therefore, two steps are divided into according to one embodiment of the invention, " page starts " order：Serial date transfer and test Card.When successfully completing " page program " order, memory bank positioning indicator will provide " passing through " (opposite is " failure ") As a result come show one successfully operation.In other respects, the timing diagram of Fig. 5 A example and step are similar with shown in Fig. 3 A, It had been previously described in more detail.
In addition, Fig. 5 B show the simplified flowchart of the parallel work-flow of " page program " order in Fig. 5 A timing diagram.Step In rapid 506, " serial date transfer " order 502 is input into serial input port (SIP) line.SIP lines are input in this Data flow be multibyte serial data stream (that is, serial input data), started (in the first byte) with order data.Then, Column address data (second, third byte of serial data stream) and row/body address date (the four, the 5th and of serial data stream 6th byte), all it is transfused to (step 508) and arrives SIP lines.In the subsequent byte of serial data stream, input data is transfused to (step 510) arrives SIP lines.In step 512, " programming starts " order 504 is sent.Then, it is the state of monitoring operation, " will reads Take state " order and write SIP line (steps 514).This causes memory devices to monitor the state of memory bank status register Position.Once mode bit shows the ready (step 516) of memory bank, and memory bank instruction " passing through " (step 518), then " page is compiled Journey " memory command has been successfully executed.
In addition, according to many aspects of the present invention, " page for being used to replicate is read " and " destination address for being used to replicate is defeated Enter " other operations of the memory command performed by memory devices." if the page for being used to replicate is read " order is written to The command register of serial link interface, then the internal source address (3 byte) of memory location be written into.Once input source Location, the content of the memory bank of memory devices transmission particular source is to data register.Then, " with being used for the target of duplication Location input " memory command (carrying 3 byte bodies/row address sequence) is used to specify the target storage for page copy operation Device address.It is then possible to " page program " order is utilized to make inner control logic with automatically writing page data to target Location." reading state " order then can be used for confirming the successful execution of order.According to full content disclosed herein, for this In field for technical staff, other storage operations are obvious.
Reference picture 6A, for illustrating " to wipe " timing diagram of (or " block erasing ") order.In addition, Fig. 6 B show Fig. 6 A when The simplified flowchart of the parallel work-flow of " erasing " order in sequence figure.Those skilled in that art can be appreciated that erasing typically Occur in block one-level.For example, flash memory 200 each memory bank has 2048 erasable piece, each piece according to The page tissue of 64 2112 (2048+64) bytes.Each piece is 132K bytes (128K+4K bytes).Erasing order is once grasped Make a block.By the way that (that is, the order data of ' 60h ') corresponding order data 602 will be ordered with " erasing " in step 610, with And the row of three bytes and body address are write into command register through SIPx in step 612, start block erasing operation.Complete order After being inputted with address, internal erase status machine automatically carries out suitable algorithm and controls all necessary sequential to wipe And verification operation.It will be noted that can be by writing or programming a logical value " 1 " to each storage in memory block Unit, perform " erasing " operation.In order to monitor erase status determine when tBERS(that is, block clashes the time) completes, in step 614, which can send " reading state ", orders 604 (for example, order datas corresponding to 70h).After " reading state " order, institute Some reading circulations will come from memory bank status register, until providing a newer command.In this example, memory bank state is posted The appropriate position (for example, position 4) of storage reflects the state (for example, busy or ready) of corresponding memory bank.When memory bank exists When step 618 is changed into ready, the appropriate position (for example, position 0) of memory bank status register is checked in step 620, with described in decision Erasing operation has passed through in step 622 or have failed in step 624.In certain aspects, the timing diagram of Fig. 6 A example and Step is similar with shown in Fig. 3 A, is being previously described in more detail.
Reference picture 7, memory bank positioning indicator is read using " reading state " memory command.In addition, when at 702 When sending " reading state " order (that is, ' 70h ') to command register 256 in Fig. 2 C, memory devices 200 are instructed to supervise Depending on the state of memory bank 202, when decision is successfully completed from memory bank 202 to the data of the page buffer in circuit 212 Transmission, and other side." once reading state " order is issued (for example, being sent to command interpreter 262), output port Enabled (OPEx) signal is driven as high level, and the content of memory bank positioning indicator passes through Serial output at 704 (SOPx) port exports.When OPEx signals are set to high level, startup serial output port buffer (such as data output deposit Device).In addition, in the example of figure 7, memory bank positioning indicator is the domain of a byte (i.e. 8), and each is used to refer to deposit Storage body (such as memory bank 202) be in operation that " busy " still perform on " ready " and/or memory bank, and (such as " erasing " orders Make) it is " passing through " or " failure ", and other aspects.Although those skilled in that art can be appreciated that what is described in Fig. 7 Memory bank positioning indicator is the domain of a byte, but its size does not want limited to this.Bigger positioning indicator has extremely A few benefit is can to monitor the state of more memory banks.In addition, for those skilled in that art it will be evident that although this In example the positioning indicator that uses each represent the state of different bank, but the invention is not restricted to this.For example, the combination of position Value may also be used for indicating the state (for example, using gate and other circuits) of memory bank.
Fig. 8 A, 8B and 8C are to be performed simultaneously using double independent serial datas link 230 and 236 according to many aspects of the present invention Send out the timing diagram of the memory devices of operation.According to many aspects of the present invention, some performed by memory devices are concurrently grasped Work includes but is not limited to：Concurrently reading, concurrency programming, concurrently wipe, program when read, erasing when read and erasing when program. Concurrent " page reading " operation performed on Fig. 8 exemplary illustration memory bank A (memory bank 202) and memory bank B (204).Fig. 8 A In, memory bank A is expressed as " memory bank 0 ", while memory bank B is expressed as " memory bank 1 ".Fig. 8 B.Reading public affairs whole here After opening content, other concurrent operations are obvious for those skilled in that art.
Reference picture 8A, carry out concurrent " page reading " for the different bank in memory devices 200 and operate 802 Hes 804.In the memory devices 200 with Double Data link interface 230 and 236, " page reading " order 804 passes through Data-Link Connection interface 236 (linking 1) is sent, and " page reading " order 802 is pending by Data Link Interface 230 (linking 0) simultaneously. Although Fig. 8 A show to start before " page reading " of " page reading " on memory bank 1 on memory bank 0, two " pages Face reading " operation can substantially simultaneously start, concurrent operations.Output data 806 from each " page reading " order, 808 are sent simultaneously by their own Data Link Interface.Therefore, each data link in memory devices 200 connects Mouth can access any memory bank and independent operation.At least one advantage of this feature is exactly with fabulous in system design Flexibility and utilization rate of equipment and installations raising (for example, bus utilization and core utilization rate).
The path of output data in Fig. 8 A from memory bank to Data Link Interface is identical with Fig. 3 A discussed before.Come from The path switch 206 that the output data of memory bank 204 is controlled by body address for example flows to defeated from S/A and page buffer 218 Go out parallel-to-serial block of registers 240 and to serial data link interfaces 236 (that is, link 1).Respectively in memory bank 202 and 204 The data transfer carried out simultaneously between serial data link interfaces 230 and 236 will independently occur each other.Due to body address 206 can be switched with control path, serial data link interfaces 236 are readily modified as accessing memory bank 202.In memory devices 200 The quantity of Data Link Interface be not limited to the pin of memory devices 200 or the quantity of port.In memory devices 200 The quantity of link interface is also not necessarily limited to the quantity of the memory bank in memory devices.For example, each Data Link Interface can be with Operate single inlet flow and/or single output stream.
In addition, according to various aspects of the invention, Fig. 8 B illustrate the difference storage for memory devices 200 The timing diagram that " page reading " order 810 and " page program " order 812 that body is carried out are executing concurrently.In this instance, pass through Serial data link interfaces 230 perform read operation in one of multiple memory banks (for example, memory bank 202), and (" page is read Take " 810), meanwhile, by another (for example, the memory bank 204) of serial data link interfaces 236 in multiple memory banks Perform write operation (" page program " 812).According to various aspects of the invention, each links of memory devices 200 can be with Access any memory bank and independent operating.
Fig. 8 C are performed for the memory devices 200 with dual serial Data Link Interface and two memory banks and concurrently stored The timing diagram of device operation.First, " erasing " order 814 to memory bank 0 (memory bank 202) links 0 (serial number by serial line interface 230) sent according to link.It is being busy with handling " erasing " life linking 0 (serial data link 230) and memory bank 0 (memory bank 202) When making 814, " page program " order is received at memory devices, and is turned to using 1 (serial data link of link 236).Therefore, " page program " order 816 on memory bank 0 (memory bank 202) by (serial data of serial data link interfaces 1 236) link performs, meanwhile, read command 818 is on memory bank 1 (memory bank 204) by (serial data link of serial data interface 0 230) perform.During memory command 814, (deposited in serial data link interfaces 0 (serial data link 230) and memory bank 0 Storage body 202) between transmit data；During memory command 818, in same link interface 0 (serial data link 230) and deposit Data are transmitted between storage body 1 (memory bank 204).Therefore, according to many aspects of the present invention, each chain in memory devices 200 Connecing can be with any memory bank of independent access (that is, not busy memory bank).
For those skilled in that art it is apparent that after reading full content disclosed herein, Fig. 8 A, 8B and 8C only show Go out some embodiments of the concurrent storage operation according to present inventive concept.The example of other concurrent operations includes but unlimited In：Erasing and/or concurrency programming when programming, programming when concurrently reading, wiping when reading, erasing when erasing, programming.In the art Technical staff can be appreciated that the order of step in flow chart is not construed as being only limited to specific order.For example, read It can be sent with program command in the case of with and without read status command.
According to many aspects of the present invention, Fig. 9 shows two between multiple serial link interfaces and multiple memory banks simultaneously Send out the description more summarized of write operation.Fig. 9 shows to write number through serial data link interfaces according to one embodiment of present invention According to the method to memory bank.First, in step 902, data flow is received in serial data link interfaces.Data flow includes will be by Order, address and the data of storage in a register.Then, in step 904, renewal and the first serial data link interfaces phase The serial data link interfaces positioning indicator answered, it is used to refer to the first serial data link interfaces and is currently being used.Step 904 Including changing the place value in status register.The specific interface of update instruction in step 904 is being used.In step 906, Analyze data stream extracts the first memory bank identifier.Memory bank identifier uniquely indicates the memory bank in memory devices. Memory bank identifier can be included in address field or other domains of data flow.Then, deposited in analyze data stream to extract After storing up body identifier, in step 908, corresponding memory bank positioning indicator is updated.For example, can by control signal come Driving occurs in step 904 and 908 renewal, wherein, control signal is produced by the control circuit in state/ID registers 210. To put it more simply, these control signals are omitted from timing diagram.Finally, in step 910, in the first serial data link and first Data are sent between memory bank.It will be noted that in this is broadly described, because data are written to the deposit of the memory bank page first Device, memory bank is then programmed into immediately, so step 910 has been simplified.
Meanwhile with the operation of step 902 concomitantly, by different serial data link interfaces on different memory banks Perform another data writing operation.In other words, sent using between the second serial data link interfaces and the second memory bank The second data flow concurrently perform second memory operation.First, in step 912, in multiple serial data link interfaces Second data flow of interface second.Alleged serial data link interfaces are all same storages in step 912 and 902 A part for device equipment.In step 914, renewal refers to corresponding to the serial data link interfaces state of the second Data Link Interface Show device, be used to refer to the second serial data link interfaces and be being used.Then, in step 916, the second data flow is analyzed to carry Take the second memory bank identifier.In step 918, renewal corresponds to the memory bank positioning indicator of the second memory bank indicator, It is used to refer to the second memory bank to be being used, and in step 920, through the related page register to the second memory bank, Data are sent between the second serial data link interfaces and the second memory bank, as foregoing relevant " page program " orders that Sample.In Fig. 9, once data transfer occurs, i.e. serial data link interfaces receive all data that write specified memory bank, phase Should in the serial data link interfaces indicator of each serial data link interfaces will be reset be used to refer to peer link work as Before can use, and memory bank indicator will keep busy until all related datas are programmed, and hereafter, memory bank indicator will indicate Associated memory bank has become available.
Figure 10 include with 902 to 910 in Fig. 9 shown in data write-in concomitantly reads data from memory bank in step when can be with The illustrative steps of execution (are expressed as step 1010).Can during concurrent storage operation in Figure 10 exemplary descriptions completion Fig. 7 To perform the example of some steps.First, in step 1002, from wherein second reception of multiple serial data link interfaces Read the request of the data stored in the second memory bank.In step 1004, renewal is corresponding with the second Data Link Interface to go here and there Row Data Link Interface positioning indicator, it is used to refer to the second serial data link interfaces and is being used.In step 1006, more The new memory bank positioning indicator for corresponding to the second memory bank identifier, is used to refer to the second memory bank and is being used.Finally exist In step 1008, data are sent between the second serial data link interfaces and the second memory bank.One shown in Figure 10 or The multiple steps of person can be executing concurrently.
Figure 1B is returned to, shown memory devices configure including the use of the individual data link interface 120 of virtual multi-link.Profit Figure 1B can be realized with the configuration of foregoing incoming serial to parallel register 232.More generally useful, memory devices can be used 200 realize Figure 1B embodiment, but there was only one in dual serial data link and used.In ventional flash memory, I/O pins are occupied, until operation is completed.Therefore, operation is not had to be established in device busy condition, it reduces device Availability and reduce overall performance.In example described in Figure 1B, initialized in one of two memory banks After operation, the available memory bank of any quilt " reading state " operation inspection can be accessed.Then, memory devices can make Available memory bank is accessed by additional switch circuit with serial data link.Therefore, according to this aspect of the invention, may be used To access multiple memory banks using single link.This virtual multi-link configuration simulates multi-link using singular link and operated.
Figure 12 is to use the execution " page program " in memory bank 0 and the virtual of " page reading " is performed in memory bank 1 The timing diagram of the memory devices execution storage operation with two memory banks of multi-link configuration.First, sent out to memory bank 0 Go out " page program " order 1202." page program " order is above having been described in, but briefly repeats here, first Perform " serial date transfer " order and the data for preparing to be programmed into memory bank 0 are loaded into memory bank page zero register.With Afterwards, " page program " order is sent, data are written to memory bank 0 from page register.Ordered when sending " reading state " When 1204, equipment indicates 1206 memory banks 1 " ready " (and memory bank 0 is in " busy ").Then, based on according to the present invention's Virtual multi-link configuration, when memory bank 0 be in busy condition, for memory bank 1 " page reading " order 1208 can with and It has been issued.Had been described above before " page reading " order." reading state " order 1210 can be sent (and such as Figure 12 institutes Show) determine the state of memory bank.The result of " reading state " order shows in interim 1212, memory bank 0 and memory bank 1 The two is all ready.Finally, sending " page reading " ordered for 1214 (being used for memory bank 1) caused corresponding to " the page reading of memory bank 1 Taking " content of storage address of order exports on serial output pin (SOP).It will be noted that when " page on memory bank 0 When face programming " operation occurs, serial data interface link pin SIP, which can be used for receiving, indicates " reading for memory bank 1 " ready " State " is ordered.In the same manner, once " page reading " order on memory bank 1 is initialised, SIP pins are again to " reading shape State " order is available, shows that both memory bank 0 and memory bank 1 are all ready.As a result, single serial data interface link can be used To access and check the state of two memory banks.The many aspects for the virtual multi-link feature realized in Figure 12 illustrate Even if previous storage operation does not terminate, the link is still available.At least one benefit of this feature is due to virtual multichain Number of pins caused by configuration is connect to reduce.Another benefit is to improve the performance of memory devices.
In addition, when many aspects of virtual multi-link feature are with double or four link configurations memory devices realizations When, it may be desirable that the all-links in addition to one links are all in unactivated state.For example, four in four link configurations (Fig. 1 C) Three of individual link can be not used and can be appointed as being not connected with (NC).At least advantage of this realization is to deposit The reduction of pin number on storage device, while also maintain link flexibility and availability.
According to many aspects of the present invention, Figure 13 exemplary descriptions are used for the chrysanthemum for being connected in series multiple memory devices 200 Pattern chain cascade configuration 1300.Especially, equipment 0 includes multiple data-in ports (SIP0, SIP1), multiple data-out ports (SOP0, SOP1), multiple control input ports (IPE0, IPE1) and multiple control output end mouths (OPE0, OPE1).These data With control signal memory devices 1300 are sent to from external source (for example, Memory Controller (not shown)).In addition, according to this Invention, the second flash memory (equipment 1) can include the same type of port such as equipment 0.Equipment 1 can be with equipment 0 serial connection.For example, equipment 1 can receive data and control signal from equipment 0.In addition to equipment 0 and equipment 1, one Individual or multiple optional equipments can also the same manner serial connection.After predetermined delay, in cascade configuration most Equipment (for example, equipment 3) afterwards provides data and control signal returns to Memory Controller.Each (example of memory devices 200 Such as, equipment 0,1,2 and 3) export IPE0, IPE1, OPE0 and OPE1 (that is, control output end mouth) echo-signal (IPEQ0, IPEQ1, OPEQ0 and OPEQ1) arrive subsequent equipment.How examples of circuits in earlier figures 2B can be from one if describing signal The equipment that equipment is delivered to subsequent daisy chain link.In addition, single clock signal can depositing for transmission to multiple serial connections Each in storage device.
In foregoing cascade configuration, the equipment operation of cascaded memory devices 1300 and the memory devices 200 not cascaded It is identical.Those skilled in that art understand, in cascade configuration, the total delay time of memory devices 1300 may increase Add.For example, Figure 14 describes highly simplified timing diagram, the timing diagram be used for it is being received at memory devices 1300, for operation " page reading " order 1402 of the memory bank of equipment 2 in memory devices 1300.Memory command is in memory devices Received at 1300 and equipment 2 is sent to by equipment 0 and equipment 1.For example, the data corresponding to " page reading " order 1402 Stream by by the SIP0 circuits of the equipment 0 from memory devices 1300 by the circuit of equipment 0 equipment 0 SOP0 circuit outputs. It is reflected in the simplified timing diagram of the output of equipment 0 in fig. 14 at 1404 on SOPx_D0 outlet lines." SOPx_DO " phase Similarly, it should be received in the serial output port 0 of equipment 0 at the SIPx_D1 of data flow then on the device 1 (at 1406) And sent by equipment 1,1408 on SOPx_D1 circuits at export.Then, data flow in equipment 2 SIPx_D2 1410 Place receives.In this example, because " page reading " order is pointed at the memory bank of equipment 2, with it is electric in memory devices 200 The similar mode of road description, the circuit in equipment 2 receive " page readings " order and control asked data from device 2 Transmission at middle memory bank on SOPx_D2 outlet lines in equipment 2 1412.The data that equipment 2 exports are connect 1414 by equipment 3 Receive, and transmitted by equipment 3, exported from memory devices 1300.Those skilled in the art can be from Figure 14 simplification sequential Figure is recognized, due to predetermined four clock cycle delays caused by cascade configuration.
Meanwhile cascade configuration allows in fact not limited number equipment connection, the handling capacity without sacrificing equipment.The present invention Some aspects have an advantage that realize multi-chip package solution and solid-state large-capacity storage application.In cascade device 1300 Input traffic it is similar with non-cascaded memory devices 200.But one can be provided with before the first byte of data flow The device identifier of byte.For example, the value " 0000 " in the first byte be able to can be indicated with instruction equipment 0, same to duration " 0001 " Equipment 1.Once those skilled in that art recognize that device identifier is not necessarily so limited a byte, it is possible to according to will Ask reduction or increase.Equally, device identifier is also not necessarily to the first byte being defined in data flow.For example, it can increase Add the size of identifier to be used for accommodating more equipment in cascade configuration, and put together with the address field of data flow.
According to one embodiment of present invention, memory devices 200 use the chip of 4Gb monolithic integrated circuit, In another embodiment, memory devices are using the chips of a pair of stackings to reach 8Gb.In another embodiment, memory devices 1300 using 4 stacked chips to realize 16Gb.According to the flash memory of many aspects of the present invention can be used for it is all The improved solution that Large Copacity non-volatile memories such as the storage of solid-state file and other non-volatile portable applications of expectation are applied Certainly scheme.Bigger autgmentability and flexibility are provided for the system integration due to not limiting the connection equipment of quantity substantially, is stored Device equipment 1300 can benefit from new scintillator device concatenated schemes.Serial line interface is by with higher clock rate, preferably letter Number integrated and lower power consumption provides additional performance boost.Serial line interface also provides infinite number of expansible I/O width, and Package arrangements need not be changed.In addition, according to the one-side pad architecture of the memory devices of the present invention, there is less I/O quantity, Greatly reduce chip package size.
Table 3 below shows the example of the certain operations of the cascaded memory devices for flashing core texture realization.Table 3 is listed Destination device address (TDA), possible operation (OP) code and the corresponding state of column address, row/body address and input data.
The command set of table 3
In some embodiments of the invention, each equipment in Figure 13 system 1300 can hold one and uniquely set Standby identifier, may be used as the destination device address (tda) in serial input data.When receiving serial input data, flash Memory devices can analyze the target device address field in serial input data, and by by destination device address and equipment Unique equipment identification number be associated, so as to which whether decision device be target device.
Table 4 shows the preferable list entries of input traffic according to an embodiment of the invention, including is retouched with reference to Figure 13 The system stated.Order, address and serial mode move into, remove memory devices 1500,
Since highest is effectively.It is high level when input port enables (IPE), serial input signals (SP) are in serial clock (SCLK) it is sampled at rising edge.Command sequence is with the destination device address (tda) of a byte and the operation of a byte Code starts, and the command code is also referred to as command code (" cmd " in table 4) by interchangeable.By by serial input signals with The destination device address of one byte of highest significant position can handle any additional input received as starting, equipment Target device address field is analyzed before data.If memory devices are not target devices, it can transmit string before treatment Row inputs data into another equipment, therefore saves additional processing time and resource.
List entries in the byte mode of table 4
One byte tda is moved into equipment, is followed by a byte cmd code.Highest significant position (MSB) is opened on SIP Begin, and each is locked in the rising edge of serial clock (SCLK).Dependent on the order, after a byte command code Column address byte, row address byte, body address byte, data byte and/or its combination or equal nothing can be followed.
As it was previously stated, memory devices can be double storage body memories, wherein, each memory bank can be by any serial chain Connect access.The serial line interface of memory devices not only drastically increases data throughout compared to Traditional parallel interface scheme, And support the operation rich in feature.For example, programming operation can perform in 200 μ s on the page of (2k+64) byte, and And erasing operation can perform in 1.5ms on the block of (128k+4k) byte.Writing controller can be used for being automatically brought into operation on piece All programmed and erased functions, including used pulse cycle, internal verification and data define.Write in height intensive (write-intensive) in system, it is used for improving 100,000 in memory devices using the error correcting code (ECC) of real-time mark algorithm The extension reliability in secondary program/erase cycle.
The serviceability of many aspects of the present invention is obvious for those skilled in that art.It is any herein or all real Example or exemplary language (for example, " such as ") are only used for better illustrating the present invention rather than limiting the scope of the invention System, unless there are other statement.Language in specification should not be considered as illustrating any content being not claimed to hair Bright implementation is required.
Although the present invention is often to be described according to preferable and exemplary embodiment, by browsing public affairs of the invention Content is opened, the other embodiment, modification and variation in the scope and spirit of claims are for those skilled in that art For be contemplated that.

Claims (16)

1. flashing the method for memory block in a kind of access NAND flash memories, methods described includes：
In one reception data flow of any of which of multiple interfaces, the data flow includes order data, address date and writes number According to；
It is determined that the flicker memory block with the data stream association；And
The flicker memory block is accessed from any of which one of the multiple interface.
2. according to the method for claim 1, wherein determining to include decoding institute with the flicker memory block of the data stream association The order data in data flow and address date are stated to determine the flicker memory block with the data stream association.
3. according to the method for claim 1, wherein receiving any of which that the data flow is included in the multiple interface The data flow of one reception individual bit width.
4. according to the method for claim 2, wherein decoding order data in the data flow and address date includes point It is at least one in command component and column address part, row address part or body address part to determine to analyse the data flow.
5. the method according to claim 11, in addition to：
Another data flow is received in any of which one of multiple interfaces；
The second order data in another data flow and address date are decoded to determine and another data stream association Second flicker memory block；And
The second flicker memory block is accessed while the flicker memory block is operated.
6. according to the method for claim 1, in addition to transmission goes into or from the data of the flicker memory block.
7. according to the method for claim 1, be additionally included in the flicker memory block it is just accessed when by status register more New is busy condition.
8. a kind of NAND flash memories, including：
Multiple interfaces, each interface, which is configured as receiving, includes order data, address date and the data flow for writing data；
Control module, for being determined and the data stream association in response to the information in the order data and address date NAND flashes memory block, and for being passed between any of which one of the multiple interface and NAND flicker memory blocks Defeated write data.
9. NAND flash memories according to claim 8, wherein in the multiple interface each also by with It is set to reading data of the transmission from NAND flicker memory blocks.
10. NAND flash memories according to claim 8, wherein the data flow is the number of individual bit width According to stream.
11. NAND flash memories according to claim 8, wherein the address date includes block address, and The control module determines the NAND flickers memory block in response to the block address.
12. NAND flash memories according to claim 8, wherein each in the multiple interface includes using In the command interpreter for decoding the order data.
13. NAND flash memories according to claim 9, wherein each in the multiple interface is configured For reading data of the transmission from NAND flicker memory blocks when the order data corresponds to page read operation.
14. NAND flash memories according to claim 13, wherein the reading from NAND flicker memory blocks Data are concurrently provided, and each in the multiple interface includes parallel-to-serial circuit, for by described in Read data and be converted to serial data from parallel data.
15. NAND flash memories according to claim 8, in addition to serial-to-parallel circuit, for by described in Write data and be converted to parallel fo from series form.
16. NAND flash memories according to claim 8, in addition to status register, it is configured as in institute State when NAND flicker memory blocks are just accessed and indicate busy condition.
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