CN111522759A

CN111522759A - Device and method for converting multi-path synchronous serial data bus into parallel data bus

Info

Publication number: CN111522759A
Application number: CN202010300663.0A
Authority: CN
Inventors: 张宝利; 李尧; 刘丛林; 庞岩; 许新骥
Original assignee: Shandong Zhiyan Exploration Technology Co ltd
Current assignee: Shandong Zhiyan Exploration Technology Co ltd
Priority date: 2020-04-16
Filing date: 2020-04-16
Publication date: 2020-08-11
Anticipated expiration: 2040-04-16
Also published as: CN111522759B

Abstract

The invention discloses a device and a method for converting a multi-channel synchronous serial data bus into a parallel data bus, wherein the method comprises the following steps: a channel bit number counter, a channel bit number counting and holding counter and a data register; the channel digit counting and holding counter receives the inverted bit synchronization clock signal, counts the high level of the clock signal, generates a channel digit counting and holding enabling signal and transmits the channel digit counting and holding enabling signal to the channel digit counter; the channel digit counter receives the inverted bit synchronization clock signal, counts the high level of the inverted bit synchronization clock signal when the inverted bit synchronization clock signal and the channel digit counter are both effective, and transmits an ADC data code stream to the shift register; and when one frame of ADC data code stream counting is finished, the ADC data in the shift register is stored to the data register. In the conversion process, the data bits are calibrated by a bit synchronous clock in the daisy chain data interface bus, and code loss, error codes and wrong codes cannot occur.

Description

Device and method for converting multi-path synchronous serial data bus into parallel data bus

Technical Field

The invention belongs to the technical field of serial-parallel conversion, and particularly relates to a device and a method for converting a multi-channel synchronous serial data bus into a parallel data bus.

Background

The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.

In some applications, the requirements of the data acquisition system for analog/digital conversion (ADC) are multiple concurrent (synchronous), high resolution, high sampling rate, high output rate (matching with the sampling rate), the data throughput of the ADC converter is high, and most chip manufacturers adopt a daisy-chain data interface bus as a data interface of the ADC converter. The daisy chain data interface bus is easy to be matched with a DSP, an FPGA, a Microprocessor (MPU) with the daisy chain data interface bus and the like for use, the microprocessor with the daisy chain data interface bus is not common, the use technology threshold of the DSP and the FPGA is high, the hardware cost is high, the design difficulty and the complexity of a system are high, and the daisy chain data interface bus is not suitable for low-cost application occasions.

When the MPU without the daisy chain data interface bus is adopted, the daisy chain data interface bus occupies a large number of external input IO pins of the microprocessor, the pins generally need to have external interrupt input resources or capture resources, interrupt operation needs to be frequently carried out, system resource consumption is quite huge, and the requirement on the processing speed of the MPU is very high; meanwhile, the interrupt operation processing flow and the main processing flow influence each other, which seriously influences the smoothness of program execution and the code execution efficiency, and causes the occurrence of code loss and error code situation in data reception.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a device and a method for converting a multi-channel synchronous serial data bus into a parallel data bus, which can simultaneously receive input multi-channel synchronous serial data code streams, convert the data from a serial mode into parallel data, and read the data by an external microprocessor through a parallel interface so as to realize conversion.

In order to achieve the above object, one or more embodiments of the present invention provide the following technical solutions:

an apparatus for converting a multiplexed synchronous serial data bus to a parallel data bus, comprising: a channel bit number counter, a channel bit number counting and holding counter and a data register;

the channel digit counting and holding counter receives the inverted bit synchronization clock signal, counts the high level of the clock signal, generates a channel digit counting and holding enabling signal and transmits the channel digit counting and holding enabling signal to the channel digit counter;

the channel digit counter receives the inverted bit synchronization clock signal, counts the high level of the inverted bit synchronization clock signal when the inverted bit synchronization clock signal and the channel digit counter are both effective, and transmits an ADC data code stream to the shift register; and when one frame of ADC data code stream counting is finished, the ADC data in the shift register is stored to the data register.

One or more embodiments also provide a method of converting a multiplexed synchronous serial data bus to a parallel data bus, comprising:

receiving a serial data code stream from a serial data bus, and performing reverse phase operation on a bit synchronization clock signal;

continuously counting the high level of the inverted bit synchronization clock signal, and transmitting an ADC data code stream to a shift register;

and when one frame of ADC data code stream counting is finished, the ADC data in the shift register is stored to the data register, and the conversion from serial data to parallel data is finished.

The above one or more technical solutions have the following beneficial effects:

in the whole data format conversion process, data bits are calibrated by a bit synchronous clock in the daisy chain data interface bus, data are read according to frames through counting of bit synchronous clock signals, the frame length is strictly kept synchronous with the frame synchronous signals in the daisy chain data interface bus, and missing codes, error codes and wrong codes cannot occur.

The conversion of serial data to parallel data is achieved by buffering the data using a shift register.

The method is suitable for all MPUs with parallel data buses, can flexibly interface with ADC conversion chips with daisy chain data interface buses manufactured by chip manufacturers, is easy to realize, strong in adaptability and wide in application range, reduces the application technology threshold, reduces the hardware cost and the design difficulty of a printed circuit board, and also shortens the development period of application programs or codes.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention.

FIG. 1 is a schematic diagram of a daisy-chained data interface bus timing sequence in the prior art;

FIG. 2 is a block diagram of an apparatus for converting a multi-lane synchronous serial data bus into a parallel data bus according to an embodiment of the present invention;

FIG. 3 is a logic diagram of the conversion of multiple synchronous serial data buses into parallel data buses according to an embodiment of the present invention;

FIG. 4 is a timing diagram corresponding to the internal timing of the multi-channel synchronous serial data bus converted into the parallel data bus and the daisy-chain data interface bus timing according to the embodiment of the present invention.

Detailed Description

It is to be understood that the following detailed description is exemplary and is intended to provide further explanation of the invention as claimed. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

The embodiments and features of the embodiments of the present invention may be combined with each other without conflict.

First, the timing of the daisy chain data interface bus will be briefly described. As shown in fig. 1, the signals DCLK, DRDY, and DOUTn are all signal lines of the daisy-chain data interface bus of the external ADC converter, and n is 1,2,3, and 4 … …, which represents the number of analog channels or the number of serial data stream channels in the input daisy-chain data interface bus that can be supported.

The signal DCLK is a bit synchronization clock of the daisy chain data interface bus, the falling edge is valid, and the time from the rising edge to the next rising edge is one clock cycle Tc; the signal DRDY is a frame synchronization pulse of a daisy chain data interface bus, the duration is Tc, the signal DRDY is set to be logic 1 when the last bit synchronization clock DCLK of the previous frame rises, and the signal DRDY is set to be logic 0 until the next bit synchronization clock DCLK rises; the signal DOUTn is a certain path of synchronous serial data code stream output after the conversion of the analog signal channel of the daisy chain data interface bus is completed, and the synchronous serial data code stream comprises the bit of analog data of digital-to-analog conversion and the bit code stream of a check (or mark) word, and the data bit of the serial data code stream is effective when the DCLK falls.

Example one

The embodiment discloses a device for converting a multi-path synchronous serial data bus into a parallel data bus, which comprises: a channel bit number counter, a channel bit number counting and holding counter, a frame synchronization zero clearing counter, a write zero clearing device, a shift register, a data register (FIFO) and a data bus selector. Wherein the content of the first and second substances,

the channel digit counting and holding counter receives the inverted bit synchronization clock signal, counts the high level of the clock signal, generates a channel digit counting and holding enabling signal and transmits the channel digit counting and holding enabling signal to the channel digit counter; when the inverted bit synchronous clock signal is counted to a preset size, the channel bit number counting holding enable signal is disabled.

The channel digit counter receives the inverted bit synchronization clock signal, counts the high level of the inverted bit synchronization clock signal when the inverted bit synchronization clock signal and the channel digit counter are both effective, and transmits an ADC data code stream to the shift register; when one frame of ADC data code stream counting is finished, ADC data in the shift register is stored in the data register, and meanwhile, a pulse signal of finishing ADC data format conversion is output so as to inform an external MPU (micro processing unit), and the MPU reads out the ADC data through a parallel data bus; if the bit synchronous clock signals are simultaneously effective, a counter clear signal is generated, and the count related in the channel bit number counter is cleared.

And the frame synchronization zero clearing counter is used for receiving the frame synchronization pulse signal and inverting the frame synchronization pulse signal, and generating the frame synchronization zero clearing signal when the inverted frame synchronization pulse signal jumps along the rising edge and the channel bit number counting and maintaining enable signal fails.

And the write zero clearing device is used for receiving a write signal of the external microprocessor and a strobe signal of a parallel bus of the external microprocessor pointing to the data register space, generating a data register zero clearing signal when the write signal and the strobe signal are both effective, and generating a shift register zero clearing signal when one of the data register zero clearing signal and the counter zero clearing signal is effective.

And the shift registers receive the inverted bit synchronization clock signals, and move one bit of data to the left simultaneously when the inverted bit synchronization clock signals are at a high level.

As shown in fig. 2 and 3, the channel bit number counter includes an and gate U1, a counter U2, a D-type flip-flop U3, an inverter U4, an and gate U5, or a gate U6; the channel bit number counting and maintaining counter comprises a counter U8 with an enable, an AND gate U9, a D-type flip-flop U11 with an enable and an inverter U10; the frame synchronization zero clearing counter comprises an inverter U12, an AND gate U13, an inverter U14, an enabled D-type flip-flop U15, an enabled D-type flip-flop U16 and an AND gate U17; the write zero clearing device comprises an AND gate U18, an inverter U19, an enabled D-type flip-flop U20 and an OR gate U21; the shift register comprises a 32-bit shift register consisting of four 8-bit left shift registers with zero clearing, namely U22, U24, U26 and U28; the data register (FIFO) consists of 4 zero clearing 8-bit data registers U23, U25, U27 and U29, and the data bus selector is U30 in the figure.

In the following description, the above logic circuits are abbreviated as Ux, where x is a serial number and x is 1,2, and 3 … … 30. The internal logic circuit Ux is a functional logic circuit composed of one or more simple digital gate circuits to realize a desired logic function, and the logic unit described in the following description has the same meaning. Hereinafter, "/" indicates a signal which is an inverse of a signal without "/" in the same name, and is the same signal as that described with the same name underlined in fig. 2 and 3, and is the same as that described when "/" appears in the following description.

After the logic circuit is powered on, the initial states of all internal logic circuits are default values, the outputs Q or Qn (where n denotes an output terminal of a counter and denotes an index of 2, and generally n is 1,2,3,4, 5, and the like) of a timer, a flip-flop, a shift register, a data register, and the like in the device are all 0, and the trigger clocks are all active at a rising edge, so that an enable input high level is active, and a clear input high level is active.

The channel bit counter comprises logic units such as U1, U2, U3, U4, U5 and U6, and the signals DCLK,/DCLK and DK _ E, DK _ D1 (Q5 output of U2, which represents a count value of 2⁵32), ALE (Q5 output of U3, indicating count value 2⁵32), IRQ, ALE _ S, DK _ CLR, EN _ CT, S _ CLR, etc. are input and output signals of the present logic unit.

Wherein the/DCLK is generated from DCLK through the inverter U7 output; the S _ CLR is from the output of U21 in the write zero device; the EN _ CT is from the output of U10 in the channel bit count hold counter.

The EN _ CT is initialized to be logic level 1, and the ALE, the S _ CLR and the DK _ D1 are initialized to be logic level 0. The rising edge of the output after the/DCLK and EN _ CT pass through U1 triggers the counter U2 to count, the U2 counts the rising delay to the 32 th/DCLK, the output DK _ D1 of the U2 jumps from logic 0 to logic 1, and the rising edge triggers the U3 to latch logic 1 to the output ALE; one path of the ALE is transmitted to the input end of a trigger clock of a data register FIFO so as to latch data of the ADC; one path of the ALE is subjected to inversion through U4 to output logic 0 to an external circuit so as to identify the completion/validity of ADC data format conversion; one path of signals of the ALE and the DCLK output ALE _ S through a U5, the ALE _ S and the S _ CLR output a counter zero clearing signal DK _ CLR through an OR gate U6 to be logic 1, the DK _ CLR clears U2 and U3, the signals DK _ D1, the ALE and the ALE _ S are all restored to be logic 0, the IRQ is restored to be logic 1, and the channel bit counter is ready for counting the next frame of ADC data code stream.

The channel bit number counting and holding counter consists of logic units such as U8, U9, U11 and U10, and signals/DCLK, EN _ CT, DK _ D2, DCLK, DK _ D2S, CK _ L, FS and the like are input and output signals of the logic units.

The DK _ D2, the CK _ L, the FS and the DK _ D2S are initialized to be logic level 0, a signal EN _ CT output by the CK _ L through the inverter U10 is logic level 1, the EN _ CT is connected with an enable control end CE of the U8 and an enable control end CE of the U10, and the counting function of the U8 and the triggering function of the U10 are enabled. The rising edge of the/DCLK triggers U8 to count, when the rising delay of the 32 th/DCLK is counted, the output DK _ D2 of the U8 jumps from logic 0 to logic 1, and after 1/2 clock cycles Tc, the DK _ D2 and the DCLK pass through U9, so that the output signal DK _ D2S jumps from logic 0 to logic 1; the DK _ D2S is transmitted to a clock end of the U11, and the rising edge of the DK _ D2S triggers the CK _ L output of the U11 to jump to logic 1; the CK _ L passes through the U10, the output signal EN _ CT is converted into logic 0, and the output states of the U1, the U8 and the U11 are locked and unchanged; and the other path of CK _ L and DY _ P pass through U17 in the frame synchronization zero clearing device, an output signal FS of the CK _ L jumps to logic 1 (when DY _ P is logic 1), U8 and U11 in the channel bit number counting and maintaining counter are cleared to restore to a default state, and ADC data code stream counting of the next frame is prepared.

The transition time of the signal FS lags behind the transition time of CK _ L, the lag time is adjusted by increasing or decreasing the stage number of the logic circuit in U17, the FS pulse has enough width to ensure that the normal logic of the related logic circuit can not be cleared or locked at the same time when the logic state is output, and then the FS pulse is restored to logic 0, and the logic 0 maintaining time meets the duration time interval of the next DCLK and DRDY.

In a time period from the time when the CK _ L jumps to logic 1 to the time before the FS pulse jumps to logic 1, the EN _ CT at logic 0 latches the output DK _ E of the U1 of the channel bit counter to logic 0, and is not controlled by the signal/DCLK, the U2 stops counting and the DK _ D1 keeps logic 1; after FS is enabled and CK _ L is cleared to set EN _ CT to logic 1, the output DK _ E of U1 is controlled by the signal/DCLK, and the channel bit counter resumes the counting function, which is the function of the channel bit count holding counter.

The valid time of the ALE and the ALE _ S, DK _ CLR is earlier than the FS, and the total time from the valid time of the ALE and the ALE _ S, DK _ CLR to the process that the FS jumps to be valid and the FS jumps to be invalid is longer than 1/2Tc and shorter than Tc.

The frame synchronization zero clearing counter comprises logic units such as U12, U13, U14, U15, U16 and U17, and the DRDY,/DCLK, DK _ G, DY _ D, DY _ CE, DY _ P, FS and the like are input and output signals of the logic units.

The DK _ G, DY _ D, DY _ P, FS is logic 0 after being initialized; and a signal DY _ CE output by the DY _ D through the U14 is logic 1, and the DY _ CE is connected with the enabling end CE of the U15 and enables the function of the U15. The DRDY and/DCLK outputs DK _ G through U13, and the rising edge of the DK _ G triggers U15 to enable the latch output DY _ D to be logic 1; the DY _ D outputs DY _ CE as logic 0 through the U14 so as to inhibit the trigger function of the U15, and the DY _ D is connected to the enabling terminal CE of the U16 so as to enable the function of the U16; when DRDY output by U12 is rising edge jumping, output signal DY _ P of U16 is triggered to jump to logic 1; DY _ P and a signal CK _ L (logic 1 in this case) output from the channel bit number count holding counter output through U17 output signal FS; the FS is respectively supplied to the channel bit counter, the channel bit count hold counter, the write clear device, the shift data latch, and the like, and the output of each logic unit is cleared to be logic 0.

The FS is a frame data synchronization clear signal, the CK _ L output from the channel bit count holding counter and the DY _ P output from the U16 are logically output after passing through the U17, and when the FS is logical 1, U2, U3, U8, U11, U15, U16, U20, U22, U24, U26, and U28 are all cleared to return to a default state.

The write zero clearing device comprises logic units such as U18, U19, U20 and U21, wherein CS, WR _ CS, WR _ CLR, ALE _ S, S _ CLR and the like are input and output signals of the logic units. The U20 initializes the WR _ CLR to a logic 0, which is inverted to a logic 1 via U19 and enables the toggle function of U20.

The write signal WR comes from a parallel data bus of an external MPU, is a write effective flag bit, and has an effective rising edge; when the external MPU write signal WR is logic low level/falling edge effective, the logic inverter is arranged in the device to convert the logic inverter into rising edge effective. The data selection bus and other data buses are from the parallel bus of the external MPU connected with the device, and the addressing spaces of the data selection bus and other data buses are all in the addressing range of the external MPU; the internal signal CS is a strobe signal of a parallel bus of the external MPU pointing to a buffer FIFO space of the internal buffer ADC data, can be generated by data selection bus logic, and is effective in high level; in addition to the above signals, the other signals are generated by internal logic circuits.

When the CS and the WR are both effective, the CS and the WR output WR _ CS after passing through U18, and the rising edge of the WR _ CS triggers U20 to output a data register clear signal WR _ CLR as logic 1; the WR _ CLR passes through the U19 all the way to output logic 0, so that the trigger function of the U20 is not enabled, and the WR _ CLR is enabled to be unchanged; the WR _ CLR path and the ALE _ S output a shift register clear signal S _ CLR as 1 through U21, so that the U2, U3, U22, U24, U26 and U28 are cleared; the WR _ CLR is sent to and cleared from the aforementioned U23, U25, U27, U29 all the way.

The WR _ CLR is cleared when the FS is active, and S _ CLR is inactive when the ALE _ S is inactive.

As shown in fig. 2, the shift register is a 32-bit shift register composed of four 8-bit left shift registers U22, U24, U26 and U28, the 32-bit shift register has 4 groups, the 4 groups of 32-bit shift registers have 128 bit data bits (16 bytes) in total, and the data code stream buffering with various bit numbers can be realized by increasing or decreasing the number of the groups of the 32-bit shift register.

The input ports of the 32-bit shift register comprise WR _ CLR, DOUTn,/DCLK, S _ CLR, ALE; DOUTn is the serial number of one of the data stream port lines in the daisy-chain interface bus of the external digital-to-analog converter ADC, and may be n-1, 2,3,4, … …, etc., where n-4 (taking 4 channels as an example).

Q0 for latching the state of DOUTn at the rising edge of the/DCLK, the original Qn (n is 0,1 … …, 7) of the U28 synchronously shifts left by one bit, the original Q7 of the U28 is transmitted to the U26 and stored in the Q0 of the U26, the original Qn of the U26 shifts data bits according to the working principle of the U28, and similarly, the U24 and the U22 simultaneously shift left by one bit of data at the rising edge of the/DCLK; when the rising edge of the/DCLK jumps 32 times, the 32-bit data bit of DOUTn is respectively latched to the output end of the 32-bit shift register, thus completing the conversion from the serial ADC data code stream to the parallel ADC.

The functions of WR _ CLR,/DCLK, S _ CLR, ALE, etc. are described in the foregoing description.

The data register (FIFO) and data bus selector, as shown in FIG. 2, are composed of 4 data registers U23, U25, U27, U29 and data bus selector U30. The U23, U25, U27 and U29 latch and hold the bit output by the 32-bit shift register when the ALE jumps to logic 1; when the WR _ CLR is logic 1, the data held by U23, U25, U27 and U29 are cleared.

The input signals of the U30 include: DB0-DB7, DB8-DB15, DB16-DB23, DB24-DB31, other data buses, and a data selection bus. The DB0-DB7, DB8-DB15, DB16-DB23, DB24-DB31 are internal retention buses that the data register FIFO latches ADC data; the other data buses refer to data address buses in part or all of the storage spaces of the data memory except the addressing space pointing to the FIFO of the data register when the other data buses are applied to a certain system and the external MPU distributes data storage spaces in a unified manner; the data selection bus is an address bus pointing to the addressing space of the data register FIFO when the external MPU distributes the data storage space in a unified way.

The timing sequence of the above logic process is shown in fig. 3.

The device can simultaneously receive multi-channel synchronous serial data code streams transmitted by a daisy chain data interface bus, the serial data code streams of each channel of ADC conversion are converted into parallel data at one time and stored in a data buffer (FIFO), at the moment, a data conversion completion notification pulse is output so as to notify that the ADC data buffered by an external MPU is valid, the external MPU reads the ADC data buffered in the data buffer through the parallel data bus, and the FIFO cannot be cleared in the data reading process.

The conversion device described in this embodiment is suitable for all MPUs having parallel data buses (or emulating parallel data buses using IO interfaces), and occupies few MPU resources, thereby reducing the system load. The method is easy to realize, can flexibly interface with the ADC conversion chip with the daisy chain data interface bus manufactured by each chip manufacturer, has strong adaptability and wide application range, reduces the threshold of application technology, and reduces the hardware expense and the design difficulty of the printed circuit board.

Example two

The present embodiment is directed to a method for converting a multiplexed synchronous serial data bus into a parallel data bus. The method comprises the following steps:

and when one frame of ADC data code stream counting is completed, the ADC data in the shift register is stored in the data register, the conversion from serial data to parallel data is completed, and the ADC data is read out by the MPU through the parallel data bus.

In order to ensure that the external MPU can read data in time, when one frame of ADC data code stream counting is completed, a pulse signal of which the ADC data format conversion is completed is also output.

In order to ensure the efficiency of data conversion and the counting accuracy, when one frame of ADC data code stream is counted, if the bit synchronization clock signal is at high level, a counter zero clearing signal is generated.

The whole conversion process is calibrated by a bit synchronous clock signal, and strictly keeps synchronization with a frame synchronous signal and a data bit synchronous clock in a daisy chain data interface bus, so that the conversion efficiency of data is higher.

The steps related to the second embodiment correspond to the first embodiment, and the detailed description thereof can be found in the relevant description of the first embodiment.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.

Claims

1. An apparatus for converting a multiplexed synchronous serial data bus to a parallel data bus, comprising: a channel bit number counter, a channel bit number counting and holding counter and a data register;

2. The apparatus as claimed in claim 1, wherein the channel bit counter outputs a pulse signal indicating completion of the ADC data format conversion when the channel bit counter completes counting of one frame of ADC data stream.

3. The apparatus according to claim 1, wherein the channel bit counter generates a counter clear signal if the bit synchronization clock signal is active simultaneously when the channel bit counter completes counting one frame of ADC data stream.

4. The apparatus of claim 1, wherein the lane bit count hold enable signal is disabled when the lane bit count hold counter counts the inverted bit sync clock signal to a predetermined size.

5. The apparatus according to claim 3, further comprising a write clearer for receiving a write signal from an external microprocessor and a strobe signal from the parallel bus of the external microprocessor to the data register space, and for generating a data register clear signal when both are active, and for generating a shift register clear signal when one of the data register clear signal and the counter clear signal is active.

6. The apparatus of claim 1, wherein the shift register receives an inverted bit-synchronous clock signal, the shift register shifting one bit of data to the left simultaneously when the inverted bit-synchronous clock signal is high.

7. The apparatus as claimed in claim 5, wherein the apparatus further comprises a frame synchronization clear counter for receiving and inverting the frame synchronization pulse signal, and generating the frame synchronization clear signal when the inverted frame synchronization pulse signal has a rising edge transition and the channel bit count hold enable signal is disabled.

8. A method for converting a multiplexed synchronous serial data bus to a parallel data bus, comprising:

9. The method according to claim 8, wherein the pulse signal after completion of the ADC data format conversion is further outputted when the counting of one frame of ADC data stream is completed.

10. The method as claimed in claim 8, wherein when one frame of ADC data stream is counted, if the bit synchronization clock signal is at high level, the counter clear signal is generated.