TWI604303B - Inout/output expander chip and verification method therefor - Google Patents

Description

Input and output extension chip and verification method thereof

This case is about input/output expander (IOE) chip and its verification method.

The wafer has to be verified after the tapeout. The verification program usually captures the debug signal of different hardware modules inside the chip for analysis to achieve the purpose of debugging.

Taking a chipset as an example, a large number of high-speed input/output pins (IO pins) are detected via a DRAM controller.

However, an input/output extension chip (IOE chip; for example, a high-speed peripheral component interconnect switch (PCIE switch) does not necessarily have a hardware like a dynamic random access memory controller having a large number of high-speed input and output pins, a conventional solution Additional input and output pins are added for wafer verification. As a result, the package size and cost will increase significantly. In particular, the added input and output pins (eg, general purpose input and output pin (GPIO)) are typically connected to a logic analyzer to display the waveform of their signals for debugging. However, the general-purpose input/output pin (GPIO) has a limited operation speed, which is disadvantageous for high-speed internal signal detection, which may cause distortion of the debug signal.

The present invention discloses an input/output extension chip that can utilize the existing signal downstream port to output a signal for debugging without excessively limiting the transmission speed.

An input/output extension chip implemented according to an embodiment of the present invention includes a debug signal generator, a debug packet generator, and at least one signal downlink. The debug signal generator generates a debug signal according to a combination of signals obtained by sampling at least one hardware module of the input/output extension chip from a main clock in the input/output extension chip. The debug packet generator generates a debug packet, wherein the debug packet carries the debug signal. The debug packet is output from the input/output extension chip via one of the at least one signal downlink to perform signal detection.

The present invention discloses an input/output extended chip verification method, wherein an embodiment includes the following steps: generating a Detector according to a signal combination obtained by sampling at least one hardware module in the input/output extension chip according to an input/output extension chip internal master clock Generating an error detection packet, wherein the error detection packet carries the error detection signal; and transmitting the error detection packet to one of at least one signal downlink of the input/output extension chip from the Input and output extended chip outputs for signal debugging.

The foregoing input/output extension chip and the verification method thereof of the invention package the error detection signal into a debugging package, and use the input and output extension chip to extend the existing signal of the chip as the input/output port of the wafer verification, without additional input and output. Feet. In addition, the primary clock for sampling of the present invention can be selected from the higher operating clocks on the input and output extension chip; for example, the operating clock for direct memory access (DMA). In this way, there is no need to provide dedicated for wafer verification. The clock is quite cost effective.

The invention is described in detail below with reference to the accompanying drawings.

100‧‧‧Input and output expansion chip

102_1...102_N‧‧‧ hardware module

104_1...104_N‧‧‧sampler

106‧‧‧Detection signal generator

108‧‧‧Detection packet generator

110‧‧‧ router

112‧‧‧ Signal Downstream

202‧‧‧Circular Card

204‧‧‧Signal Analysis Software

206‧‧‧Verification computer

208‧‧‧ Protocol Analyzer

400‧‧‧sampler

402‧‧‧ Register

404‧‧‧Multiplexer

Interrogation packet for 600‧‧‧64-bit encapsulation mode

610‧‧‧32-bit encapsulation mode debug packet

Async_FIFO_0...Async_FIFO_3‧‧‧First In First Out Buffer

DBBG_GRP0[0]...DBBG_GRP0[n], DBBG_GRP1[0]...DBBG_GRP1[n], DBBG_GRP2[0]...DBBG_GRP2[n], DBBG_GRP3[0]...DBBG_GRP3[n]‧‧‧ Data

DP‧‧‧Detection packet

DP_S‧‧‧ Serial debugging package

DS‧‧‧Detection signal

MS_CLK‧‧‧Main clock

S302...S312, S502...S508‧‧‧ steps

1 is a diagram illustrating an input/output extension chip 100 according to an embodiment of the present invention; FIG. 2 is a diagram illustrating a connection state when the input/output extension chip 100 is verified according to an embodiment of the present invention; and FIG. 3 is a flowchart with FIG. 1 and FIG. FIG. 4 illustrates a sampler 400 corresponding to a hardware module according to an embodiment of the present invention; FIG. 5 illustrates a flow chart according to an embodiment of the present invention. Signal sampling of the hardware module; FIG. 6A illustrates a 64-bit encapsulation mode debug packet 600 according to an embodiment of the present invention; and FIG. 6B illustrates a 32-bit encapsulation mode debug packet 600 according to an embodiment of the present invention.

The following description sets forth various embodiments of the invention. The following description sets forth the basic concepts of the invention and is not intended to limit the invention. The scope of the actual invention shall be defined in accordance with the scope of the patent application.

Figure 1 illustrates an input/output expansion according to an embodiment of the present invention. The wafer 100 includes a plurality of hardware modules 102_1, 102_2...102_(N-1), 102_N, a plurality of samplers 104_1, 104_2...104_(N-1), 104_N, a debug signal generator 106, and a The debug packet generator 108, a router 110, and at least one downstream port 112 (only the selected signal downlink 112 is shown for simplicity in the figure).

The samplers 104_1, 104_2, ..., 104_(N-1), 104_N are respectively corresponding to the hardware modules 102_1, 102_2, ..., 102_(N-1), 102_N, according to the input/output extension chip 100, a main clock MS_CLK A signal is obtained from the corresponding hardware module sample, and the debug signal generator 106 is combined to generate a debug signal DS. The error detection packet generator 108 is configured to generate an error detection packet DP, and the error detection packet DP carries the error detection signal DS. The debug packet DP is output from the input/output extension chip 100 via one of the signal downlinks 112 for signal detection. In one embodiment, the router 110 transmits the debug packet DP to the selected signal downlink 112. The signal downlink 112 can be implemented by the physical layer implementing parallel-to-serial conversion of the packet for debugging, and outputting the serial debugging packet DP_S.

The master clock MS_CLK may be selected from the higher operating clocks that are present on the input and output extension die 100. For example, the high frequency ones in the operating clocks of the hardware modules 102_1, 102_2...102_(N-1), 102_N are selected. For example, use the operating clock for direct memory access (DMA). In this way, the case does not need to provide a dedicated clock for wafer verification, which is quite cost-effective.

In particular, the signal downlink 112 can also be a conventional input/output extension chip, without additional addition for wafer verification. Traditional I/O expansion chips usually use signal downlinks to connect external devices or cascade other interfaces. Extend the switcher. In this case, the signal downlink is used as the input/output port for wafer verification.

In one embodiment, the input and output extension die 100 can be a high speed peripheral component interconnect switch (PCIE switch). The signal downlink 112 can be a PCIE downstream port. The router 110 can be a combination of a PCIE hub and a multiplexer, so that the debug packet DP is transmitted to the PCIE downlink via the multiplexer via the PCIE hub. In addition, the multi-lane feature of the PCIE switcher also helps to transmit high-speed, large amounts of data for debugging. The PCIE switcher is more suitable for applying the technology without being limited to the controller driver. It is worth noting that, in addition to the PCIE switch, other chips that have signal down-going, multi-channel, and can be packaged without being limited by the controller driver are suitable for use in the present technology.

According to the above definition, the main clock MS_CLK is used as the hardware module sampling, and the design of the existing signal downlink 112 is used for output, which is not only low in cost, but also has a higher transmission speed output signal for debugging. It should be noted that, in the case where the process and cost of the input/output extension chip 100 are allowed, the higher of the existing operation clocks is selected as the main clock MS_CLK for sampling, and the distortion of the obtained error detection signal is smaller. However, low-cost wafers often do not allow the use of too high operating clocks, so the present invention selects which of the existing operating clocks on the input-output expansion chip 100 as the primary clock MS_CLK depends on the process of the input-output expansion chip 100. And the cost, that is, the main clock MS_CLK of the present invention is the higher of the existing operating clocks allowed by the process conditions and cost.

In one embodiment, the input and output extension chip 100 is further integrated with a south bridge of a chip set.

In an implementation manner, the hardware modules 102_1, 102_2...102_(N-1), 102_N may be PCIE hardware, XHCI hardware, SATA hardware, GNIC hardware, etc., as for which signals are provided for debugging, The user sets a specific control register decision via a specific input/output system (BIOS) or a specific debug tool in the operating system (OS). However, the signal obtained directly by the hardware module on the chip is relatively high speed (for example, 60M~500M). One embodiment of the present invention is to capture the error detection packet by the protocol analyzer coupled to the signal downlink 112 (the latter) 2 will be detailed), and then analyze the captured debug packet for offline debugging, which is more real-time analysis than the low-speed general-purpose input and output pin (GPIO) coupled logic analyzer (LA). The prior art of misdetecting the waveform of the signal is better because the low speed GPIO pin may introduce distortion of the debug signal.

FIG. 2 illustrates a connection condition when the input/output extension chip 100 is verified according to an embodiment of the present invention. The input/output extension chip 100 is coupled to a loopback card 202 via the signal downlink 112 to establish a link status, so that the input/output extension chip 100 is serially debugged with the packet DP_S. It is captured by a protocol analyzer 208 for debugging. In an embodiment, the loopback card 202 sends the error detection packet DP_S outputted from one of the signal downlinks 112 (TX) back to the receiving end (RX) of the signal downlink 112 to establish a corresponding A link to a protocol (such as the PCIE protocol).

One embodiment is to use a signal analysis software 204 to debug the debug packet DP_S captured by the protocol analyzer 208. With PCIE switch For example, in a conventional application, the protocol analyzer 208 is configured to capture PCIE packets between a PCIE switch and a PCIE device for analysis. According to an embodiment of the present invention, the protocol analyzer 208 is a serial debug packet DP_S between the capture signal downlink 112 and the loopback card 202. The signal analysis software 204 can analyze the protocol analyzer 208 offline. The captured serial debug packet uses the valid information in the packet DP_S to convert the digital signal into an easy-to-understand waveform for error detection. In particular, the signal outputted by the input/output extension chip 100 in a packetized manner is stored in the protocol analyzer 208 in a txt file. In an embodiment, the text file can be copied to the verification computer when analysis is required. 206, the signal analysis software 204 of the verification computer 206 is used for analysis to implement debugging, so that the input/output extension chip 100 does not need to specifically set a storage space to store the error detection packet DP_S, and the error analysis can be performed offline in the verification computer. Performed on 206 to improve the efficiency of capturing debug signals.

One embodiment of the present invention is an input/output extended wafer verification method, and FIG. 3 is a flowchart with the first and second figures. Step S302 is coupled to the signal downlink 112 to the loopback card 202, and the loopback card 202 simulates the response signal downlink 112, establishes the connection state of the signal downlink 112, and the output signal is sent out by the protocol analyzer. 208 grabbed for debugging. Step S304, the samplers 104_1, 104_2, ..., 104_(N-1), 104_N respectively obtain signals from the hardware modules 102_1, 102_2, ..., 102_(N-1), 102_N according to the main clock MS_CLK, and the signals are obtained. Step S306 combines to generate the error detecting signal DS. Step S308 generates a debug packet DP that carries the debug signal DS. Step S310 transmits the error detection packet DP to the signal downlink 112. In step S312, the signal downlink 112 performs parallel-to-serial conversion on the debug packet DP, and outputs serial The link state established by the loopback card 202 by the debug packet DP_S is captured by the protocol analyzer 208 for debugging.

Since the operating clocks of the hardware modules 102_1, 102_2, ..., 102_(N-1), 102_N are quite diverse, clock domain switching (Clock Domain Crossing, CDC) is required to uniformly sample the main clock MS_CLK. For example, the operating clock of USB3 hardware can be as high as 500M, far exceeding the operating time of other low-speed hardware (for example, 60M, 120M, 125M, 250M). When the main clock MS_CLK is selected to be 250M, the clock domain conversion requirement is corresponding.

In one embodiment, the samplers 104_1, 104_2...104_(N-1), 104_N are in a multi-layer structure of a FIFO buffer, respectively for the samplers 104_1, 104_2...104_(N-1 And at least one of the hardware modules 102_1, 102_2...102_(N-1), 102_N corresponding to 104_N implements clock domain conversion (CDC), and converts the corresponding signal to the main clock MS_CLK. The clock domain is such that the signal obtained from the sampling of the corresponding hardware module according to the main clock MS_CLK is not distorted.

Regarding the processing of data, facing the operation clocks of the hardware modules 102_1, 102_2...102_(N-1), 102_N, the samplers 104_1, 104_2...104_(N-1), 104_N need to operate the data unit The clock is unified. In one embodiment, the disclosed sampler divides a plurality of registers and a plurality of multiplexers to divide the extracted signals supplied by the corresponding hardware modules into complex arrays, wherein the operation clocks of the same group of signals are the same. Clock domain.

FIG. 4 illustrates a sampler 400 corresponding to a hardware module according to an embodiment of the present invention, wherein the first-in first-out buffers Asyn_FIFO_0...Asyn_FIFO_3 required for clock domain conversion are further required to be used for signal division. A plurality of registers 402 and a plurality of multiplexers 404. As shown, each 16-bit metadata supplied by the hardware module will be pushed into register 402 in parallel in x4 mode. For example, the on-picture register 402 stores (n+1)x4 pen 16-bit metadata DBBG_GRP0[0]...DBBG_GRP0[n], DBBG_GRP1[0]...DBBG_GRP1[n], DBBG_GRP2[0]...DBBG_GRP2[n], DBBG_GRP3[ 0]...DBBG_GRP3[n]. After being selected by the multiplexer 404, each 16-bit metadata unit actually passed to the subsequent module for debugging can ensure that the 16-bit clock is synchronized (eg, the operating clock belongs to the same clock domain).

The following discusses how the first-in first-out buffer Asyn_FIFO_0...Asyn_FIFO_3 implements clock domain conversion.

The frequency of a signaled signal (numbered DB_CLK) of a signal (a number selected by the multiplexer 404 from the corresponding register 402 stored (n+1) of the pen signals) is greater than or equal to the frequency of the signaled clock (numbered DB_CLK). The frequency of the main clock MS_CLK is less than or equal to the frequency of the main clock MS_CLK (for example, the main clock MS_CLK is 250M, and 125M DB_CLK 250M), the disclosed sampler 400 pushes the signal to be input into a first-in first-out buffer (Asyn_FIFO_0...Asyn_FIFO_3) according to the signaled clock pulse DB_CLK, and then pushes the data according to the main clock MS_CLK. The first in first out buffer. The first-in first-out buffer can be designed as four layers in one embodiment because the clock of the data push (Pop) is faster or the same frequency as the data push, that is, the data is not in the first-in first-out. Accumulated in the buffer, but considering the data push/pop pointer generation requires 2 clock cycles, the design first in first out buffer design provides 4 layers of depth.

When the frequency of the signaled signal clock DB_CLK of the signal is greater than the frequency of the main clock MS_CLK and less than or equal to twice the frequency of the main clock MS_CLK (for example, 250M<DB_CLK) 500M), the disclosed sampler 400 down-converts the signal clock DB_CLK, and widens the number of bits of the signal to be taken. According to the frequency-reduced signal, the signal is widened by the number of bits. The signal is pushed into a plurality of parallel first-in first-out buffers (a plurality of Asyn_FIFO_0...Asyn_FIFO_3), and then the data is pushed out to the parallel first-in first-out buffers according to the main clock MS_CLK. Taking the signal timing DB_CLK of the 300M frequency as an example, the signal of the 16-bit x300M signal needs to be down-converted half to 32-bit x150M, and then divided into two groups of 16-bit 150M frequency signals and pushed into two parallel groups. First-in first-out buffers (for example, ASYNC_FIFO_0 and ASYNC_FIFO_1) implement clock domain conversion in parallel.

As for the frequency of the main clock MS_CLK is greater than twice the frequency of the signal clock DB_CLK (for example, DB_CLK<125M), according to the sampling theorem, the sampling clock is sampled more than 2 times higher than the signal to be taken, even if the sampling clock is sampled. The data is not in the same time domain as the signal being acquired, and the data obtained after sampling can restore the original signal. Therefore, the signal can be sampled without first-in first-out buffer (one of Asyn_FIFO_0...Asyn_FIFO_3), and the signal is directly sampled by the main clock MS_CLK. Alternatively, the signal of such a condition is still sampled by the primary clock MS_CLK using a first-in first-out buffer (as shown in Figure 4).

Figure 5 illustrates a signal sampling of a hardware module in accordance with an embodiment of the present invention in a flow chart. Step S502 compares the main clock MS_CLK and the signaled clock time DB_CLK. If the comparison result is 0.5MS_CLK DB_CLK MS_CLK, the flow proceeds to step S504, according to the extracted signal clock DB_CLK, the signal is pushed into the first-in first-out buffer, and then the data is pushed out of the first-in first-out buffer according to the main clock MS_CLK. If the comparison result is MS_CLK<DB_CLK 2MS_CLK, the process proceeds to step S506, the frequency signal DB_CLK is down-converted, and the number of bits of the signal is widened. According to the frequency-reduced signal, the signal is widened by the number of bits. Pushing in parallel multiple first-in first-out buffers, and then pushing data into parallel first-in first-out buffers according to the main clock MS_CLK. If the comparison result is DB_CLK<0.5MS_CLK, the flow proceeds to step S508, and the taken signal is directly sampled by the main clock MS_CLK without the first-in first-out buffer. Alternatively, step S508 can also be sampled by the primary clock MS_CLK using the first in first out buffer according to the fourth figure design.

The following discusses how the error detection signal DS is carried in the error detection packet DP. In one embodiment, the error detection signal DS is encapsulated in the payload data of the error detection packet DP, and the header corresponding to the packetized error detection signal DS is encapsulated in the error detection packet DP. Address area (address). The debug DP can carry up to N of the debug signal DS. N is a number, which is related to the address area width of the debug packet DP. The wider the address area of the debug packet DP, the more the number of headers that can be recorded, and the higher the N value.

FIG. 6A illustrates a 64-bit encapsulation mode error detection packet 600 according to an embodiment of the present invention, including a data transaction layer packet (Transaction Layer Packet (TLP) address area, and a TLP load 0...TLP load 2 TLP. Load data area. The TLP load data area is in a 64-bit package mode, each corresponding to an 8-bit header. Limited by the width of the TLP address area of 64 bits, a total of six error detection signals DS are packaged by the TLP load data area, respectively, packet 0 ... packet 5. In addition to the header of packet 0 (packet 5), the TLP address area contains a plurality of headers. The lower bits (e.g., the lower 14 bits [13:0]) are set to a fixed value (14'h0) to avoid cross-boundary address confusion (e.g., cross 4K boundary). Moreover, in one embodiment, the most significant bit of the TLP address region can be set to one to avoid that the all zero address region signal causes signal detection after outputting the input and output extension chip 100 to fail. It is to be noted that the input/output extension chip 100 is a high-speed peripheral component interconnection (PCIE) protocol specification, but the invention is not limited thereto. In this embodiment, the error detection packet 600 complies with the PCIE protocol specification, and the format is the same as the normal PCIE data transaction layer packet (TLP) packet, but the TLP address area is not like the normal TLP packet system carrying the memory address (memory Address), but the corresponding header containing the packet 0...packet 5: including the trigger flag, overflow flag and timer.

FIG. 6B illustrates a debug packet 610 of a 32-bit encapsulation mode according to an embodiment of the present invention, wherein the error detection signal of the TLP load data area is still limited by a width of 64 bits in the TLP address area. pen. However, the 32-bit encapsulation mode allows the TLP payload data area to include only TLP load 0 and TLP load 1.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧Input and output expansion chip

102_1...102_N‧‧‧ hardware module

104_1...104_N‧‧‧sampler

106‧‧‧Detection signal generator

108‧‧‧Detection packet generator

110‧‧‧ router

112‧‧‧ Signal Downstream

DP‧‧‧Detection packet

DP_S‧‧‧ Serial debugging package

DS‧‧‧Detection signal

MS_CLK‧‧‧Main clock

Claims (20)

An input/output extension chip includes: at least one hardware module and a corresponding sampler thereof; and a debug signal generator, based on the input and output according to the at least one hardware module and its corresponding sampler The signal combination obtained by expanding a main clock sample inside the chip generates a debug signal; a debug packet generator generates a debug packet, wherein the debug packet carries the debug signal; and at least A signal downlink, wherein the debug packet is output from the input/output extension chip via one of the at least one signal downlink for signal detection. The input/output extension chip of claim 1, wherein: one of the at least one signal downlinks establishes a connection state by coupling a loopback card, so that the error detection packet is obtained from the input. The output of the extended chip is captured by a protocol analyzer for error detection. The input/output extension chip of claim 1, further comprising: one of the at least one hardware module and one of the corresponding samplers, and the corresponding hardware module according to the main clock Sampling to obtain a signal. The input/output extension chip of claim 3, wherein: the samplers each comprise a first-in first-out buffer structure for implementing clock domain conversion on at least one of the signals of the corresponding hardware module. And converting the above-mentioned signal to the clock domain of the main clock. The input/output extension chip of claim 3, wherein: the frequency of the sampler in the main clock is greater than one of the corresponding hardware modules. When the frequency of the signal is doubled, the signal is directly sampled by the main clock. The input/output extension chip of claim 1, wherein: the sampler is at a frequency of a signal of a signal of the corresponding hardware module that is greater than or equal to the frequency of the main clock. When the frequency is less than or equal to the frequency of the main clock, the signal is pushed into a first-in first-out buffer according to the signaled time of the signal, and the data is pushed out according to the main clock. First out buffer. The input/output extension chip of claim 1, wherein: the frequency of a signal of a sampled signal of a sampled signal of the corresponding hardware module is greater than a frequency of the main clock, and When the frequency is less than or equal to twice the frequency of the main clock, the frequency of the signal is reduced, and the number of bits of the signal is widened. According to the frequency of the signal after the frequency reduction, the number of bits is widened. The signal is pushed into a plurality of parallel first-in first-out buffers, and the data is pushed out to the parallel first-in first-out buffers according to the main clock. The input/output extension chip of claim 1, wherein: the sampler divides the extracted signals supplied by the corresponding hardware module into a complex array by using a plurality of registers and a plurality of multiplexers, wherein the same The operating clocks of the grouped signals belong to the same clock domain. The input/output extension chip of claim 1, wherein: the debugging packet carries up to N pens of the debugging signal; and N is a number, and is related to the address area of the debugging packet. width. The input/output extension chip of claim 1, wherein: the address area of the error detection packet records each debug of the error detection packet The header of the signal is used; and the complex low-order bits of the address area of the packet are set to a fixed value to avoid confusion of cross-boundary addresses. An input/output extension chip verification method includes: providing a corresponding sampler for each of at least one hardware module of an input/output extension chip; and expanding the sampler according to the at least one hardware module and its corresponding sampler based on the input and output Generating a signal obtained by sampling a main clock sample inside the chip to generate a signal for detecting error; generating a packet for debugging, wherein the debugging packet is used to carry the signal for debugging; and transmitting the packet for debugging to the input and output One of the at least one signal downlink of the extended chip is output from the input and output extension chip for signal detection. The method for verifying the input/output extended chip according to claim 11, further comprising: coupling one of the at least one signal downlink to a loopback card to establish a link state, so that the debug packet is obtained from the The input and output extended chip outputs are captured by a protocol analyzer for debugging. The input/output extended chip verification method of claim 11, further comprising: operating one of the samplers to obtain a signal from the corresponding hardware module according to the main clock. The input/output extension chip verifier as described in claim 13 The method, wherein each of the samplers implements a clock domain conversion on at least one of the acquired signals of the corresponding hardware module in a first-in first-out buffer structure, and converts the extracted signal to a clock domain of the primary clock. The input/output extended chip verification method of claim 13, wherein: the sampler is at a frequency greater than a received signal of a received signal of the hardware module corresponding to the sampler when the frequency of the main clock is greater than When the frequency is twice the frequency, the signal is sampled directly by the main clock. The method for verifying the input/output extended chip according to claim 11, wherein: the sampler is at a frequency of a signal of a signal of the corresponding hardware module that is greater than or equal to the main clock. When the frequency of the second half is less than or equal to the frequency of the main clock, the signal is pushed into a first-in first-out buffer according to the signaled time of the signal, and then the data is pushed according to the main clock. The first in first out buffer. The input/output extended chip verification method according to claim 11, wherein: the sampler is at a frequency of a taken signal of a corresponding signal of the corresponding hardware module, and the frequency of the clock is greater than the frequency of the main clock. And less than or equal to twice the frequency of the main clock, down-clocking the signaled clock, and widening the number of bits of the signal to be taken, according to the frequency of the signal after the frequency reduction, the number of bits will be widened The subsequent signal is pushed into a plurality of parallel first-in first-out buffers, and the data is pushed out to the parallel first-in first-out buffers according to the main clock. The input/output extended chip verification method according to claim 11, wherein: the sampler divides the extracted signals supplied by the corresponding hardware modules into a complex array by using a plurality of registers and a plurality of multiplexers, respectively. The operating clocks of the same group of signals are in the same clock domain. The method for verifying the input/output extended chip according to claim 11, wherein: the debugging packet carries up to N pens of the debugging signal; and N is a number, which is related to the bit of the debugging packet. The width of the address area. The input/output extended chip verification method according to claim 11, wherein: the address area of the error detection packet records a header of each of the error detection signals carried by the error detection packet; and the Detector The plurality of low-order bits in the address area of the misuse packet are set to a fixed value to avoid confusion across the boundary address.