CN110515881A - A kind of synchronization system and synchronization high performance method of serial communication frame - Google Patents
A kind of synchronization system and synchronization high performance method of serial communication frame Download PDFInfo
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- CN110515881A CN110515881A CN201910781026.7A CN201910781026A CN110515881A CN 110515881 A CN110515881 A CN 110515881A CN 201910781026 A CN201910781026 A CN 201910781026A CN 110515881 A CN110515881 A CN 110515881A
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- serial communication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
Abstract
The present invention relates to a kind of synchronization system of serial communication frame and synchronous high performance methods; for the technological deficiency of existing serial communication frame synchronization; there is provided a kind of delay frame head searching method, it is ensured that the serial communication frame synchornization method verified again to complete data frame after complete data frame has been received in buffer area.Compare frame head and frame check code method simultaneously, erroneous judgement when can evade in serial communication frame data containing data identical with frame head, it is ensured that synchronous correctness.This method only uses a small amount of decision logic clear, can fast and effeciently realize the synchronization of serial communication, and program structure is clear, and operand is small can effectively to mitigate processor load, is also easy to transplant to other serial communication protocols.This synchronous method only needs to do a small amount of adaptation, and the serial communication frame data for being just able to satisfy various different-formats receive.
Description
Technical field
The present invention relates to the synchronization high performance method of serial communication frame, the frame suitable for control field serial port communication data is same
Step.
Background technique
Modern control system generally requires to complete its specific function by multiple independent control modules to cooperate jointly.Control
Data exchange is completed by serial communication between molding block, necessary communication protocol is added, in communication process to improve system
Reliability and stability, and to complete specific communication protocol, must there is certain synchronization mechanism.Common serial communication number
Include according to frame structure: frame head, frame type, data block, frame check code.The frame synchornization method of use includes: gradually comparing, is based on
Fifo queue and 3 kinds of frame synchornization methods based on state machine.These methods are directed to the byte received and are compared with frame head, come
Judge frame head, when being matched to the consistent sequence of frame head, which is synchronized as frame head.When in serial communication frame data
Containing data identical with frame head, frame synchronization can be caused to fail, cause communication failure；It seriously will cause in prolonged communication
It is disconnected, cause serious accident.
The byte of low probability appearance in a data frame is theoretically chosen as frame head；Or the length by increasing frame head,
It can be improved synchronous probability.However, the randomness of the first Various types of data is difficult to select general data as frame head；Second
It can reduce the probability for occurring frame head in frame data, but cannot thoroughly prevent the problem, while frame head is too long can also cause other
Problem.
Summary of the invention
Technical problem solved by the present invention is the present invention is directed to the technological deficiency of existing serial communication frame synchronization, one is provided
Kind delay frame head search, serial communication frame synchronization system and method based on partial data frame check.
The technical scheme is that a kind of synchronization system of serial communication frame, including serial data receiving module, annular
Buffered memory module, frame head search module, whole frame check module and frame data preserving module；
The serial data receiving module reads the data received in serial port chip FIFO in each communication cycle；And
Data are sequentially written in loop buffer memory module according to the sequencing of reading；Loop buffer memory module, to storing data
Length is judged；Frame head search module carries out the search of frame head first byte to loop buffer memory module storing data；Whole frame school
Test the verification that module carries out frame type to loop buffer memory module storing data, carries out verification sum to serial communication frame；Frame number
New communication data is received according to preserving module, using message mechanism notice main program according to command type to data frame at
Manage or execute corresponding command operation.
A further technical solution of the present invention is: a kind of synchronization high performance method of serial communication frame, feature exist
In, comprising the following steps:
Step 1: serial data receiving module receives the data in serial port chip FIFO, goes forward side by side in each communication cycle
Row is read；Data are sequentially written in loop buffer memory module according to the sequencing of reading after reading；
Step 2: loop buffer memory module judges storing data length, when storing data length is more than or equal to
When serial communication frame length, triggering frame head search module work；When storing data length is less than serial communication frame length, terminate
This is subsynchronous；
Step 3: frame head search module carries out the search of frame head first byte to loop buffer memory module storing data, if with
Frame head is inconsistent, then reads annular buffered memory module, continues frame head search；If consistent, storing data is first determined whether
Length is more than or equal to serial communication frame length, if length is more than or equal to serial communication frame length, triggers whole frame check module work
Make；
Step 4: whole frame check module carries out frame type to loop buffer memory module storing data, to serial communication frame
Carry out the verification of verification sum；If verification is correct, carries out whole frame and fall out, frame data preserving module is written in dequeued data；If verification
Mistake, then preceding byte is pseudo- frame head, falls out and works as byte, and returns to step 3；
Step 5: frame data preserving module receives new communication data, main program is notified using message mechanism, according to life
Type is enabled to be handled data frame or executed corresponding command operation.
Invention effect
The technical effects of the invention are that: the present invention has the following beneficial effects: compared with prior art
The present invention is directed to the technological deficiency of existing serial communication frame synchronization, provides a kind of delay frame head searching method, it is ensured that
The serial communication frame synchornization method verified again to complete data frame after complete data frame has been received in buffer area.Simultaneously
Compare frame head and frame check code method, erroneous judgement when can evade in serial communication frame data containing data identical with frame head,
Ensure synchronous correctness.
This method only uses a small amount of decision logic clear, can fast and effeciently realize the synchronization of serial communication, Er Qiecheng
Sequence structure is clear, and operand is small can effectively to mitigate processor load, is also easy to transplant to other serial communication protocols.
This synchronous method only needs to do a small amount of adaptation, and the serial communication frame data for being just able to satisfy various different-formats connect
It receives.
Detailed description of the invention
Fig. 1 is the frame format of typical serial communication frame.
Fig. 2 is the synchronization high performance method functional block diagram of serial communication frame of the invention.
Fig. 3 is that the loop buffer memory module in the present invention stores schematic diagram.
Fig. 4 is synchronization flow chart of the invention.
Fig. 5 is the first schematic diagram of the present embodiment
Fig. 6 is the second schematic diagram of the present embodiment
Specific embodiment
Referring to Fig. 1-Fig. 6, in order to make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached
Figure and embodiment, the present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only used for
It explains the present invention, is not intended to limit the present invention.
The technical solution adopted in the present invention is as follows:
(1) firstly, the present invention includes serial data receiving module, the serial data receiving module is in each communication week
Phase reads the data received in serial port chip FIFO.And data are sequentially written in loop buffer according to the sequencing of reading and are deposited
Store up module.
(2) loop buffer memory module judges storing data length.When storing data length is more than or equal to serial ports
When communication frame length, triggering frame head search module work；When storing data length is less than serial communication frame length, terminate this
It is synchronous.
(3) frame head search module carries out the search of frame head first byte to loop buffer memory module storing data, and if frame head
It is inconsistent, then annular buffered memory module is read, frame head search is continued；If consistent, storing data length is first determined whether
More than or equal to serial communication frame length, if storing data length is less than serial communication frame length, it is subsynchronous to terminate this；If length
When more than or equal to serial communication frame length, whole frame check module work is triggered.
(4) whole frame check module carries out frame type to loop buffer memory module storing data, carries out to serial communication frame
Verify the verification of sum.If verification is correct, carries out whole frame and fall out, frame data preserving module is written in dequeued data；If check errors,
Then preceding byte is pseudo- frame head, falls out and works as byte, and returns to (3).
(5) frame data preserving module receives new communication data, using message mechanism notice main program according to order class
Type is handled data frame or is executed corresponding command operation.
As shown in Figure 1, common serial port communication data frame structure includes: frame head, frame type, data block, frame check code.Frame
Head is for synchronizing, usually one or more ascii characters,；Frame type is defined in communication protocol；Data block is that should send
Communication effective information, the method that verification generallys use single byte distance, cumulative sum.Data-frame sync head is assumed in the present invention
Have 2 bytes (H1, H2), frame Class1 byte (Type), n byte of data block (D1~Dn), 1 byte (C1) of check code, then frame
A length of n+4.
As shown in Fig. 2, the synchronization high performance method functional block diagram of serial communication frame of the invention.It is received including serial data
Module, loop buffer memory module, frame head search module, whole frame check module, frame data preserving module.Loop buffer stores mould
Block storing data length should be not less than 2* (n+4) -1, it is ensured that a complete data frame can be stored in loop buffer.
As shown in Figure 3, Figure 4, Fig. 3 is that the loop buffer memory module in the present invention stores schematic diagram.Fig. 4 is of the invention
Synchronous flow chart.Each communication cycle reads the data received in serial port chip FIFO.And by write pointer by data successively
Loop buffer memory module is written.Loop buffer memory module judges storing data length.When storing data length is big
When being equal to serial communication frame length, triggering frame head search module work.Frame head search module deposits loop buffer memory module
Frame head search is carried out data are stored up from read pointer, compared with frame head first byte, if the byte and frame head first byte are unequal,
Annular buffered memory module is then read, the search of frame head lead-in is continued；If equal, whether storing data length is first determined whether
Whole frame check module work is triggered if length is more than or equal to serial communication frame length more than or equal to serial communication frame length n+4
Make.
Whole frame check module carries out second byte of frame head, frame type, verification to loop buffer memory module storing data
Code is verified.If being verified, carry out whole frame and fall out, frame data preserving module is written in dequeued data；If being verified,
Preceding byte is pseudo- frame head, falls out and works as byte, and continues the search of frame head first byte.The frame data preserving module fallen out receives
New communication data is handled data frame or is executed corresponding life according to command type using message mechanism notice main program
Operation is enabled, carries out data update again when receiving next complete data frame.
It is explained further for two example two below
As shown in Figure 5, it is assumed that certain data frame head is 2 bytes (0xaa, 0x55), and frame type is 1 byte (0x11), data
Block length is 6 bytes, 1 byte of frame check code.
Because whole frame is 10 bytes, to guarantee that loop buffer memory module can store a complete frame data, annular
Buffered memory module storing data length should be not less than 19 bytes.
As shown in Figure 6, it is assumed that read in loop buffer memory module data, contain pseudo- a frame head, a complete frame data
(frame data also contain and frame head identical bytes string).
Data and frame first byte aa of the frame head search module to the read pointer storage of loop buffer memory module storing data
It is compared, if inconsistent, reads annular buffered memory module, continue the comparison of next byte.When finding pseudo- frame
Head aa.Loop buffer memory module storing data length is equal to frame length at this time, triggers whole frame check module work.
Whole frame check module carries out second byte of frame head, frame type, verification to loop buffer memory module storing data
Code is verified, at this time verification failure.
Frame head search module continues frame head search, when the aa byte for finding whole frame.When loop buffer memory module
Storing data length is equal to frame length, triggers whole frame check module work.Whole frame check module deposits loop buffer memory module
Storage data carry out second byte of frame head, frame type, check code and are verified, and verification is correct at this time.Then whole frame is fallen out, this is same
The end of the step.
Embodiment shows: while comparing frame head and frame check code method, can evade in serial communication frame data containing with
Erroneous judgement when the identical data of frame head, it is ensured that synchronous correctness.In addition, this method only uses a small amount of decision logic clear, it can be fast
Speed has effectively achieved the synchronization of serial communication, and program structure is clear, and operand is small can effectively to mitigate processor load,
It is also easy to transplant to other serial communication protocols.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the scope of the invention, all at this
Made any modification within the design of invention, equivalent replacement and improvement etc. should be included in scope of patent protection of the invention
It is interior.
Claims (2)
1. a kind of synchronization system of serial communication frame, which is characterized in that store mould including serial data receiving module, loop buffer
Block, frame head search module, whole frame check module and frame data preserving module；
The serial data receiving module reads the data received in serial port chip FIFO in each communication cycle；And it will count
Loop buffer memory module is sequentially written according to the sequencing according to reading；Loop buffer memory module, to storing data length
Judged；Frame head search module carries out the search of frame head first byte to loop buffer memory module storing data；Whole frame check mould
The verification that block carries out frame type to loop buffer memory module storing data, carries out verification sum to serial communication frame；Frame data are protected
Storing module receives new communication data, using message mechanism notice main program according to command type to data frame carry out processing or
Execute corresponding command operation.
2. the synchronization high performance method based on the synchronization system of a kind of serial communication frame described in claim 1, which is characterized in that packet
Include following steps:
Step 1: serial data receiving module receives the data in serial port chip FIFO in each communication cycle, and is read
It takes；Data are sequentially written in loop buffer memory module according to the sequencing of reading after reading；
Step 2: loop buffer memory module judges storing data length, when storing data length is more than or equal to serial ports
When communication frame length, triggering frame head search module work；When storing data length is less than serial communication frame length, terminate this
It is synchronous；
Step 3: frame head search module carries out the search of frame head first byte to loop buffer memory module storing data, and if frame head
It is inconsistent, then annular buffered memory module is read, frame head search is continued；If consistent, storing data length is first determined whether
More than or equal to serial communication frame length, if length is more than or equal to serial communication frame length, whole frame check module work is triggered；
Step 4: whole frame check module carries out frame type to loop buffer memory module storing data, carries out to serial communication frame
Verify the verification of sum；If verification is correct, carries out whole frame and fall out, frame data preserving module is written in dequeued data；If check errors,
Then preceding byte is pseudo- frame head, falls out and works as byte, and returns to step 3；
Step 5: frame data preserving module receives new communication data, main program is notified using message mechanism, according to order class
Type is handled data frame or is executed corresponding command operation.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111443928A (en) * | 2020-03-24 | 2020-07-24 | 四川众合智控科技有限公司 | Beacon flashing method and system based on serial port communication |
| CN111522759A (en) * | 2020-04-16 | 2020-08-11 | 山东智岩探测科技有限公司 | Device and method for converting multi-path synchronous serial data bus into parallel data bus |
| CN111651256A (en) * | 2020-05-31 | 2020-09-11 | 西安爱生技术集团公司 | Serial communication data synchronization method based on FreeRTOS |
| CN111711609A (en) * | 2020-05-21 | 2020-09-25 | 重庆川仪自动化股份有限公司 | Protocol design method in serial port communication |
| CN111858447A (en) * | 2020-07-13 | 2020-10-30 | 深圳市集贤科技有限公司 | Method for receiving data from serial port and processing data frame |
| CN114372016A (en) * | 2021-12-27 | 2022-04-19 | 安徽大学 | Asynchronous serial communication method based on frame synchronous code plus modulation |
| CN114765528A (en) * | 2021-01-15 | 2022-07-19 | 烽火通信科技股份有限公司 | Frame synchronization method, device, equipment and readable storage medium |
| CN115696446A (en) * | 2022-10-27 | 2023-02-03 | 南京威翔科技有限公司 | Signal transmission method of low-power-consumption fuse device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5832310A (en) * | 1993-12-30 | 1998-11-03 | Unisys Corporation | Serial I/O channel having dependent and synchronous sources of control data and user defined data |
| CN102510323A (en) * | 2011-09-22 | 2012-06-20 | 航天科工惯性技术有限公司 | Frame identifying method for serial data |
| CN104765573A (en) * | 2015-04-10 | 2015-07-08 | 中国船舶重工集团公司第七一0研究所 | Serial communication data processing analysis method |
| CN105681134A (en) * | 2016-03-04 | 2016-06-15 | 西安航天动力技术研究所 | General multiple serial port communication protocol detection and identification method |
| CN107257277A (en) * | 2017-05-11 | 2017-10-17 | 杭州航海仪器有限公司 | The many types of method for control of locking of serial frame synchronization |
-
2019
- 2019-08-23 CN CN201910781026.7A patent/CN110515881A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5832310A (en) * | 1993-12-30 | 1998-11-03 | Unisys Corporation | Serial I/O channel having dependent and synchronous sources of control data and user defined data |
| CN102510323A (en) * | 2011-09-22 | 2012-06-20 | 航天科工惯性技术有限公司 | Frame identifying method for serial data |
| CN104765573A (en) * | 2015-04-10 | 2015-07-08 | 中国船舶重工集团公司第七一0研究所 | Serial communication data processing analysis method |
| CN105681134A (en) * | 2016-03-04 | 2016-06-15 | 西安航天动力技术研究所 | General multiple serial port communication protocol detection and identification method |
| CN107257277A (en) * | 2017-05-11 | 2017-10-17 | 杭州航海仪器有限公司 | The many types of method for control of locking of serial frame synchronization |
Non-Patent Citations (1)
| Title |
|---|
| 张波: "一种适合高速接收机的帧同步方法", 《电视技术》 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111443928A (en) * | 2020-03-24 | 2020-07-24 | 四川众合智控科技有限公司 | Beacon flashing method and system based on serial port communication |
| CN111522759A (en) * | 2020-04-16 | 2020-08-11 | 山东智岩探测科技有限公司 | Device and method for converting multi-path synchronous serial data bus into parallel data bus |
| CN111711609A (en) * | 2020-05-21 | 2020-09-25 | 重庆川仪自动化股份有限公司 | Protocol design method in serial port communication |
| CN111651256A (en) * | 2020-05-31 | 2020-09-11 | 西安爱生技术集团公司 | Serial communication data synchronization method based on FreeRTOS |
| CN111858447A (en) * | 2020-07-13 | 2020-10-30 | 深圳市集贤科技有限公司 | Method for receiving data from serial port and processing data frame |
| CN114765528A (en) * | 2021-01-15 | 2022-07-19 | 烽火通信科技股份有限公司 | Frame synchronization method, device, equipment and readable storage medium |
| CN114765528B (en) * | 2021-01-15 | 2023-09-26 | 烽火通信科技股份有限公司 | Frame synchronization method, device, equipment and readable storage medium |
| CN114372016A (en) * | 2021-12-27 | 2022-04-19 | 安徽大学 | Asynchronous serial communication method based on frame synchronous code plus modulation |
| CN114372016B (en) * | 2021-12-27 | 2023-09-29 | 安徽大学 | Asynchronous serial communication method based on frame synchronization code modulation |
| CN115696446A (en) * | 2022-10-27 | 2023-02-03 | 南京威翔科技有限公司 | Signal transmission method of low-power-consumption fuse device |
| CN115696446B (en) * | 2022-10-27 | 2024-04-16 | 南京威翔科技有限公司 | Signal transmission method of low-power-consumption fuze device |
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