SU1621030A1 - Interrupt device for microprocessor system - Google Patents

Abstract

The invention relates to microprocessor technology and is intended to organize the discipline of priority interruptions in microprocessor systems of control and computing systems. The purpose of the invention is to increase the speed of interrupt processing, the microprocessor system interrupt unit contains a group block of interrupt interrupts, a group of priority interrupt blocks, a decoder, a memory block. interrupt, first h second multiplexers, bus driver, counter, trigger, elements P, IIT. Moreover, the group block of priority interrupts contains the priority encoder, the current priority register, the comparison circuit, the D-trigger and element II, and each priority interrupt block contains the priority ipcr, the D-trigger and the And element. The inaccuracy of the invention consists in increasing the speed of the interrupt device by providing identification of a separate request from an arbitrary number of priority interrupt requests in an interrupt cycle using a microprocessor restart ,, 2 FAS ,. f-ly, 3 silt about

Description

The invention relates to microprocessor technology and is intended to organize the discipline of priority interruptions in microprocessor systems of control and computing systems.

The purpose of the invention is to increase the interrupt processing speed.

FIG. 1 shows a block diagram of the device; Fig 2 is a functional diagram of the group priority interrupt block; in fig. 3 - functional diagram of the group block of priority interrupts.

The microprocessor system interrupt device consists of a group block 1 priority interrupts containing information inputs 1.1.1-b1cN, synchronization input 1.2, first input 1 „3 reset, second input 1.4 reset, output 1„ 5 interrupt request, information outputs 1.6, priority blocks interrupt group 2.1-2..N, contain

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.N.1 reset, inputs 2. 1., NC2 synchronization, outputs 2.1o3-2, N.3 interrupt requests, information outputs 201, .4, decoder 3, 4 memories, interrupts, multiplexer 5, containing output 5.1, multiplexer 6, bus driver 7, counter 8, trigger 9, elements OR 10-12, AND elements 13, t4, groups of address inputs 15, groups of address inputs 16, information outputs 17, inputs 18 for enabling interrupt input 19 synchronization input 20, reception input 21, interrupt acknowledgment input 22, synchronization input 23, write input 24, interrupt request output 25, stroke 26 the reading control, data inputs 2701-270N, when oritetnogo encoder 28, AND gate 29, D-flip-flop 30, the priority encoder 31, the register 32 of the current priority comparing circuit 33, I) - flip-flop 34, AND gate 350

Device inputs 15 and 16 are address inputs for connecting the microprocessor system address bus, device outputs 17 are data inputs for connecting the microprocessor system data bus, device input 18 is an input for connecting the microprocessor system control bus, interrupt signaling signaling in the system, for example, INTE for microprocessor 580, the device input 19 is an input for connecting the microprocessor system control bus bit, For example, a system reset, such as RESET for microprocessor 580, device input 20 represents the microprocessor system control bus clock signal input, for example, t2 for microprocessor 580, device 2 input represents the microprocessor control bus terminal input receiving information from the data bus, e.g., DBIN for microprocessor 580, the device input 22 is a control bus discharge input signaling the confirmation of the interruption, i.e. on the transition of the microprocessor to the interrupt processing cycle, for example, the INTA for the microprocessor 580, input 23

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about 35

40

45

50

55

the device is a control bus discharge input signaling the start of a new microprocessor machine cycle, for example, SYNC for a microprocessor 580, device input 24 is an input for a microprocessor system control bus discharge signal for outputting information to an external device, for example, OUT for microprocessor 580, the device output 25 is an output for switching to the control bus discharge of a microprocessor system that accepts interrupt requests, such as INT for Microprocessor 580

The device works as follows0

In the initial state, all the triggers and registers are reset to device input 19 by a logic signal. Information inputs of the device 27 "1 - 27.N receive combinations of interrupt requests from various external devices requiring service. Moreover, devices connected to block 2 of priority interrupts have higher priority groups having a larger number, and among devices connected to one priority interrupt block; - Devices connected to the input 27, having a larger number. At the outputs of the corresponding priority encoders 28, information about interrupt request codes in blocks 2 priority interrupts of the group that have a higher priority in each of blocks 2, and logical 1 signals, indicating the presence of at least one interrupt request, appears. that according to the synchronization pulse arriving with. the corresponding input of the device to the inputs 2, 1 .2-2.N.2 of the blocks 2 priority interrupts of the group are set to the logical 1 state of the D-flip-flops 30, the D-inputs of which are applied to the logical level 1. Thus, the inputs 1.1- The KN group interrupt priority block receives combinations of group interrupt requests that are perceived by the priority encoder 31, the output of which is the interrupt request code of the highest priority block from the priority interrupt blocks requiring the current service. tu5162

It goes to the first group of information inputs of the comparison circuit 33, where it is compared with the information at the output of the current priority register 32, the outputs of which are connected to the second group of inputs of the comparison circuit 33. Since in the initial state the register 32 is reset, at the output of the comparison circuit 33 a logical 1 signal appears, which enters the input of the element 35, to the other input of which a logical 1 signal is received, indicating that there are interrupt requests. By the sync pulse coming from the corresponding input of the device to the input 1.2 of block 1, a D-flip-flop 34 is set due to the fact that a logical level is applied to its D-input. Thus, the output 1.5 of block 1 is set to a logical 1 signal indicating an interrupt request, I have A higher priority in the priority interrupt block, which, in turn, has a higher priority at the given time. On the leading edge of the pulse at the output of the D flip-flop 34, the priority code at the current time is written to the output block 1.6 at the current priority register 32 1 o

Consequently, at the output 25 of the device, a logical 1 signal is set, and at the address inputs of multiplexer 6, the code of the group 2 priority interrupts of the group, the request for which is received at a given time. The signal at output 25 / of the device is perceived by the microprocessor in the last clock cycle of the current command of a certain background program, and it is overridden into the interrupt processing cycle. In this case, the microprocessor's internal interrupt trigger is reset and the logical 1 signal is removed from the device enable input 18, which results in a logical 1 signal from the output of the element OR 12 to the inputs t.3 of the group block 1 for priority interrupts and the inputs 2.1.1 for blocks 2 for the priority interrupts. The interrupt request triggers 30, 34 are zeroed out and held in the zero state. Interrupts are prohibited by the signals at the input 21 of the receiving device (a logic level of 1 which indicates that

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the microprocessor is in the state of inputting information from the data bus) and the interrupt acknowledgment input 22 (the logic level 1 which indicates that the microprocessor is in the interrupt processing cycle) the trigger 9 is set to the logic

0 1 and the enable signal is applied

To the input, control the bus driver 7, the outputs of which are connected to the data outputs of the device. In the initial position, the outputs of the bus generator 7 are in a high impedance state due to the absence of an active signal level at its control input. Inlet ttnngto shaper 7 are connected to R1 outlets

0 multiplexer 6, which are connected to the outputs of block 1 to 6 of the group block 1 of the priority prerppapps connected to the outputs of the block 9 of the priority interrupt group having the highest

5 priority. Therefore, the pa output of the bus driver 7 sets the information corresponding to the interrupt request code, which has the highest priority in block 2 of the group's priority interrupts, which in turn has the highest priority among the currently required services. The logical 1 signal from the output of the trigger 9 controls the multiplexer

C 5, which in its initial position, when there is an address of a logical signal O at its input, transmits the information to the swap outputs and the second group of address inputs of the interrupt memory unit 4

0 about the state of the part of the address inputs 16 of the device. Moreover, this part is a subset of the address inputs of the device 16 When the address of the first multiplexer 5 signals arrives at the input

5 logic 1 from the output of the trigger 9 to the outputs of the multiplexer 5 is transmitted information from the outputs 106 of the group block 1 priority interrupt. Therefore, the state of the address inputs in the interrupt memory unit 4 is determined both by the state of the part of the device’s address inputs 16 and by the code of the priority interrupt unit 2, which has the highest priority, the request

e to interrupt from which is being executed at the moment.

The logical 1 signal from the output of the trigger 9 is also fed to the second input of the AND 14 element, the first input of which is connected to the second synchronization input 23 of the device, to which the clock signal accompanying each cycle of the microprocessor is applied. Therefore, the counter 8 at its counting input starts counting these synchronization pulses.

The microprocessor perceives the interrupt vector coming from the output of the bus driver (the bits of the bus driver 7 corresponding to bits 7, 6, 0, 1, 2 of the RST1Idddl11 command are connected via a limiting resistor to the + 5V bus from the power supply), and addresses the first interrupt processing command whose address depends not only on the interrupt vector, but also on the code of the preemptive interrupt block that generated this interrupt vector. Therefore, an interrupt processing command will be read from block 4 of the interrupt memory corresponding to the given highest priority interrupt request, without additional program processing. This command is read from the interrupt memory block 4 after the active level is supplied to the control input 26 of the interrupt memory block 4 of the device to which, for example, a chip sample signal from the microprocessor system decoder is fed, and after the signal 21 logical 1, indicating the receipt of information on the microprocessor data bus. When a command is read, the outputs of the bus driver 7 are transferred to the high-impedance state, since from the input 22 the interrupt signals confirm the active signal level due to the fact that the microprocessor executes the command sampling cycle from the memory of the interrupt cycle by the value of the restart command.

The first interrupt-handling command is, for example, an unconditional branch instruction to the memory area where a specific interrupt processing program is written. After such a transition is completed, the counter 8 nullifies and the pulse from its overflow output, which enters the input of the element OR 11, zeroes the trigger 9. The multiplexer 5 is disconnected from the outputs 1-6 of the group block 1 priority interrupts and re-connected to the part of the address lines of the address inputs 16 devices that represent the possibility of its addressing by address lines 16 when executing, for example, an interrupt program.

By executing a specific interrupt processing program, the microprocessor necessarily writes to the stack the contents of the general purpose and status registers, and then resolves the interrupts with a special command, which allows multilevel interrupts, if after performing these operations a service request is received from priority block 2 interrupts having a higher priority than the one whose request is being serviced, again on a synchronization pulse coming from the input 20 of the device to the input 1.2 of the group block and 1 priority interrupt, D-flip-flop 34 is set. This will happen because after programmatically enabling interrupts, a logical 1 signal will be present at device input 18 again, which will remove the active signal level from zeroing inputs 1 of the 3V trigger and 34 and 2 signals 1 -20N ID-flip-flops 30 "D-flip-flop 30 will be installed in the priority interrupt block with a higher priority, which will cause a code change at the output of the priority encoder 31, and, since this code will be greater than the code recorded in register 32, logical 1 output signal e comparison schemes 33.

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Thus, the next program interruption will occur, regardless of the degree of completion of the previous one.

The proposed device provides for the storage of interrupt requests in the trigger-flags of devices that cause an interrupt on inputs 27.1-2.N. These flags remain set until the completion of the interrupt handler program from this device and are wrapped by a microprocessor using technical means of this external device, for example, output ports with addresses corresponding to external devices. The output signals of the decoders of these output ports activate the zero outputs of the trigger fl ov fl o

Upon completion of the interrupt processing program, the microprocessor resets the checkbox of the device that caused the interruption using technical means belonging to this external device5, which results in the removal of the interruption request from the corresponding inputs 27.1-27.N.

The microprocessor accesses the decoder 3 in the same way as the output device using the second address inputs of the device 15, which can be combined with the first address inputs 16 of the device, and the input 24, resulting in the appearance of a signal of logical 1 at the output of the decoder 3. When This logical 1 signal goes to the first inputs of the OR 10 element, and its output goes to input 1 4 of group block 1 of priority interrupts, which leads to resetting the register 32 “Group bpo 1 of priority interrupts is ready to accept the next priority the interrupt request. Before performing the above operations of zeroing flags and register 32 of the current priority, it is necessary to prohibit interrupts programmatically, after which the subroutine returns,

In case of interruption of the interrupt processing program by a request to interrupt a higher priority after completion of processing a request of a higher priority, the processing of the interruption request of the previous priority will start again from the first command of the interrupt processing program, if during this time no requests have been received for interrupting a higher priority. It is undesirable that then this program does not provide for an interrupt authorization command until the end of the program.

Thus, the proposed device identifies the address of the first command of an individual interrupt request in the mode of vector interrupts using the microprocessor restart in the interrupt cycle without additional program processing.

Consider an example of a specific implementation of the proposed device for operation as part of a microprocessor system based on microprocessor 580 for 14 levels of interruption.

ten

15

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We use two blocks 2.1 and 2.2 priority interrupts with priority encoders 31, 28 for 7 inputs. The signal width of the register 32 logj. Ј 30 Outputs of blocks 2.1 and 252 of priority interrupts are connected to the first 1.1.1 and second 1.1.2 inputs of group block 1 of priority interrupts. On the remaining inputs give signals logical O.

The restart command (RST) of microprocessor 580 has the form 11ddd111Ј "Then the following interrupt vectors will correspond to 14 interrupt levels:

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04 Oe

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06 0 g

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Thus, one interrupt vector corresponds to two interrupt levels. To identify an interrupt request by one interrupt vector that determines the address of the first interrupt processing command, it would be necessary to provide commands for entering information from the outputs 1.6 of the group priority interrupt block that encodes the number block of priority interrupts from blocks 2.1-2.2, and using this information, determine the address of the first command of the processing program of a particular two interrupts,

20

25

thirty

35

In the proposed device, the code at the output 1.6 of the priority interrupt block 001 Ј encodes interrupt requests 1-7, and the code 010 encodes requests 8-14. Thus, the sixth bit of the microprocessor address is connected to the first input of the multiplexer 5, and the second bit of the KB code is connected to its second input, and the signal from the logical 1 output of the trigger 9 will determine the state of the second address inputs of the interrupt memory block 4 the second bit of code 1i6 of the preemption block. Then, in block 4 of the interrupt memory, the initial interrupt handling commands must be placed at the following addresses (for example, the width of the address lines of the memory block is 8):

010 | - first processing team

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7 8 9

10 11 12 13 14

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1708 After the microprocessor enters the interrupt cycle, the interrupt memory block 4 will be addressed by the bus lines of the address of the device 16 address inputs and by the output 501 of the first multiplexer 5c. Add the commands-calls to the interrupt service routines 1-14, which are out of addresses 010g-170g. block 4 interrupt memory. Therefore, after these command calls have been made, it is necessary to reset trigger 9 in order to switch the first multiplexer 5 so that when executing the interrupt handling routines it is possible to address block 4 of the interrupt memory by address inputs 16. Therefore, the conversion factor of counter 8 should be equal to the number of cycles (the number of sync pulses on the microprocessor's sync output connected to the input 23 of the device) of writing to the stack when executing the RST command (2 cycles) plus the number of cycles of the CALL command (subroutine call) 3 „

Thus, the conversion factor of the counter 8 is equal to 5, and after the fifth pulse, the first multiplexer 5 is switched.

Suppose interruption requests have been received for the first and second inputs 27. 1 about 1-27.1.2 of block 2.1 of priority interrupts and for the third input 27-203 of block 202 of priority interrupts Then the output 2.1.4 of block 2.1 of priority interrupts will set the interrupt request code 010is a at the output 2.-2P4 block 2.2. priority interrupt - code 011. Since block 2, .2 priority interrupt has a higher priority than block 2.1, then in register 32 when requesting an interrupt a count will be written

i 010 (second block). Therefore, after the interrupt cycle, a restart command is issued on the RST 110111112 command. A command from the 130 ° cell will be selected that identifies the priority request 0113 from the priority interrupt block having priority 0102 without the additional program for searching the block number JQ

Claims (2)

Invention Formula 10 Microprocessor interrupt device with a processor system containing a group block of priority interrupts, a group of blocks of priority interrupts and a decoder, the information inputs of priority blocks, interrupts form a group of information inputs of the device, synchronization inputs of a group block of priority interrupts and blocks of priority interrupts of a volume group 25 the dinenes are the first synchronization input of the device, the inputs of the decoder are the first group of address inputs of the device, characterized in that, with the purpose OQ of interrupt processing speed, an interrupt memory block, first and second multiplexers, bus driver, counter, trigger, first, second and third elements OR, first and second elements AND, the information outputs of the priority interrupt blocks of the group are connected to the device control inputs of the second multiplexer, the address inputs of which are connected to the information outputs of the group block of priority interrupts, the outputs of which are connected to the information inputs of the bus driver, in stroke shaper bus is a data output device outputs the interrupt request block priority interrupt groups are connected to the data inputs of the group priority unit 50 interrupts, the interrupt request output of a group priority interrupt block is the output of device interrupt requests, the first group of address inputs of the interrupt memory block 55 and the first group of information inputs the first multiplexer are, respectively, the first and second subgroups of the group of address inputs of the device 40 45 13 The second group of information inputs of the first multiplexer is connected to the group of information outputs of the priority interrupt group block, and the group of outputs of the first multiplexer is connected to the second group of address inputs of the interrupt memory block, the first enable input of the interrupt memory block is the receive input of the device, and the second The interrupt memory enable input is the read control input of the device whose outputs are information outputs of the device, the output of the decoder gating is the recording entry of the device, the output of the decoder is connected to the first input of the first OR element, the second input of which is connected to the first inputs of the second and third OR elements, is the device reset input, the output of the first OR element is connected to the second input of the priority group interrupts reset, the first inlet reset of which is connected to the output of the third element OR and to the reset inputs of the priority interrupt blocks of the group, the second input of the third element OR is the input to enable the device to break through, the first The first and second inputs of the first element I are, respectively, the inputs for receiving and confirming the interrupt of the device, the output of the first element I is connected to the enable input of the bus driver and to the input of the trigger setup, the output of which is connected to the address input of the first multiplexer and to the perlon input of the second element I, second the input of which is the second input of synchronization / device of the device, and the output of the second element I is connected to the counting input of the counter, the reset input of which is connected to the input input of the device, and the output of which is for prison to the second input of the second OR gate, the output of the second OR element connected to WMO / dy reset trigger. 2, a device according to claim 1, wherein the group block of priority interrupts contains a priority encoder, a current priority register, a comparison circuit, a D flip-flop and an AND element, the information inputs of the priority cipher 1621030 14 0 five 0 five 0 0 five Toors are informational inputs of the priority interrupt group block, the information encoder of the priority encoder is connected to the information input of the current priority register and to the first input of the comparison circuit, the output of the current priority register is connected to the second input of the comparison circuit and is the information output of the group block of priority interrupts, the output of the comparison circuit is connected to the first input of the AND element, the second input of which is connected to the signal output of the priority encoder, the third input of the element This is the synchronization input of the group preemptive interrupt unit, the output of the And element is connected to the D-flip-flop synchronization input, the information input of which is connected to the bus of the logical unit of the device, the D-flip-flop output is the interrupt request output of the group preemptive interrupt and connected to the sync input the current priority register, the D-flip-flop input is the first reset input of the group block of priority interrupts, and the current priority register reset input is the second input reset unit group priority interrupts, 3, the Device in PP. 1 and 2, characterized in that each group's priority interrupt block contains a priority encoder, a D-trigger and an AND element, the information inputs of the priority encoder are information inputs of the priority interrupt block, the information outputs of the priority encoder are information outputs of the priority interrupt block, the signal the output of the priority encoder is connected to the first input of the AND element, the second input of which is the synchronization input of the group priority interrupt block, and the output of The input AND is connected to the D-flip-flop synchronization input, the information input of which is connected to the bus of the logical unit of the device, the L-flip-flop output is the group preemptive interrupt request interrupt request output, and the D-tringer reset input is the group preemptive reset input. FIG. one. x 27/7 282 27.12 " at mi 2.1.2 28 28.1 21.1 2.Shch 0 2.7.3 29 thirty 2.7 (2 2 Z.N) FIG. 2