WO2001001338A1 - Procede pour la transmission de donnees et la gestion de memoire, et support de donnees correspondant - Google Patents

Procede pour la transmission de donnees et la gestion de memoire, et support de donnees correspondant Download PDF

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Publication number
WO2001001338A1
WO2001001338A1 PCT/EP2000/005797 EP0005797W WO0101338A1 WO 2001001338 A1 WO2001001338 A1 WO 2001001338A1 EP 0005797 W EP0005797 W EP 0005797W WO 0101338 A1 WO0101338 A1 WO 0101338A1
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WO
WIPO (PCT)
Prior art keywords
data
memory
buffer memory
processor unit
data blocks
Prior art date
Application number
PCT/EP2000/005797
Other languages
German (de)
English (en)
Inventor
Thomas Stocker
Original Assignee
Giesecke & Devrient Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Giesecke & Devrient Gmbh filed Critical Giesecke & Devrient Gmbh
Priority to AU58185/00A priority Critical patent/AU5818500A/en
Publication of WO2001001338A1 publication Critical patent/WO2001001338A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Definitions

  • the invention is based on a method according to the type of the main claim.
  • Methods of this type are known in connection with portable data carriers in the form of chip cards provided with a microcontroller, so-called “smart cards”, for example from W. Rankl, W. Effing: “Handbuch der Chip Actually”, Carl Hanser Verlag, 2nd edition 1996 and are used in various forms in an increasing number of application areas.
  • Chip cards which consist of a card carrier made of plastic and into which an integrated semiconductor circuit and a contact field for making electrical connections with a corresponding reading device are embedded are particularly widespread.
  • contactless signal transmission methods are also increasingly being used.
  • Portable data carriers should therefore not only be standard chip cards currently used, but rather all current and future transportable objects in which a microcontroller is embedded in order to enable a user to perform chip card-typical interactions with corresponding interaction stations provided for this purpose ,
  • APDU application protocol data units
  • This term denotes internationally standardized data units of layer 7 in the OSI model, ie the application layer widespread transmission protocols used by the application layer transmit certain "transmission protocol data units"("Transmission Protocol Data U it", TPDU) using serial transmission techniques, for example according to ISO / IEC 7816-3 or ISO / IEC 10536-4.
  • TPDU Transmission Protocol Data U it
  • serial transmission techniques for example according to ISO / IEC 7816-3 or ISO / IEC 10536-4.
  • chip cards have a non-volatile memory designed as an EEPROM for persistent data objects and a memory designed as a RAM, which is very small compared to the EEPROM for volatile data objects. Since the main part of the data is in the EEPROM, it has to be accessed frequently. Write access to EEPROM memory in particular, however, has the disadvantage of being time-consuming in comparison to pure arithmetic operations of the chip card microcontroller; an EEPROM write operation typically takes a few milliseconds. If larger amounts of data are to be processed on a chip card, this can lead to processing times which are unacceptable in view of the speed of reaction normally required for chip cards.
  • From DE 196 26 337 AI is in for a processor card with a fast first memory in the form of RAM in terms of write access and a second non-volatile memory slow in write access Shape of an EEPROM known a method for handling long messages. Messages arriving on the card should first be written into the fast RAM memory until it is filled or until at least one destination address valid for the EEPROM memory has been recognized. If further message parts subsequently arrive, the content of the RAM memory and the subsequent message parts are transferred to a buffer area in the EEPROM memory. To increase the data throughput, it is proposed to replace copying processes in the EEPROM by renaming. However, the measure only applies if the data itself is not changed.
  • No. 5,715,431 describes a concept for securing data contained in an EEPROM of a chip card against disturbances when they occur during a write operation.
  • the data to be overwritten are stored in a security buffer in the
  • This task is solved by the method specified in the independent claims 1, 2 and 10 for setting up a transmission / reception operation and by the data carrier specified in the independent claims 6 and 13.
  • the methods according to claims 1, 2 and 10 are characterized in that typical data processing operations for portable data carriers, which each access the slow non-volatile memory, are not carried out individually with immediate execution of the slow accesses, but first several successive operations are collected and then run together as a block.
  • the method according to claims 1 and 2 enables a faster data exchange with an external terminal through a more efficient use of APDUs, and thus above all enables an increased data throughput to the outside, the method according to claim 10 through a more efficient write access to an EEPROM memory, in particular one increased data throughput within a portable data carrier.
  • Fig. 4 shows a transmit / receive operation when using a
  • Fig. 1 shows the structure of a chip card 1, which is used in the following as a form of training for the data carrier.
  • a central processor unit 2 which, in conjunction with suitable microcontroller software, produces the functionality of the chip card 1.
  • the processor unit 2 is assigned a first memory device 4, 5, which is divided into two areas and is typically designed as a RAM and enables short access times.
  • the first area 4 contains an APDU buffer 10 which serves as a transmission buffer memory;
  • the second area 5 contains a cache buffer 20 which functions as an input / output buffer and is directly assigned to a data transmission device 3.
  • the cache buffer 20 is dimensioned in such a way that the sequence of the data carrier programs or card applications which access the cache buffer 20 is ensured.
  • the data carrier programs for their part are designed to be interoperable in such a way that they can run on cards from different manufacturers, regardless of the details of the respective card structure. For this reason, in practice, most data carrier programs do not fully utilize the cache buffer 20.
  • the card 1 exchanges data with an external device 9, for example a terminal for payment transactions, via the data transmission device 3.
  • the data transmission device 3 reads data blocks to be sent from the cache buffer 20, in the reception mode it stores received data blocks therein.
  • Details on the implementation of chip cards 1, in particular a representation of the structure of customary APDUs and customary bit-serial data transmission devices, are, for example, from the aforementioned publication W. Rankl, W. Effing: "Manual of chip cards", 2nd edition, pp. 155 to 215, removable, to which reference is made here in this regard.
  • FIG. 2 illustrates a first variant of a transmit / receive operation for a chip card 1 equipped as described above using a schematic representation of the APDU buffer 10 and the cache buffer 20 in successive operating states, a data block 10a, 10b, 10c being generated in each operating state has been.
  • Each data block 10a, 10b, 10c represents the result of an operation carried out by the processor unit 2 to achieve the next operating state in each case and, in addition to hatched data, contains administrative information 40, for example so-called headers.
  • User data such as administrative information can have different and varying amounts and each occupy a varying part of the APDU buffer 10; As a rule, the APDU buffer 10 is not completely occupied by the data blocks 10a, 10b, 10c.
  • the APDU buffer 10 which serves as the transmission buffer memory area, is used in transmission mode to provide data blocks 10a, 10b, 10c that are generated and to be transmitted by the processor unit 2 in an operating state.
  • the data transmission device 3 copies the data blocks 10a, 10b, 10c provided in succession in the APDU buffer 10 in each operating state, while maintaining their sequence, in the cache buffer 20, so that the APDU buffer 10 of the processor unit 2 again quickly receives the next data block is available.
  • the administrative information 40 associated with each data block 10a, 10b, 10c is no longer required and is removed. A number of data blocks 10a, 10b, 10c dependent on the data carrier program can thus be collected in the cache buffer 20.
  • the copying of data blocks 10a, 10b, 10c provided after each operating state from the APDU buffer 10 into the cache buffer 20 continues until the cache buffer 20 is filled or until a data carrier program executed by the processor unit 2 completes the execution of a data Transmission process requires. Only on this occasion does the data transmission device 3 cause the entire contents of the cache buffer, ie all data blocks 10a, 10b, 10c previously collected in the cache buffer 20, to be transmitted to the terminal 9 as a data train. For the transmission, the data transmission device 3 generates management information which is coordinated with the terminal 9 and which it attaches to the data train.
  • the data transmission device 3 In the receiving mode, the data transmission device 3 initially stores, independently of one another, data blocks received from the terminal 9 in the cache buffer 20. In doing so, it removes the management information transmitted with the data blocks. On a certain occasion, in particular when the capacity of the cache buffer 20 is exhausted, it copies the data blocks collected in the cache buffer 20 one by one, while maintaining their sequence, into the APDU buffer 10, from where they the processor unit 2 each immediately removed and processed. When copying, the data transmission device 3 again provides the data blocks with management information tailored to the processor unit 2. The processor unit 2 can thus receive several fillings of the APDU buffer 10 one after the other without having to wait each time for the completion of a bit-serial data transmission sequence between chip card 1 and terminal 9.
  • the data blocks 10a, 10b, 10c collected in the cache buffer 20 do not necessarily have to belong to a single data carrier program. This can also result from several data carrier programs executed simultaneously or quasi simultaneously.
  • the removal of the management information from data blocks 10a, 10b, 10c when storing them in the cache buffer 20 and adding them again when removing them from the cache buffer 20 can be used to convert a protocol used within the chip card 1 to one for communication used with the outside world. Different communication mechanisms can be used for different data carrier programs within the card. Different protocols can also be used externally, for example depending on the terminal in question.
  • APDU buffers 10 can be set up, which are assigned to different data carrier programs.
  • a single cache buffer 20 is sufficient, which is used alternately in the receive mode and in the transmit mode. If communication with a terminal 9 is to take place in full duplex operation, i.e. Chip card 1 and terminal 9 each send and receive simultaneously, two cache buffers 20 are expediently provided. The first cache buffer is used for transmit mode, the second for receive mode. The transmission / reception operation can then be carried out in the two cache buffers as described above.
  • FIG. 3 shows a second variant of a send / receive operation using a schematic representation of a cache buffer 120 and of an APDU.
  • Buffers 110 in three successive operating states HOa, 110b, HOc.
  • the cache buffer 120 is directly accessible to a data transmission device 3 for exchanging data blocks with an external chip card terminal 9.
  • the APDU buffer which serves as the transmission buffer memory area, is used in transmit mode to provide data blocks generated and to be sent by the processor unit 2, in the receive mode to receive received ones and for processing by the processor unit 2 certain data blocks.
  • the function of these components corresponds to that in the embodiment variant shown in FIG. 1.
  • the arrangement shown in FIG. 3 differs from that shown in FIG. 1 in that the APDU buffer and the cache buffer are implemented as a uniform, contiguous address area in the RAM of the chip card.
  • the memory areas of the APDU buffer and the cache buffer overlap in such a way that the APDU buffer 110 forms the upper part 125 of the entire buffer memory 120 and the cache buffer the non-overlapped part 135.
  • APDUs to be copied in succession from different operating states 110a, 110b, 110c of the APDU buffer HO are now copied into the upper part 125 of the cache buffer, with the management information 140 being eliminated.
  • a shift operation is then carried out, by means of which the content of the upper part 125 is shifted into the non-overlapped memory area 135 while maintaining its data sequence.
  • FIG. 4 shows an embodiment of the invention in the case of a chip card, the memory device of which comprises a first memory device in the form of a RAM memory with a write cache area 210 set therein and a second memory device 30 in the form of an EEPROM memory. Furthermore, a processor device for processing write accesses to the EEPROM memory 30 is provided, which can be implemented, for example, in the form of a chip card microcontroller controlled by a suitable program.
  • the EEPROM memory 30 Since a write access to the EEPROM memory 30 takes a few milliseconds, the EEPROM memory 30 represents a memory which is slow in terms of write access compared to a RAM memory on which write accesses can be carried out. According to the invention, write accesses become the EEPROM memory 30 is therefore not executed immediately. Instead, a plurality of data elements in the EEPROM memory 30, which contains the data elements 211a, 211b, 211c to be written, are first copied into the write cache area 210 one after the other. All subsequent write and likewise all read accesses to the plurality of data elements copied into the write cache memory area 210 are then carried out in the write cache memory area 210, ie in the fast RAM memory.
  • EEPROM memories 30 are generally divided by at least one memory area boundary into contiguous memory areas 30a, 30b, 30c, 30d, 30e, 30f, 30g, 30h, which are called “pages”.
  • a write access to the content of such pages 30a, 30b, 30c, 30d, 30e, 30f, 30g in EEPROM 30 generally affects the entire page 30a, 30b, 30c, 30d, 30e, as a result of the usual technical memory implementation.
  • the control device is therefore expediently set up in such a way that it interprets a page 30a, 30b, 30c, 30d, 30e, 30f, 30g referenced by data elements 211a, 211b, 211c to be written or read as a plurality of data elements and copied into the write cache memory area 210 , If another page 30a, 30b, 30c, 30d, 30e, 30f, 30g is subsequently referenced by data elements to be written or read, that is, the page boundary of the page 30a, 30b, 30c, 30c, 30d, 30e, 30f last copied into the write cache memory area 210 , 30g, the control device generates a special control command which, in a single write operation, causes the content of the page 30a, 30b, 30c, 30d, 30e, 30f, 30g, 30e, 30f, 30g still referenced in the EEPROM 30 initially in the EEPROM 30 updated from the content of the write cache area 210 and then the newly referenced page 30a
  • a special control command which causes the corresponding page 30a, 30b, 30c, 30d, 30e, 30f, 30g in the EEPROM 30 to be updated in a corresponding manner in the write cache area 210, can also be triggered in another way. This can be triggered, for example, by the execution of certain program commands, such as the issuing of status signals, which acknowledge that a status has been reached.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

L'invention concerne un support de données approprié pour effectuer un échange de données avec un terminal externe (9). Afin d'accélérer l'échange de données, il dispose d'une mémoire tampon d'entrée/sortie (20) à laquelle une unité de transmission de données (3) a directement accès. Cette dernière (3) extrait de la mémoire tampon (20) les blocs de données à envoyer et stocke dans ladite mémoire tampon les blocs de données reçus. Ce support de données présente également au moins une mémoire tampon de transmission (10) servant à mettre à disposition ou à recevoir au moins un bloc de données à envoyer ou à recevoir. L'invention vise à d'accroître le débit de données à l'intérieur du support de données, lorsque ce dernier dispose d'une première mémoire (4) à accès d'écriture longs, et d'une deuxième mémoire (5) à accès d'écriture rapides. A cet effet, une zone de mémoire cache d'écriture, dans laquelle sont collectés tout d'abord les éléments de données à écrire dans la première mémoire lente (4), est créée dans la deuxième mémoire rapide. Après réception d'une instruction de commande, le contenu de la mémoire lente (4) est mis à jour en fonction du contenu de la zone de mémoire cache d'écriture, au cours d'un seul accès d'écriture.
PCT/EP2000/005797 1999-06-24 2000-06-23 Procede pour la transmission de donnees et la gestion de memoire, et support de donnees correspondant WO2001001338A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU58185/00A AU5818500A (en) 1999-06-24 2000-06-23 Data transfer and memory management method and data carrier

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19928939.5 1999-06-24
DE19928939A DE19928939A1 (de) 1999-06-24 1999-06-24 Datenträger sowie Verfahren zur Datenübertragung und zur Speicherverwaltung

Publications (1)

Publication Number Publication Date
WO2001001338A1 true WO2001001338A1 (fr) 2001-01-04

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AU (1) AU5818500A (fr)
DE (1) DE19928939A1 (fr)
WO (1) WO2001001338A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1244078A1 (fr) * 2001-03-23 2002-09-25 PROTON WORLD INTERNATIONAL en abrégé PWI Procédé de mise à jour d'un document électronique
GB2397408A (en) * 2003-01-15 2004-07-21 Agilent Technologies Inc EEPROM emulation in an optical transceiver
CN100423025C (zh) * 2001-10-10 2008-10-01 雅斯拓股份有限公司 智能卡中字节传输的管理
US7636769B2 (en) 2006-04-14 2009-12-22 Microsoft Corporation Managing network response buffering behavior

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2242880T3 (es) 2001-09-26 2005-11-16 Siemens Aktiengesellschaft Procedimiento para el procesamiento de conjuntos de datos consistentes.
DE102006058511B4 (de) * 2006-12-12 2021-07-08 Giesecke+Devrient Mobile Security Gmbh Verfahren zum Empfangen von Nachrichten durch einen portablen Datenträger und portabler Datenträger
DE102006058512B4 (de) * 2006-12-12 2021-07-22 Giesecke+Devrient Mobile Security Gmbh Verfahren zum Empfangen einer Nachricht in einem tragbaren Datenträger und tragbarer Datenträger
DE102007011638A1 (de) * 2007-03-09 2008-09-11 Giesecke & Devrient Gmbh Verfahren zum Einschreiben von Daten in einen Speicher eines tragbaren Datenträgers

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US5200600A (en) * 1988-08-29 1993-04-06 Hitachi Maxell, Ltd. IC card and method for writing information therein
US5864588A (en) * 1995-12-20 1999-01-26 Mitsubishi Electric Semiconductor Software Co., Ltd. Communications device
WO1999021120A1 (fr) * 1997-10-17 1999-04-29 Intermec Ip Corp Etiquette electronique comprenant un modem r.f. destinee a surveiller la performance d'un vehicule a moteur avec filtre

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JPH05250523A (ja) * 1992-03-06 1993-09-28 Toshiba Corp 処理方式
DE69334149T2 (de) * 1992-04-02 2008-02-14 Kabushiki Kaisha Toshiba, Kawasaki Speicherkarte
GB9307623D0 (en) * 1993-04-13 1993-06-02 Jonhig Ltd Data writing to eeprom
EP0811204B1 (fr) * 1995-07-05 1999-09-22 International Business Machines Corporation Traitement de longues informations dans une carte a puce

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200600A (en) * 1988-08-29 1993-04-06 Hitachi Maxell, Ltd. IC card and method for writing information therein
US5864588A (en) * 1995-12-20 1999-01-26 Mitsubishi Electric Semiconductor Software Co., Ltd. Communications device
WO1999021120A1 (fr) * 1997-10-17 1999-04-29 Intermec Ip Corp Etiquette electronique comprenant un modem r.f. destinee a surveiller la performance d'un vehicule a moteur avec filtre

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1244078A1 (fr) * 2001-03-23 2002-09-25 PROTON WORLD INTERNATIONAL en abrégé PWI Procédé de mise à jour d'un document électronique
CN100423025C (zh) * 2001-10-10 2008-10-01 雅斯拓股份有限公司 智能卡中字节传输的管理
GB2397408A (en) * 2003-01-15 2004-07-21 Agilent Technologies Inc EEPROM emulation in an optical transceiver
GB2397408B (en) * 2003-01-15 2005-11-16 Agilent Technologies Inc Transceiver
US7107414B2 (en) 2003-01-15 2006-09-12 Avago Technologies Fiber Ip (Singapore) Ptd. Ltd. EEPROM emulation in a transceiver
US7636769B2 (en) 2006-04-14 2009-12-22 Microsoft Corporation Managing network response buffering behavior

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Publication number Publication date
AU5818500A (en) 2001-01-31
DE19928939A1 (de) 2001-01-11

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