EP0565866B1 - Dispositif de circuit à haute densité d'intégration - Google Patents

Dispositif de circuit à haute densité d'intégration Download PDF

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Publication number
EP0565866B1
EP0565866B1 EP93103944A EP93103944A EP0565866B1 EP 0565866 B1 EP0565866 B1 EP 0565866B1 EP 93103944 A EP93103944 A EP 93103944A EP 93103944 A EP93103944 A EP 93103944A EP 0565866 B1 EP0565866 B1 EP 0565866B1
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EP
European Patent Office
Prior art keywords
function block
terminal
signal
integrated circuit
boundary scanning
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EP93103944A
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German (de)
English (en)
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EP0565866A3 (fr
EP0565866A2 (fr
Inventor
Masahiko c/o NEC Corporation Shoda
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NEC Corp
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NEC Corp
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods

Definitions

  • the present invention relates generally to a large-scale integrated circuit device (hereafter referred to as LSI). More specifically, the invention relates to a LSI including a serial bus function for externally performing setting and changing internal functions through a serial bus and a boundary scanning function for performing checking of wiring after installation on a circuit board.
  • LSI large-scale integrated circuit device
  • LSIs incorporating the boundary scanning function as standardized by IEEE 1149.1. Such LSIs permits identification of a faulty portion by checking soldering failure, pattern failure, functions of the LSI per se by the boundary scanning function after installation on the circuit board.
  • Fig. 7 is a schematic block diagram of the LSI having the serial bus function.
  • a serial/parallel converter 101 converts a serial data (SID) 109 externally input as an internal coefficient into a parallel data 110.
  • the parallel data becomes an input for a plurality of registers 106 and 107 .
  • a register selector 105 generates a selection control signal 116 and 117 for determining the register to store the parallel data 110.
  • the data (internal coefficient) 118 stored in one of the registers 106 and 107 is set in a LSI function block 1.
  • An address decoder 102 judges whether a main address is the address of the LSI per se when the parallel data 110 is a main address signal.
  • a matching signal 111 becomes active and is outputted to a state controller 103.
  • the state controller 103 uses the matching signal 111 and a bus busy signal (SIB) 112 and a clock signal (SIK) 113 as inputs, and generates an enabling signal 115 for enabling the register selector 105 in synchronism with the clock signal 113 when both of the matching signal 111 and the bus busy signal 112 are active.
  • SIB bus busy signal
  • SIK clock signal
  • a sub-address decoder 104 generates a selection signal for selecting one of a plurality of registers 106 and 107 through checking of a sub-address when the parallel data 110 is a sub-address signal, and outputs the sub-address signal to the register selector 105.
  • the register selector 105 generates the above-mentioned selection control signal 116 and 117 on the basis of the selection signal 114 and the enabling signal 115 .
  • Fig. 8 shows a timing chart illustrating an operation of the serial bus function. It should be noted, the right side end of each signal above the broken line is continued to the left side end of the corresponding signal.
  • the serial bus function initiates operation.
  • the serial data 109 in synchronism with the clock signal 113 is converted into the parallel data 110 by the serial/parallel converter 101.
  • the parallel data 110 for main addresses A7 ⁇ A0 as illustration in Fig. 8 is checked whether it is the address of the LSI per se or not by the address decoder 102 . If the address is that of the LSI per se , the matching signal 111 becomes active. Then, the state controller 103 recognizes that the input signal on the data 109 input subsequently to the main address A7 - A0 is for its own data to make the enabling signal 115 active for enabling the register selector 105.
  • the register selector 105 Based on the signal designated by the sub-address, the register selector 105 generates the selection control signal 116, 117 for selecting the register. At this time, the serial data D7 ⁇ D0 on the data 109 is stored in the selected register through serial/parallel conversion and thus the operation of the LSI function block is designated by the data (designation signal) 118 .
  • a TAP controller 201 generates various signals 215, 216, 224 and 225 for controlling the boundary scanning function depending upon the state of a test mode signal (TMS) 213 which varies in synchronism with a test clock 214.
  • TMS test mode signal
  • a test data (TDI) 212 is input as a serial data and output as a test data output (TDO) 227 based on operating conditions designated by the TAP controller 201 through the following three paths.
  • the first path is a path established through input/output cells 207, 208 provided between the LSI function block 1 and signal input/output, serial lines 219, 222, 226 to the test data output 227.
  • the second path is a path established through a by-pass 205, serial lines 220, 222, 226 to the test data output 227.
  • the third path is a path established through an instruction register 202, serial lines 223, 226 to the test data output 227 .
  • Multiplexers 209 and 210 are adapted to select these three paths depending upon control signals 221 and 224.
  • a buffer 211 is adapted to lead the output 226 of the multiplexer 210 to the test data output 227 depending upon a control signal 225.
  • an instruction decoder 203 decodes an instruction 217 from the instruction register 206 to generate a control signal 218 for a boundary register portion 204 and a control signal 221 for the multiplexer 209. Resistors 228 and 229 pull up the test data input 212 and the test mode signal 213, respectively.
  • Fig. 10 Operation of the boundary scanning function is illustrated in Fig. 10 in a form of operational timing chart.
  • Fig. 10 the right side ends of the respective signal illustrated above the broken line are continued to the left side ends of the corresponding signals illustrated below the broken line.
  • Data IR of the test data input 212 is fed to the instruction register 202 in synchronism with the clock signal 214.
  • TAP controller 201 generates an instruction register control signal 216 for controlling to write the instruction set by the data IR in the instruction register 202.
  • the instruction 217 written in the instruction register 202 is output to the instruction decoder 203.
  • the instruction decoder 203 outputs the control signal 218 to the boundary register portion 204 according to a timing signal 215 from the TAP controller 201.
  • the data DR on the test data input 212 is shifted to the input cell 207 and the output cell 208 in order.
  • the multiplexers 209 and 210 are selected by the selection signals 221 and 224 as the outputs of the instruction decoder 203 and the TAP controller 201.
  • the buffer 211 determines whether the test data output 227 is activated based on the enabling signal 225 of the TAP controller 201.
  • the important functions in this boundary scanning function are those in the input/out cells 207 and 208.
  • the input/output cells 207 and 208 are provided between the LSI function block 1 and input/output pins (not shown) and are provided functions for controlling output data and sampling input data for detecting solder failure, pattern breakage on the circuit board.
  • test data input 212 the test data input 212
  • test mode select signal 213 the test clock signal 216
  • test data output 227 the test data output 227
  • EP-A-0111053 describes level sensitive scan design strings on an integrated circuit chip which are employed from multiple functions of providing control parameters to logic blocks on the chip and for providing reconfiguration messages to the reconfiguration logic on the chip, in addition to a normal function of transferring test data to various portions of the chip.
  • EP-A-0111053 nor EP-A-0230219 contain a boundary scanning function block or a serial bus function block.
  • Fig. 1 is a block diagram showing the first embodiment of a large-scale integrated circuit device (LSI) according to the invention.
  • the LSI is composed of a LSI function block 1 having an original LSI circuit function, a boundary scanning function block 2 and a serial bus function block 3 . These three blocks are integrated. An input signal 4 and an output signal 5 are provided for the LSI function block 1 .
  • the boundary scanning function block 2 has the construction the same as that illustrated in Fig. 9 and has a boundary scanning function standardized by the provision of IEEE 1149.1 for identification of a faulty portion by checking soldering failure, pattern breakage, erroneous installation.
  • the boundary scanning function block 2 controls input/output cells in the LSI function block 1 with a cell output signal 12 as an output to the input/output cells and a cell input signal 13 as an input from the input/output cells.
  • the serial bus function block 3 includes D-type flip-flop (D-FF) 119 and inverters 120 and 121 in addition to the construction illustrated in Fig. 7 set forth above, and is provided with a function for setting and changing coefficient for arithmetic circuit in the LSI function block, filter coefficient and so forth through a control signal 14.
  • D-FF D-type flip-flop
  • a clock terminal 8 (corresponding to the clock terminal 113 in Fig. 7 and the test clock terminal 214 in Fig. 9 ) is employed in common to both blocks 2 and 3 for receiving a clock signal.
  • a data terminal 7 (corresponding to the serial data terminal 109 in Fig. 7 and the test data input terminal 212 in Fig. 9 ) is employed in common to both blocks 2 and 3 for receiving data signals.
  • a control terminal 6 (corresponding to the bus busy terminal 112 of Fig. 7 and the test mode select terminal 213 of Fig. 9 ) is employed in common for both clocks 2 and 3 for receiving control signals as operation designating signals.
  • the control terminal 6 is pulled up by a pull-up resistor 31, serves as a test mode select terminal 10 (corresponding to TMS 213 of Fig. 9 ) of the boundary scanning function block 2 through an OR gate 33 and is directly connected to the bus busy terminal (corresponding to SIB 112 of Fig. 7 ) of the serial bus block 3.
  • the data terminal 7 pulled up by a pull-up resistor 32 serves as a test mode input terminal (corresponding to the TDI 212 of Fig. 9 ) for the boundary scanning function block 2 and also serves as the serial data terminal (corresponding to SID 109 of Fig. 7 ) for the serial bus function block 3.
  • the clock terminal 8 serves as a test clock terminal (corresponding to the TCK 214 of Fig. 9 ) for the boundary scanning function block 2 and serves as a clock terminal (corresponding to SIK 113 of Fig. 7 ) for the serial bus function block 3.
  • a boundary scanning function block enabling control signal 9 is generated in the serial bus block 3, which is supplied to an OR gate 33 as one input.
  • a serial bus block freezing signal 15 is generated in the boundary scanning function block 2 and input to the serial bus function block 3.
  • a reset signal 15 generated as one of a control signal group 216 by the TAP controller 201 (the same as the TAP controller 201 of Fig. 9 ) is used.
  • the content of the control signal group 216 of the TAP (Test Access Port) controller 201 is defined in IEEE 1149.1, and illustrated in Fig. 2.
  • the reset signal 15 is adapted to be switched from HIGH level to LOW level while the test mode select signal (TMS) 6 is maintained at HIGH level for the period corresponding to five test clocks TCK 8 (214) and whereby switch the state of the boundary scanning function block 2 from the enabled state to the reset state.
  • TMS test mode select signal
  • This reset signal is also used as the serial bus function block freezing (SB freezing) signal 15.
  • Fig. 3 shows a block diagram showing the additional portion of the serial bus function block 3 which is added to the circuit of Fig. 7.
  • the SB freezing signal 15 from the boundary scanning function block 2 serves as a decode inhibit signal for an address decoder 102 via an inverter 120.
  • the SB freezing signal 15 serves as a data input for the D-FF 119.
  • the address decoder 102 turns a decoding output 122 into HIGH level when a specific address, such as (000000000) of a parallel address 110 of a serial/parallel converter 101 and supplies the HIGH level decoding output to the reset input of the D-FF 119 via an inverter 121.
  • the Q output of this D-FF 119 becomes the input for the OR gate 33 of Fig. 1 as the boundary scanning function block enabling control signal (BS control signal).
  • the clock 214 (8) is applied to the clock input of the D-FF 119.
  • Fig. 4 is a timing chart showing operation of the circuit of Figs. 1 ⁇ 3 .
  • the clock is applied to the clock terminal 8 .
  • Both of the data terminal 7 and the control terminal 6 are controlled into HIGH level.
  • the reset signal 15 of the TAP controller 201 in the boundary scanning function block 2 becomes LOW level.
  • the boundary scanning function block 2 is reset and falls into the disabled state. Since this reset signal is also used as the SB freezing signal 15, the address decoder 102 is enabled via the inverter 120 as illustrated in Fig. 3 and turns the data input of the D-FF 119 input HIGH level to output HIGH level Q output 9. Then, HIGH level is output at the Q output 9. Therefore, the boundary scanning function block enabling control signal (BS control signal) 9 becomes HIGH level so that subsequent variation of the test mode select signal 6 will not be transmitted to the boundary scanning function block 2 via the OR gate 33.
  • BS control signal boundary scanning function block enabling control signal
  • the boundary scanning function block 2 is reset and thus held in the disabled state, and conversely, the serial bus function block 3 is in the enabled state. This condition is shown at a time t 0 in Fig. 4 .
  • the data signal at the data terminal 7 becomes (000000000)
  • the data signal is detected by the address decoder 102 in the enabled state.
  • the address decoder 102 outputs HIGH level decoding output 122 to reset the D-FF 119.
  • the boundary scanning function block enabling control signal (BS control signal) becomes LOW level (time t 1 ) to permit input of the test mode select signal (TMS) 6 to the boundary scanning function block 2 via the OR gate 33.
  • TAP controller 201 Fig.
  • the boundary scanning function block 2 initiate operation according to the input of the test mode select signal (TMS) 6 to perform the function of the boundary scanning function block 2, such as applying the test data from the test data input (TDI) 7 and outputting the data from the test data output (TDO) 11.
  • TMS test mode select signal
  • the reset signal 15 of the TAP controller 201 is switched from HIGH level to LOW level (time t 3 ) to disable the boundary scanning function block 2 by resetting. Since this reset signal serves as SB freezing signal 15, the address decoder 102 is enabled through the inverter 120 in Fig. 3 and the data input of the D-FF 119 becomes HIGH level to make the level of the Q output thereof HIGH. Accordingly, the boundary scanning function enabling control signal (BS control signal) becomes HIGH level (time t 4 ) so that the subsequent variation of the test mode select signal 6 will never been transmitted to the boundary scanning function block 2 via the OR gate 33. Namely, after time t 4 , the boundary scanning function block 2 is held in the disabled state by resetting, and the serial bus function block 3 is held in the enabled state to perform serial bus function.
  • BS control signal boundary scanning function enabling control signal
  • Fig. 5 shows an example of circuit as application of the preferred embodiment of the LSI according to the invention.
  • two LSIs (as represented by 18A and 18B ) are controlled by a controller 19 .
  • the serial bus/boundary scanning controller 19 generate a test data output (TDO) 24 and a serial data (SID) 23 to apply them as two inputs for a two-input AND gate 35A , and to apply the serial data (SID) 23 as one input of a two-input AND gate 35B.
  • TDO test data output
  • SID serial data
  • Respective outputs 7A and 7B of the AND gates 35A and 35B are connected to data terminals SID (TDI) of the LSIs 18A and 18B .
  • the controller 19 generates the bus busy signal (SIB)/test mode select signal (TMS) to apply then to respective control terminals 6A and 6B of LSIs 18A and 18B .
  • the controller 19 further generates the clock (SIK)/test clock (TCK) to apply to respective clock terminals 8A and 8B of the LSIs 18A and 18B .
  • test data output (TDO) 11A of the LSI 18A serves as another input of the AND gate 35B.
  • the test data output (TDO) 11B of the LSI 18B serves as the test data input (TDI) for the controller 19.
  • the reference numerals 34A, 34B, 36 denotes pull-up resistors.
  • the controller 19 Upon turning ON of power supply, the controller 19 makes the test mode select signal (bus busy signal) 6A and 6B HIGH level and maintains the HIGH level for a period corresponding to five clocks 8A and 8B . Thereafter, the boundary scanning function blocks 2 in the LSIs 18A and 18B are reset the functions and placed in the disabled condition. Then, the serial bus function blocks 3 are enabled to perform the serial bus control. At this time, all test data outputs (TDO) 24, 11A, 11B are held HIGH level by the pull-up resistors 34A, 34B and 36.
  • TDO test data outputs
  • the controller 19 can generate the serial data (SID) 23 for supplying to respective data terminals 7A and 7B of respective LSIs 18A and 18B, or enable the boundary scanning function by outputting (000000000) to the main address for enabling the boundary scanning function block 2 and disabling the serial bus function block 3.
  • SID serial data
  • Fig. 6 is a block diagram illustrating the second embodiment of the large-scale integrated circuit device according to the present invention. Like reference numerals to Fig. 1 represent the like element.
  • the boundary scanning function block enabling control signal 9 and the serial bus function block freezing (SB freezing) signal 15 are omitted, and in place, an external select signal 16 is added.
  • the select signal 16 is input to the OR gate 33 via an inverter 37.
  • the select signal 16 and the serial bus busy signal (SIB) 6 become two inputs of an OR gate 38.
  • the output 17 of the OR gate 38 serves as the serial bus busy signal (SIB) for the serial bus function block 3.
  • the test mode select input 10 of the boundary scanning function block 2 is constantly held HIGh level by the effect of the inverter 37 and the OR gate 33. Therefore, the boundary scanning function block 2 is held in reset and disabled state. Since the bus busy signal 6 is input to the serial bus function block 3 as the signal 17 via the OR gate 38, the serial bus function block 3 initiates operation.
  • the select signal 16 becomes HIGH level
  • the bus busy signal 6 becomes HIGH level by the OR gate 38. Therefore, the bus busy signal 17 for the serial bus function block 3 becomes HIGH level so that the serial bus function block 3 terminates its operation.
  • the test mode select signal (TMS) 6 appears on the output 10 of the OR gate 33 so that the boundary scanning function block 2 initiates the operation.
  • the LSI in the first and second embodiments set forth above, various modification should be obvious to those skilled in the art.
  • the foregoing circuit may be modified to make at least one set of terminals in common among three sets of terminals.
  • the terminals required for the serial bus function and the boundary scanning function are made in common, it can minimize the number of additional terminals in addition to the terminals for the original function of the LSI per se . Therefore, it becomes possible to eliminate increasing of the size of the LSI package.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Claims (8)

  1. Circuit intégré à haute densité d'intégration comprenant :
    un bloc de fonction de circuit intégré (1) présentant une fonction de circuit d'origine en tant que circuit intégré ;
    un bloc de fonction de bus série (3) destiné à fixer et à modifier une fonction interne du bloc de fonction de circuit intégré (1), ledit bloc de fonction de bus série (3) incluant une borne de signal d'horloge (113) destinée à recevoir un signal d'horloge, une borne de bus occupé (112) recevant un signal série de bus occupé en tant que signal de désignation de fonctionnement, et une borne de données série (109) recevant des données série ;
    un bloc de fonction de balayage de frontière (2) destiné à vérifier un câblage du bloc de fonction de circuit intégré (1) après installation sur une carte imprimée, ledit bloc de fonction de balayage de frontière (2) incluant une borne de signal d'horloge (214) recevant un signal d'horloge, une borne de choix de mode d'essai (213) destinée à recevoir un signal de choix de mode d'essai en tant que signal de désignation de fonctionnement et une borne de données d'essai (212) destinée à recevoir des données d'essai ;
       caractérisé en ce que
    le circuit intégré à haute densité d'intégration comprend en outre :
    une première borne commune (6) qui est commune à la borne de bus occupé (112) et à la borne de choix de mode d'essai (213) ;
    une deuxième borne commune (7) qui est commune à la borne de données série (109) et à la borne de données d'essai (212) ;
    une borne de choix (16) destinée à recevoir un signal de choix dans le but d'activer sélectivement l'un dudit bloc de fonction de bus série (3) et dudit bloc de fonction de balayage de frontière (2) ;
    des premiers moyens formant porte (33) destinés à bloquer la délivrance du signal de bus série occupé délivré à ladite première borne commune (6) audit bloc de fonction de balayage de frontière (2) lorsque ledit signal de choix active ledit bloc de fonction série ; et
    des seconds moyens formant porte (38) destinés à bloquer la délivrance du signal de choix de mode d'essai délivré à ladite première borne commune (6) audit bloc de fonction de bus série (3) lorsque ledit signal de choix active ledit bloc de fonction de balayage de frontière (2) ;
       dans lequel chacun desdits premier et second moyens formant portes (33, 38) est commandé respectivement par l'un des signaux complémentaires du signal de choix.
  2. Dispositif de circuit intégré à haute densité d'intégration selon la revendication 1, comprenant en outre une troisième borne commune (8) qui est parallèle à des bornes de signaux d'horloge communes audit bloc de fonction de bus série (3) et audit bloc de fonction de balayage de frontière (2).
  3. Circuit intégré à haute densité d'intégration comprenant :
    un bloc de fonction de circuit intégré (1) présentant une fonction de circuit d'origine en tant que circuit intégré ;
    un bloc de fonction de bus série (3) destiné à fixer et à modifier une fonction interne du bloc de fonction de circuit intégré (1), ledit bloc de fonction de bus série (3) incluant une borne de signal d'horloge (113) destinée à recevoir un signal d'horloge, une borne de bus occupé (112) recevant un signal série de bus occupé en tant que signal de désignation de fonctionnement, et une borne de données série (109) recevant des données série ;
    un bloc de fonction de balayage de frontière (2) destiné à vérifier un câblage du bloc de fonction de circuit intégré (1) après installation sur une carte imprimée, ledit bloc de fonction de balayage de frontière (2) incluant une borne de signal d'horloge (214) recevant un signal d'horloge, une borne de choix de mode d'essai (213) destinée à recevoir un signal de choix de mode d'essai en tant que signal de désignation de fonctionnement, et une borne de données d'essai (212) destinée à recevoir des données d'essai ;
       caractérisé en ce que
    le circuit intégré à haute densité d'intégration comprend en outre :
    une première borne commune (6) qui est commune à une borne de bus occupé (112) et à la borne de choix de mode d'essai (213) ;
    une deuxième borne commune (7) qui est commune à la borne de données série (109) et à la borne de données d'essai (212) ;
    des moyens formant porte (33) destinés à délivrer un signal appliqué à ladite première borne commune (6) audit bloc de fonction de balayage de frontière (2) en réponse à un signal de porte ;
    des moyens de détection d'adresse (10), prévus dans ledit bloc de fonction de bus série (3), destinés à détecter un signal délivré à ladite deuxième borne commune (7) représentant un motif d'adresse spécifique pour générer ledit signal de porte, tandis que ledit bloc de fonction de balayage de frontière (2) est désactivé ;
    des moyens d'exécution de commande (119, 33), sensibles à une sortie de détection desdits moyens de détection d'adresse (102), destinés à rendre actif un signal délivré par ladite borne commune (6) audit bloc de fonction de balayage de frontière (2) ; et
    des moyens de commande d'activation (201), prévus dans ledit bloc de fonction de balayage de frontière (2) et sensibles à un signal délivré par lesdits moyens formant porte (33), destinés à activer la fonction de balayage de frontière et à désactiver la fonction de bus série.
  4. Dispositif de circuit intégré à haute densité d'intégration selon la revendication 3, comprenant en outre une troisième borne commune (8) en parallèle avec des bornes de signaux d'horloge communes audit bloc de fonction de bus série (3) et audit bloc de fonction de balayage de frontière (2).
  5. Dispositif de circuit intégré à haute densité d'intégration selon la revendication 3, dans lequel lesdits moyens de commande d'activation (201) génèrent un signal d'activation (216) destiné à activer ladite fonction de balayage de frontière en réponse au signal délivré par lesdits moyens formant porte (33).
  6. Dispositif de circuit intégré à haute densité d'intégration selon la revendication 5, dans lequel ledit bloc de fonction de bus série (3) inclut des moyens (120) destinés à désactiver ladite fonction de détection desdits moyens de détection d'adresse (10) en réponse audit signal d'activation (216).
  7. Dispositif de circuit intégré à haute densité d'intégration selon la revendication 5, dans lequel lesdits moyens de commande d'activation (201) génèrent un signal de désactivation destiné à désactiver ladite fonction de balayage de frontière lorsqu'un signal appliqué à ladite première borne commune (6), via lesdits moyens formant porte (33), est maintenu pendant une période de temps prédéterminée.
  8. Dispositif de circuit intégré à haute densité d'intégration selon la revendication 5, dans lequel lesdits moyens d'exécution de commande (119, 33) comprennent une bascule de type D prélevant ledit signal d'activation en tant qu'entrée de données et ladite sortie de détection desdits moyens de détection d'adresse (102) en tant qu'entrée de restauration, et une porte OU (33) prélevant la sortie de ladite bascule de type D en tant qu'entrée et le signal appliqué à ladite première borne commune (6) de ladite première paire en tant qu'autre entrée.
EP93103944A 1992-03-19 1993-03-11 Dispositif de circuit à haute densité d'intégration Expired - Lifetime EP0565866B1 (fr)

Applications Claiming Priority (3)

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JP63929/92 1992-03-19
JP6392992 1992-03-19
JP6392992 1992-03-19

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EP0565866A2 EP0565866A2 (fr) 1993-10-20
EP0565866A3 EP0565866A3 (fr) 1997-11-05
EP0565866B1 true EP0565866B1 (fr) 2002-01-02

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EP (1) EP0565866B1 (fr)
KR (1) KR970011582B1 (fr)
DE (1) DE69331404T2 (fr)

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Publication number Priority date Publication date Assignee Title
US5377199A (en) * 1993-06-30 1994-12-27 Intel Corporation Boundary test scheme for an intelligent device
JP3333036B2 (ja) * 1994-03-17 2002-10-07 富士通株式会社 試験装置、試験装置を備えたシステムおよび試験方法
JP2671817B2 (ja) * 1994-08-26 1997-11-05 日本電気株式会社 半導体集積回路の検査方法
US6804725B1 (en) * 1996-08-30 2004-10-12 Texas Instruments Incorporated IC with state machine controlled linking module
KR100413763B1 (ko) * 2001-07-13 2003-12-31 삼성전자주식회사 탭드 코아 선택회로를 구비하는 반도체 집적회로

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Publication number Priority date Publication date Assignee Title
US4488259A (en) * 1982-10-29 1984-12-11 Ibm Corporation On chip monitor
NL8502476A (nl) * 1985-09-11 1987-04-01 Philips Nv Werkwijze voor het testen van dragers met meerdere digitaal-werkende geintegreerde schakelingen, drager voorzien van zulke schakelingen, geintegreerde schakeling geschikt voor het aanbrengen op zo'n drager, en testinrichting voor het testen van zulke dragers.
JPS62164140A (ja) * 1986-01-14 1987-07-20 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション デ−タ処理システムの試験方法
JPH0683291B2 (ja) * 1988-02-12 1994-10-19 日本電気株式会社 シリアル通信方式
US5225772A (en) * 1990-09-05 1993-07-06 Schlumberger Technologies, Inc. Automatic test equipment system using pin slice architecture
US5130988A (en) * 1990-09-17 1992-07-14 Northern Telecom Limited Software verification by fault insertion
US5198759A (en) * 1990-11-27 1993-03-30 Alcatel N.V. Test apparatus and method for testing digital system

Also Published As

Publication number Publication date
KR930020652A (ko) 1993-10-20
DE69331404D1 (de) 2002-02-07
EP0565866A3 (fr) 1997-11-05
KR970011582B1 (ko) 1997-07-12
US5341380A (en) 1994-08-23
DE69331404T2 (de) 2002-08-29
EP0565866A2 (fr) 1993-10-20

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