EP0548917B1 - Circuit de conversion de fréquence d'échantillonnage pour données d'image - Google Patents

Circuit de conversion de fréquence d'échantillonnage pour données d'image Download PDF

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Publication number
EP0548917B1
EP0548917B1 EP92121804A EP92121804A EP0548917B1 EP 0548917 B1 EP0548917 B1 EP 0548917B1 EP 92121804 A EP92121804 A EP 92121804A EP 92121804 A EP92121804 A EP 92121804A EP 0548917 B1 EP0548917 B1 EP 0548917B1
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Prior art keywords
filter
memory
converter
coefficient
pixel values
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German (de)
English (en)
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EP0548917A1 (fr
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Jeffrey A. c/o EASTMAN KODAK COMPANY Small
John J. C/O Eastman Kodak Co. Uebelacker
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Eastman Kodak Co
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Eastman Kodak Co
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00—Geometric image transformations in the plane of the image
    • G06T3/40—Scaling of whole images or parts thereof, e.g. expanding or contracting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing

Definitions

  • the present invention is directed to a sample rate converter for image data which is compact and low in cost and, more particularly, to a converter that directly converts a pixel stream to a different sample rate either higher or lower by filtering during which weights or filter coefficient are applied to pixels in the pixel stream using coefficient tables that are selected responsive to the desired conversion ratio.
  • the reduction and magnification can be performed by interpolating the pixel data.
  • One method of interpolating the pixel image data is to perform sample rate conversion in the direction of an image line.
  • the sample rate conversion is performed by oversampling a line of pixels H pixels in length by some integer factor N. Oversampling consists of inserting (N-1) additional pixels of value zero between every pixel in the input image line, resulting in a stream of NxH upsampled pixels.
  • a convolutional filter is positioned at the beginning of the stream of upsampled pixels and used to sample the resulting stream of pixels to give a single output pixel.
  • a convolutional filter generally consists of weighing values which are used in taking a weighted sum of the pixel stream, starting with the pixel which is under the first weighing value and continuing until there are no more weighing values.
  • the convolutional filter is shifted forward in the stream of upsampled pixels by M pixels where M is the downsampling rate, and the next output pixel is then produced. The process is repeated until the filter no longer overlaps the upsampled pixel stream.
  • the number of output pixels is then equal to N/M times the number of input pixels.
  • One way to implement this method in hardware is to pass a stream of input data through a shift register 2 whose length is equal to the filter length, L. After each input pixel is shifted in, (N-1) zero values must be shifted in to accomplish the upsampling. Then, the output from each stage of the shift register 2 must pass through a corresponding one of a group 4 of multipliers to be multiplied by the corresponding filter weight from a corresponding one of a group of storages to storing the weights.
  • the document relates to a monolithic ⁇ A/D and D/A converter with filter for broadband speech coding.
  • Both ADC and DAC are implemented with oversampling second-order ⁇ converters, reducing the demands on analog anti-aliasing and anti-imaging filters.
  • Decimation and interpolation are achieved in 2 and 4 stages , respectively, using linear-phase FIR filters for stability and waveform reproduction.
  • a 160th order lowpass FIR filter is implemented in distributed-arithmetic style, with precomputed sums of coefficients stored in a ROM. The appropriate sums are selected by the binary input stream and accumulated to yield a result every 32 sample periods.
  • the second decimation filter and the first three interpolation filters are realized with a microprogrammed convolution processor.
  • the convover structure takes advantage of the symmetric impulse response of the linear-phase FIR filters using two sample-data RAMs with separate address-generation units as delay lines, and adding their outputs before the multiply-accumulate step, thereby reducing the necessary multiplications by half.
  • the filter coefficients are supplied by a cyclically addressed ROM, which also provides the microcode controlling the operations in the digital part. The redefinition of the ROM contents allows the same hardware to be used for other applications, as up to 4 filters with up to 256 coefficients can be programmed in microcode. Attention is further drawn to US-A-4792975 wich relates to digital speech signal processing for pitch change with jump control in accordance with pitch period.
  • a sample rate converter that produces a converted pixel stream by filtering.
  • the converter stores a pixel stream in a data memory and during conversion pointers are used to select the pixels which are multiplied by filter coefficients and accumulated.
  • the multiplication is performed by a lookup table that stores the results of the pixel-coefficient multiplication for all combinations of pixel values and coefficients for each sample rate conversion that the converter will perform.
  • the output of the lookup table is controlled by the pixel data, the coefficient selected and the table selected.
  • the accumulated output is the filtered image data.
  • the sample rate converter 28 of the present invention is designed as a finite impulse response filter which is particularly designed to perform one of three possible sample rate conversions responsive to a rate conversion selection by a user.
  • the filter coefficients and how they were derived is described in U.S. application 809,365 entitled Storage and Retrieval of Digital Photographic Images by Axman, Barry, Mathieu, Timmermans and Richards and having Kodak Docket No. 60,092 incorporated by reference herein.
  • the converter 30 particularly directly implements the following equations without upsampling and zero stuffing.
  • the present invention 28 as illustrated in Fig. 3, has four major sections, a data memory 30 (a random access memory) which stores the incoming pixel data in a wrap around arrangement in which later pixels write over pixels that have been previously processed, a multiplier 32 which multiplies the filter coefficients of the selected equation times the corresponding pixels and an accumulator 33 which accumulates the filtered pixel output.
  • the accumulator 33 includes a multiplier 34 and a storage register 35 comprising D-flip flops.
  • the pixel data is selected and the multiplication is performed under the control of a control section 36 which includes a control unit 37 which increments counter 38 and register 40 which, along with a multiplexer 42 controlled by the control unit 37, select what pixel data or value to multiply.
  • the control unit 37 controls the coefficient being multiplied by a counter 44 whose output maps through a map unit 46.
  • the control unit 37 is controlled by registers 48-54 which specify the length of the image line being processed, the filter length and filter being used, the upsampling rate and the down sampling rate.
  • Fig. 3 allows the sample rate conversion to be done directly, that is, rather than by intermediate steps of upsampling (zero stuffing) and downsampling (zero processing). In particular, no processing time or hardware is used for the writing, reading or processing of the zeros which would be introduced by the intermediate step of upsampling.
  • the jth subset is equal to [k j , k N+j , k 2N+j , ..., k nN+j ], where n is an integer incremented from 0 until (nN+j) is greater than (filter length-1), N is the upsampling rate and j is an integer from zero to (N-1). This eliminates those weights for upsampled pixels which would correspond to inserted zeros.
  • N the effective upsampling rate
  • M the effective downsampling rate
  • the period and the order in which the subsets of weights must be applied as new input pixels become available may be determined by constructing a diagram similar to Fig. 1 for the desired values of N and M. Then the output pixels may be written in terms of the weighted sums, from which the order of the subsets of weights may be directly determined.
  • a control unit such as unit 37, the operation of which is described in more detail in Fig. 5, may be designed for any such N and M which will select the proper subsets of weight for appropriate segments of input pixels.
  • the control unit 37 determines when there is sufficient information to calculate the next output pixel, selects the proper subset of weights, and directs the calculation of the appropriate weighted sums.
  • the order in which these subsets are applied to segments of the input pixel stream are controlled by the control unit 37 and several small counters 38 and 40 and a register 44 as shown in Fig. 3.
  • the control unit 37 controls three pointers, P1, P2 and P3, which are all initialized to zero at the start of each line of input pixels.
  • P1 and P2 point to the data memory RAM 30 while P3 points to a table of filter coefficients.
  • the control unit 37 writes it into the RAM 30 at the location pointed to by P1 and then increments P1 by one.
  • the accumulator 33 is reset, then the value (pixel) pointed to by P2 in RAM 30 is read out and multiplied by the weight pointed to by P3 and added in the accumulator 33. P2 and P3 are then each incremented by one, the new memory location (pixel) in RAM 30 pointed to by P2 is then read out and the pixel is multiplied by the weight that P3 now points to, and the result is added to the accumulator 33. This process continues until the pointer P3 would be incremented past the last weight of the selected subset. The resulting "DATA OUT" value in the accumulator 33 is then clocked out by means of the "DATA CLK" line. As subsequent input pixels become available, the above process is repeated, generating a stream of output pixels until no more pixels are available from the input line of pixels.
  • a look up table of weights stored in a memory and a hardware multiplier can provide the weights and perform the multiplication.
  • This method may require more clock cycles than the approach shown in Figs. 1 and 2, because it is processing data serially rather than in parallel.
  • a line length of H the following number of RAM 30 accesses is required:
  • the weight multiplication rather than being performed by a combination of a memory and a hardware multiplier is preferably performed via a look-up table stored in a RAM or ROM (Read Only Memory) type of memory 32, as shown in Fig. 3.
  • a portion of the memory address is the pointer P3, which serves to select a particular area of the memory which corresponds to a particular weight, and another portion of the address is the pixel value (multiplicand) to be multiplied.
  • the portion of the memory 32 which corresponds to a particular weight consists of a look-up table whose entries are the product of the selected weight with the multiplicand value that is applied to the remaining address lines.
  • additional address lines are preferably included to select different sets of weights since the present invention is designed to implement different filters for different sample rate conversions. If only a single conversion rate is to be implemented the address lines for the map (table) select are not necessary and the size of the memory 32 is correspondingly smaller. Also, the configuration of Fig. 3 is easy to change for different line lengths, sampling ratios and filter lengths, as the pertinent parameters are stored in easily accessed registers, and the weights can be easily changed by either changing the memory (by writing or by physical replacement) or by selecting different banks within the memory. In the embodiment of Fig. 3, different banks (different conversion rates) are chosen using additional address lines (SRC Table Select) while several sets of different parameters are selectable by means of several register bits. The details and requirements for memory 32 will be discussed in more detail with respect to Fig. 4.
  • a small RAM 30 may be used when P1 is designed to "wrap around” when it is incremented past the last location in the RAM 30.
  • This RAM 30 must contain at least as many memory locations as there are weights in the filter.
  • the RAM size is subtracted from the pointer P1. In practice, the subtraction is never actually performed because the pointer length (the highest count of counter 38) is chosen to match the number of available addresses and the pointer P1 wraps around by default (or it is reset to zero) when an attempt is made to increment it past the last address of the RAM. P2 also behaves in this fashion.
  • the size of the weight table (and the size of the weight times pixel table stored in memory 32) may be further reduced by passing P3 through a mapping process or mapping unit 46 as shown in Fig. 3, so that values of P3 which correspond to identical weights map to the same address in the weight table.
  • the pointer P3 would be mapped so as to access these in the order: [k 0 , k 2 , k 4 , k 4 , k 2 , k 0 ] or [k 1 , k 3 , k 5 , k 3 , k 1 .
  • the reduction in the number of weights is especially advantageous.
  • mapping unit 46 which performs the conversion of the count in pointer counter 44 into the appropriate coefficient selection, is depicted in the truth tables set forth below.
  • the mapping unit 46 can be implemented as a look-up table in a memory, such as a ROM, in which the address inputs are map select, subset select and pointer 3 count and the output is coefficient address bits. For example, if the results of the multiplication of coefficient k1 times all possible pixel values are stored in a memory at addresses 0100 to 01FF (as shown in Fig. 4 to be discussed in detail later) the output of the ROM would be "1" when coefficient K1 is specified by the control unit 37 as the subset selection value. Correspondingly, if the k5 coefficient (weight) value is specified the coefficient output by the mapping ROM would be "5" allowing addresses 0500 to 05FF to be addressed.
  • a memory such as a ROM
  • mapping unit 46 could also be hardwired decode logic produced by a person of ordinary skill in the art from the look up tables 1-3 using a logic design tool such as Idea Station from Mentor Graphics.
  • the memory map of a look-up table used to perform the multiplication for the three different filters as set forth in equations 1-3 and which takes advantage of this symmetry and the address scheme is shown in Fig. 4.
  • the memory address includes two table or map select bits 70 which select the conversion ratio implemented, three coefficient or weight select bits 72 allowing up to eight coefficients or weights and eight bits 74 equalling the pixel value being multiplied.
  • the content of memory 32 is divided into three tables 76, 78 and 80 corresponding to the particular conversion rate. Each of the tables is divided into sections 82-92 where each section is a table corresponding to the values of one of the coefficients times all possible pixel values.
  • section 86 includes all the output values for the coefficient k2 times all possible pixel values.
  • each section occupies 256 eight bit bytes. Note the sections corresponding to coefficients k6 and k7, the 4 to 3 conversion, are not shown since that table 80 is not being shown in detail in Fig. 4.
  • the control unit 37 can be a conventional microprocessor with appropriate program and data storage or the unit 37 can be hardwired circuits which includes conventional counters, registers, comparators, adders and control logic, for example, a state machine. Hardwired circuits are preferably used when the invention is implemented as part of an integrated circuit since the space required for the hardwired circuits is less than that for a microprocessor.
  • Fig. 5 illustrates the operations performed by the control unit 37 from which a person of ordinary skill in the art can program a microprocessor or design the hardwired circuits.
  • the control unit 37 exits from a wait or idle state and resets 92 or sets to zero the count in counters 38 and 44 and the count in register 40, loads the conversion ratio map or table selected value as designated by the contents of register 50 and sets the coefficient subset select value indicating what coefficient is to be processed to zero.
  • the subset select value can be contained in a counter or in a register the contents of which can be incremented and the map select value can also be stored in a register.
  • the contents of registers A, B, D and E which will be discussed in more detail later, are reset to zero.
  • the unit 37 determines 94 whether the acknowledge (ACK) line is clear, sends 96 a request (REQ) when it is clear, waits unit ACK is again active and releases 100 REQ.
  • the sequence of steps 94, 96, 98 and 100 are the conventional hand shaking that occurs when a new pixel value is available for processing.
  • the converter 28 is ready to begin processing a pixel value of the input pixel stream.
  • the first step is to set the address select line of the multiplexer 42 to select 102 counter 38.
  • the write line to RAM 30 is then pulsed 104 causing the first pixel value to be written into the first location of RAM 30.
  • Next counter 38 is incremented 106 and the count stored in register E is incremented.
  • the register E count counts the number of pixels input, so that the operation of the converter 28 can be suspended when all the pixels of the line have been input.
  • the contents of register D is also incremented 110 by the upsampling rate N.
  • Register D stores a value used to determine when enough pixel values have been input to produce an output pixel.
  • Register D is incremented by N each time that a new input pixel is written into RAM 30.
  • the contents of register D are determined 112 to exceed the down sample rate M the contents of register D are decremented by M and the process of calculating the next output pixel is performed. Otherwise the number of input pixels stored in register E is tested 114 against the line length to determine whether to stop 116. If the end of the line of pixels has not been reached the handshaking operation occurs again and another input pixel value is stored.
  • pointer 2 is selected 117 by the multiplexer 42, the contents of register D are updated 118, the contents of accumulator 33 are reset 120 and the contents of register B are set 122 to zero.
  • Register B stores the count of how many weights or coefficients within a particular subset of weights have been used.
  • Register A is loaded 124 with the value of pointer 2 stored in register 40.
  • the accumulator 33 is then clocked 126 accumulating the result of the multiplication.
  • Register 40 and counter 44 are then incremented (+1) 128 pointing to the next pixel value and coefficient to multiply.
  • the coefficient count in register B is incremented 130 and the coefficient count is tested 132 to determine whether all weights have been processed and an output pixel value can be produced. If so, the data clock is pulsed 134.
  • the value in pointer counter 40 is then updated 136.
  • C is a value which is added to the old pointer value stored in register A to determine the next value of pointer 2. This "slides" the next subset of weights to properly align with the input pixel stream to calculate the next output pixel value.
  • the C input can be produced from a look-up table stored in a ROM which has inputs of Map Select (i.e. sample rate conversion selection) and Subset Select lines. Next the subset select value is incremented (+1) 138 to point at the next set of coefficients. When this operation is finished, the control unit 37 increments 110 register D and continues as previously discussed.
  • the present invention results in much less hardware being required even when using discrete VLSI parts such as multipliers, adders and memory to perform a sample rate conversion.
  • the circuit of the present invention is more flexible than the prior art, allowing the same set of hardware to perform different sample rate conversions, where parameters such as line length, filter length, sampling ratios, and filter weights may all be easily changed by writing new values to the various registers and/or memory shown in Fig. 3 without requiring reconfiguration of the hardware.

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Claims (8)

  1. Convertisseur de fréquence d'échantillons (28), comprenant :
    a) un moyen de mémorisation (30) pour mémoriser des données en entrée à une première fréquence d'échantillonnage ;
    b) des moyens de filtre pour filtrer directement les données en entrée afin de produire des données en sortie à une seconde fréquence d'échantillonnage, dans lequel ledit moyen de filtre comprend :
       une mémoire de multiplication (32) reliée audit moyen de mémoire (30) mémorisant toutes les combinaisons des valeurs de pixel que multiplient les coefficients de filtre pour chaque fréquence de conversion d'échantillons ; et
    c) une section de commande (36) reliée audit moyen de mémorisation (30) et audit moyen de filtre, ladite section de commande (36) comprenant :
    un multiplexeur (42) sélectionnant entre les pointeurs de mémoire pour ladite mémoire ;
    des premier et second compteurs de pointeurs (38, 40) reliés audit multiplexeur ;
    un troisième compteur de pointeur (44) relié à ladite mémoire de multiplication ;
    une unité de commande (37) reliée audit moyen de mémoire, audit moyen de filtre et auxdits compteurs de pointeur ; et
    un moyen d'établissement de correspondance (46), connecté entre ledit troisième compteur de pointeur (44) et ladite mémoire de multiplication (32) pour convertir un compte séquentiel en une sélection de coefficients non séquentiels.
  2. Convertisseur selon la revendication 1, dans lequel ledit moyen de filtre comprend de plus :
    une mémoire de coefficients de filtre (32) sortant des coefficients de filtre correspondant aux données en entrée et pour chaque fréquence de conversion d'échantillons ;
    un multiplicateur (32) connecté à ladite mémoire et multipliant les données en entrée par les coefficients de filtre ; et
    un accumulateur (33) connecté audit multiplicateur (32) et accumulant les données en entrée multipliées par les coefficients..
  3. Convertisseur selon la revendication 1, dans lequel ledit moyen d'établissement de correspondance (46) convertit un compte séquentiel, une sélection de sous-ensemble de coefficients et une sélection de correspondance de conversion de fréquence d'échantillonnage en la sélection de coefficients non séquentiels.
  4. Convertisseur selon l'une quelconque des revendications précédentes, dans lequel les coefficients de filtre sont symétriques et ladite mémoire de multiplication comprend une mémoire divisée en tables correspondant aux conversions de fréquence d'échantillonnage et chaque table étant divisée en sections de coefficients mémorisant les valeurs de pixel que multiplie un coefficient de filtre symétrique correspondant.
  5. Convertisseur selon la revendication 1 ou 3, dans lequel ledit moyen d'établissement de correspondance (46) comprend soit une table de consultation en mémoire morte, soit une logique de décodage.
  6. Convertisseur de fréquence d'échantillonnage (28) pour convertir des valeurs de pixel en entrée entrées à une première fréquence en valeurs de pixel en sortie produites à une seconde fréquence, ledit convertisseur comprenant :
    une mémoire vive (30) mémorisant les données en entrée ;
    un multiplexeur (42) connecté à ladite mémoire vive (30) ;
    un premier compteur (38) connecté audit multiplexeur (42) et commandant la mémorisation des valeurs de pixel en entrée dans ladite mémoire vive ;
    un registre (40) connecté audit multiplexeur et commandant la sortie des valeurs de pixel en entrée afin de produire les valeurs de pixel en sortie;
    une mémoire morte (32) connectée à ladite mémoire vive et mémorisant les valeurs de pixel que multiplient les valeurs de coefficients de filtre;
    une unité d'établissement de correspondance (46) connectée à ladite mémoire morte et produisant une valeur de sélection de coefficient ;
    un compteur (44) connecté à ladite unité d'établissement de correspondance et commandant la production de la valeur de sélection de coefficient ; et
    un accumulateur (33) connecté à ladite mémoire morte (32) et produisant les valeurs de pixel en sortie.
  7. Convertisseur selon la revendication 1, dans lequel ledit moyen de filtre effectue un filtrage par convolution.
  8. Convertisseur selon la revendication 1, dans lequel ledit moyen de mémorisation (30) comprend une mémoire vive.
EP92121804A 1991-12-23 1992-12-22 Circuit de conversion de fréquence d'échantillonnage pour données d'image Expired - Lifetime EP0548917B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/810,405 US5274469A (en) 1991-12-23 1991-12-23 Sample rate converter circuit for image data
US810405 1991-12-23

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EP0548917A1 EP0548917A1 (fr) 1993-06-30
EP0548917B1 true EP0548917B1 (fr) 1997-08-27

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EP (1) EP0548917B1 (fr)
JP (1) JPH0612487A (fr)
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DE3918866A1 (de) * 1989-06-09 1990-12-13 Blaupunkt Werke Gmbh Anordnung zur umsetzung eines signals mit einer ersten abtastrate in ein signal mit einer zweiten abtastrate
JP3094419B2 (ja) * 1990-02-19 2000-10-03 ソニー株式会社 サンプリングレート変換装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008522313A (ja) * 2004-12-03 2008-06-26 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ プログラマブルプロセッサ

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US5274469A (en) 1993-12-28
DE69221840D1 (de) 1997-10-02
EP0548917A1 (fr) 1993-06-30
DE69221840T2 (de) 1998-03-26
JPH0612487A (ja) 1994-01-21

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