EP0544427B1 - Circuit de contrÔle pour un système d'affichage avec un circuit d'attaque de source numérique, capable de générer des tensions d'attaque à plusieurs niveaux en partant d'une seule source d'énergie externe - Google Patents
Circuit de contrÔle pour un système d'affichage avec un circuit d'attaque de source numérique, capable de générer des tensions d'attaque à plusieurs niveaux en partant d'une seule source d'énergie externe Download PDFInfo
- Publication number
- EP0544427B1 EP0544427B1 EP92310381A EP92310381A EP0544427B1 EP 0544427 B1 EP0544427 B1 EP 0544427B1 EP 92310381 A EP92310381 A EP 92310381A EP 92310381 A EP92310381 A EP 92310381A EP 0544427 B1 EP0544427 B1 EP 0544427B1
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- EP
- European Patent Office
- Prior art keywords
- signal
- output
- signals
- external power
- display module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2011—Display of intermediate tones by amplitude modulation
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
- G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
Definitions
- the present invention relates to a display module drive circuit, and more particularly to a digital source driver for outputting multi-level drive voltages for display of a multi-density-level image based on an input digital video signal of a specified number of bits.
- Fig. 13 schematically shows a conventional matrix type liquid crystal display module.
- the matrix type liquid crystal display module employs a TFT (Thin Film Transistor) as a switching element for driving pixel electrodes.
- a TFT liquid crystal display panel 300 includes m signal electrodes 302 (Nos. O 1 through Om) arranged in parallel with each other and i scanning electrodes 301 (Nos. 1 through i) arranged in parallel with each other and perpendicularly to the signal electrodes 302.
- a TFT 304 In proximity to the intersecting point between each scanning electrode 301 and each signal electrode 302 is provided a TFT 304 for driving a corresponding pixel electrode 303.
- One horizontal scanning line is composed of m pixel electrodes 303 connected to one scanning electrode 301.
- the TFT liquid crystal panel 300 is driven by an LCD module drive circuit 200 including a source driver 201 and a gate driver 202.
- the source driver 201 and the gate driver 202 are connected respectively to the signal electrodes 302 and the scanning electrodes 301.
- the source driver 201 samples and holds an input digital image signal or a video signal to supply the signal to the signal electrodes 302.
- the gate driver 202 successively outputs scanning pulses to the scanning electrodes 301.
- the gate driver 202 and the source driver 201 receive control signals such as a clock signal from a control circuit 203.
- An external power voltage generating circuit 204 generates a plurality of external power voltages of different levels (for example, eight) from an input power voltage and supplies them to the source driver 201.
- Fig. 14 shows in detail the construction of the source driver 201 shown in Fig. 13.
- the source driver 201 includes a shift register 101, a sampling memory 102, a hold memory 103, a decoder 104, and an output voltage selecting circuit 105.
- the source driver 201 has m signal systems corresponding to the m signal electrodes.
- Fig. 15 shows the construction of an n th (1 ⁇ n ⁇ m ) signal system of the source driver 201.
- part belonging to the nth signal system of the output voltage selecting circuit 105 is composed of eight analog switches ASW 0 through ASW 7 .
- the shift register 101 shown in Figs. 13 and 14 outputs a SAMPLING pulse Tsmpn for the n th pixel.
- externally input video signals D 0 , D 1 , and D 2 are taken into the sampling memory 102 and held in three D-flip-flops 121, 122, and 123 belonging to the nth signal system of the sampling memory 102.
- an OUTPUT pulse OE is input to the hold memory 103.
- the video signals D 0 , D 1 , and D 2 held in the sampling memory 102 are transferred to the hold memory 103 (three D-flip-flops 131, 132, and 133) and then to the decoder 104.
- the decoder 104 decodes the input video signals D 0 , D 1 , and D 2 and outputs eight enabling signals Y 0 through Y 7 (only one of these signals is at a high (H) level and the others are at a low (L) level).
- one of analog switches ASW 0 through ASW 7 in the output voltage selecting circuit 105 becomes conductive. Therefore, from among the eight external power voltages V 0 through V 7 transmitted from the external power voltage generating circuit 204 to the output voltage selecting circuit 105, one voltage which has been applied to the analog switch made conductive is output to the signal electrode (source line) On (1 ⁇ n ⁇ m). In this way, the external power voltages V 0 through V 7 having multiple levels or gradations can be supplied as drive voltages to the TFT liquid crystal panel 300 in accordance with the contents of the video signal D 0 , D 1 , and D 2 .
- the above-mentioned conventional drive circuit is accompanied by a problem of requiring an increased number of external power voltages which serve as density-scale reference voltages.
- EP-A-0 298 255 discloses a drive circuit for an active-matrix liquid crystal (LC) display panel, in which a control voltage is periodically converted from a value corresponding to the ON state of the LC elements to a value corresponding to the OFF state thereof during one horizontal scanning period.
- Analogue switches connected to the source lines of the panel are switched on at the beginning of each horizontal scanning period. After that, each source line is charged until a voltage corresponding to its respective digital data signal sample is reached, and then the respective analogue switch is turned off. The voltage is thereafter maintained by the capacitance of the source line and/or an additional sample holder.
- the object of the present invention is to provide a display module drive circuit which is capable of supplying multi-level drive voltages corresponding to multiple density levels of an image to be displayed, without increasing the number of the external power sources.
- the present invention provides the display module drive circuit defined by claim 1.
- a display module drive circuit in accordance with an embodiment of the present invention operates as follows. First, a timing signal generating circuit generates timing signals having different pulse widths in each horizontal period. The number of the timing signals (for example, 8) depends on the density levels of the image to be displayed. One of the timing signals is always held at H level. Then a voltage control circuit receives video signals and the timing signals and selects one of the timing signals based on the contents of the video signals in each horizontal period. Fig. 9 shows an example of selection of the timing signal for generation of the control signal. As shown in Fig. 9, when the video signals indicated by D 0 , D 1 , and D 2 represent the levels L, L, and L respectively, the timing signal T 0 is selected.
- the timing signal T 1 is selected.
- the timing signal T 7 is selected.
- the voltage control circuit outputs a control signal at a high level for a period corresponding to the pulse width of the selected timing signal.
- the capacitor receives the external power voltage from an external power source through the first switch means during the time when the control signal is output in each horizontal period so that a drive voltage is generated in each horizontal period.
- the external power voltage is supplied by an external power source offering an electrical potential which becomes higher with time, as illustrated in Fig. 10 that shows a relationship between the timing signals and the drive voltages used in an embodiment of the invention; thus, the level of the drive voltage is controllable in accordance with the pulse width of the selected timing signal so that drive voltages of multiple levels can be generated.
- the display module drive circuit drive voltages of multiple levels can be generated from a single external power source.
- the timing signal generating circuit generates an increased number of timing signals according to the amount of gradations.
- the number of the drive voltages increases accordingly.
- the above arrangement obviates any increase in number of the external power sources.
- the multi-level drive voltages can be generated without increasing the external power source. Accordingly, the following advantages are produced.
- the above-mentioned output voltage generating circuit has two capacitors and the two capacitors are alternately charged with the external power voltage in alternate horizontal periods, the drive voltages are output alternately from the two capacitors. In other words, when one of the capacitors is being charged, the other capacitor outputs the drive voltage. Therefore, continuous output of the drive voltage is achieved.
- the two capacitors are switched by output-switching signals which are generated by the timing signal generating circuit. The output-switching signals are at opposite levels from each other in their active periods and respectively inverted every horizontal period.
- Fig. 1 is a block diagram of a matrix type liquid crystal display module which uses a drive circuit 200 including a gate driver 202 which is the same as that of Fig. 13 and a source driver 7 in accordance with an embodiment of the present invention.
- a drive circuit 200 including a gate driver 202 which is the same as that of Fig. 13 and a source driver 7 in accordance with an embodiment of the present invention.
- the same components as those in Fig. 13 showing the conventional matrix type liquid crystal display module are denoted by the same numerals, and no detailed description on those components is provided here.
- the liquid crystal display module of Fig. 1 has no circuit for generating a plurality of external power voltages of multiple levels such as the external power voltage generating circuit 204 shown in Fig. 13.
- Fig. 2 shows the construction of the entire source driver 7 shown in Fig. 1.
- Fig. 3 shows a part processing the n th (1 ⁇ n ⁇ m) one of the m signal groups (each one represented by three bits) of the source driver 7.
- the m signal groups correspond to the m pixels.
- the source driver 7 includes a shift register 1, a sampling memory 2, a hold memory 3, a timing signal generating circuit 4, a voltage control circuit 5, and an output voltage generating circuit 6.
- the shift register 1, sampling memory 2, and hold memory 3 are the same as the shift register 101, sampling memory 102, and hold memory 103 shown in Fig. 13-15 respectively.
- the timing signal generating circuit 4 is composed of two parts 4A and 4B as shown in Fig. 4.
- the part 4A is composed of D-flip-flop circuits 41, 42, and 43, an AND circuit 44, a NOR circuit 45, and a NAND circuit 47.
- the part 4A of the timing signal generating circuit 4 when receiving clock pulses CLK and a pulse signal OE input once a horizontal period, the part 4A of the timing signal generating circuit 4 generates output-switching signals OE1 and OE2, which are at opposite levels from each other in their active periods and inverted respectively every horizontal period, as well as a clear signal CLR1 obtained by inverting most part of the pulse signal OE.
- signals OEA and OEB in Fig. 5 are outputs of the D-flip-flop circuits 42 and 43 respectively.
- the part 4B of the timing signal generating circuit 4 is composed of a 6-bit counter 46, an inverter 48, and D-flip-flop circuits 49 through 55, as shown in Fig. 4.
- the part 4B When receiving the clock pulses CLK, the part 4B first generates a signal 64 CK representing 64 clock pulses as shown in Fig. 6. Then, eight kinds (corresponding to the number of density levels of an image) of timing signals T 0 , T 1 , ..., T 7 having different pulse widths are generated in one horizontal period based on the signal 64 CK. (Note that the timing signal T 0 is maintained at H level.)
- the voltage control circuit 5 more specifically part thereof processing the n th signal group shown in Fig. 3, receives video signals HnD 0 , HnD 1 , and HnD 2 from the hold memory 3, the timing signals T 0 , T 1 , ..., T 7 , and the output-switching signals OE1 and OE2 from the timing signal generating circuit 4. Then the voltage control circuit 5 outputs control signals CON1 and CON2 at specific levels every horizontal period, as shown in Fig. 7, according to the contents of the received signals and output-switching signals.
- the control signal CON1 is held at H level for a period corresponding to the pulse width of the timing signal T 0 , T 1 , ..., or T 7 selected according to the contents of the video signals HnD 0 , HnD 1 , and HnD 2 . Meanwhile, the control signal CON2 is maintained at L level, irrespective of the contents of the video signals HnD 0 , HnD 1 , and HnD 2 .
- the control signal CON1 assumes L level irrespective of the contents of the video signals HnD 0 , HnD 1 , and HnD 2 . Meanwhile, the control signal CON2 is held at H level for a period corresponding to the pulse width of the timing signal T 0 , T 1 , ..., or T 7 selected according to the contents of the video signals HnD 0 , HnD 1 , and HnD 2 .
- the output voltage generating circuit 6 (more specifically part thereof processing the n th signal group) is composed of wirings L1 and L2 connecting an external power source (voltage V) to a source line (signal electrode) On, capacitors C1 and C2 connected between each of the wirings L1 and L2 and the ground, and analog switches ASW1, ASW2, ASW3, and ASW4.
- the analog switches ASW1 and ASW3 are arranged on the wiring L1 and on opposite sides of the capacitor C1 toward the external power source and the source line On, respectively.
- These analog switches ASW1 and ASW3 are turned on and off respectively by the control signal CON1 from the voltage control circuit 5 and the output-switching signal OE2 from the timing signal generating circuit 4 (the switches are turned on when each control signal is at H level and turned off when each control signal is at L level).
- the analog switches ASW2 and ASW4 are arranged on the wiring L2 and toward the external power source and the source line (signal electrode) On from the capacitor C2, respectively. These switches ASW2 and ASW4 are turned on and off respectively by the control signal CON2 from the voltage control circuit 5 and the output-switching signal OE1 from the timing signal generating circuit 4 (the switches are turned on when each control signal is at H level and turned off when each control signal is at L level).
- the above-mentioned source driver 7 operates as follows. First, when the shift register 1 outputs a sampling pulse Tsmpn for the n th pixel, the externally input video signals D 0 , D 1 , and D 2 are taken into the sampling memory 2 at the leading edge of the sampling pulse Tsmpn. Then those sampled video signals are held as video signals SnD 0 , SnD 1 , and SnD 2 in the three D-flip-flops 21, 22, and 23 of the sampling memory 2 (part processing the n th signal group). When the sampling operation in one horizontal period is completed, the pulse signal OE is input to the hold memory 3.
- the video signals SnD 0 , SnD 1 , and SnD 2 held in the sampling memory 2 are received by the hold memory 3 (three D-flip-flops 31, 32, and 33) to be then transferred as video signals HnD 0 , HnD 1 , and HnD 2 to the voltage control circuit 5.
- the voltage control circuit 5 outputs the control signal CON1 or CON2 of H level for the period corresponding to the pulse width of the timing signal T 0 , T 1 , ..., or T 7 selected in each horizontal period based on the contents of the video signals HnD 0 , HnD 1 , and HnD 2 , as described hereinbefore.
- the output-switching signal OE1 is at H level and the output-switching signal OE2 is at L level in a specified horizontal period.
- the control signal CON1 is turned to H level and the control signal CON2 is turned to L level. Consequently, in the output voltage generating circuit 6, the analog switches ASW1 and ASW4 are turned on while the analog switches ASW2 and ASW3 are turned off. Therefore, the capacitor C1 is charged with the external power voltage V through the analog switch ASW1 for the period corresponding to the pulse width of the timing signal T 0 , T 1 , ..., or T 7 selected by the voltage control circuit 5.
- the output-switching signals OE1, OE2 serve to determine which of the capacitors C1, C2 should be charged with the external power voltage and which of the voltages charged in the capacitors C1, C2 should be supplied to the source line On.
- the output-switching signal OE1 is switched to L level and the output-switching signal OE2 is switched to H level.
- the control signal CON1 is switched to L level and the control signal CON2 is switched to H level.
- the analog switches ASW1 and ASW4 are turned off while the analog switches ASW2 and ASW3 are turned on in the output voltage generating circuit 6. Therefore, the capacitor C2 is charged with the external power voltage V by way of the analog switch ASW2 for the period corresponding to the pulse width of the timing signal T 0 , T 1 , ..., or T 7 selected by the voltage control circuit 5.
- the source driver 7 can generate multi-level drive voltages from only a single external power source.
- the timing signal generating circuit 4 When increasing the number of bits of the video signal to increase the number of density levels of an image, the timing signal generating circuit 4 generates an increased number of timing signals according to the number of the density levels to enable generation of multi-level drive voltages based on the timing signals. In this way, multi-level drive signals can be offered without increasing the number of the external power sources.
- the light transmissivity varies in the medium voltage region and is saturated in the low and high voltage regions as shown in Fig. 11. Since digital one bit display system has only the on and off status, a high contrast can be obtained so long as the display panel is driven at voltages in the low and high voltage regions.
- the characteristic curve (voltage-time characteristic) of the external power voltage shown in Fig. 10 is corrected as shown in Fig. 12 to provide the voltage levels or gradations with a linear characteristic.
- transmissivity varies in the medium voltage region at the present time as shown in Fig. 11, the transmissivity needs to change in the low voltage region in the future because a liquid crystal display device using a low drive voltage such as 3V, for example, can be used then.
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
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- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal Display Device Control (AREA)
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Claims (6)
- Circuit d'attaque de module d'affichage, propre à produire, à partir d'une source extérieure d'énergie fournissant une tension de sortie à variation temporelle, plusieurs signaux de tension de sortie pour la commande de l'intensité d'affichage d'éléments d'image d'un panneau afficheur (300) du type matriciel, chaque signal de tension de sortie ayant un niveau qui correspond à une intensité sélectionnée, parmi un certain nombre d'intensités d'affichage prédéterminées, en fonction d'un signal vidéo numérique d'entrée (D0, D1, D2) représentant l'image à afficher, le circuit d'attaque de module d'affichage comprenant :un moyen (4) pour produire un certain nombre de signaux de cadencement (T0 à T7) de largeurs différentes, le nombre des signaux de cadencement étant égal audit nombre d'intensités d'affichage ;un moyen (5) pour sélectionner l'un des signaux de cadencement en fonction du niveau dudit signal vidéo, et pour fournir sur cette base un signal de commande, le signal de commande étant produit sous la forme d'un premier et d'un second signaux de commande (CON1, CON2) en alternance dans des périodes horizontales successives ; etun moyen (6) pour produire lesdits plusieurs signaux de tension de sortie, comprenant des moyens (ASW1 à 4) pour relier ladite source extérieure d'énergie à un premier condensateur (C1) ou à un second condensateur (C2) pour une période prédéterminée en réponse, respectivement, audit premier ou audit second signal de commande, de telle manière que, lorsque l'un des deux condensateurs est relié à la source extérieure d'énergie, l'autre condensateur fournisse un signal de tension de sortie.
- Circuit d'attaque de module d'affichage selon la revendication 1, dans lequel le moyen générateur de signaux de cadencement (4) fournit en outre un premier et un second signaux de commutation de sortie (OE1, OE2), qui ont des niveaux opposés l'un à l'autre dans leurs périodes actives, et qui sont respectivement inversés à chaque période horizontale, et dans lequel le moyen de sélection (5) reçoit ledit signal vidéo (D0, D1, D2), les signaux de cadencement (T0 à T7) et les signaux de commutation de sortie (OE1, OE2), et choisit l'un des signaux de cadencement, sur la base du contenu du signal vidéo et des signaux de commutation de sortie dans chaque période horizontale, afin de produire le premier ou le second signal de commande (CON1, CON2) à un niveau spécifié pour la durée correspondant à la largeur d'impulsion du signal de cadencement (T0 à T7) sélectionné.
- Circuit d'attaque de module d'affichage selon la revendication 1 ou la revendication 2, dans lequel le moyen générateur de tension de sortie (6) a des premiers moyens commutateurs (ASW1, ASW2) pour appliquer lesdits premier et second signaux de commande (CON1, CON2), respectivement, auxdits premier et second condensateurs (C1, C2).
- Circuit d'attaque de module d'affichage selon la revendication 3, dans lequel le moyen générateur de tension de sortie (6) a des deuxièmes moyens commutateurs (ASW3, ASW4) pour fournir le signal de tension de sortie, en alternance, à partir des premier et second condensateurs (C1, C2).
- Circuit d'attaque de module d'affichage selon la revendication 4 lorsqu'elle dépend de la revendication 2, dans lequel les deuxièmes moyens commutateurs (ASW3, ASW4) sont commandés sur la base des états desdits premier et second signaux de commutation de sortie (OE1, OE2).
- Circuit d'attaque de module d'affichage selon l'une quelconque des revendications précédentes, dans lequel la forme d'onde de tension produite par ladite source extérieure d'énergie est prévue pour la correction d'une non linéarité de la caractéristique de transmissivité, selon la tension appliquée, des cristaux liquides utilisés dans ledit panneau afficheur (300).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3312319A JPH05150737A (ja) | 1991-11-27 | 1991-11-27 | 表示装置用駆動回路 |
JP312319/91 | 1991-11-27 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0544427A2 EP0544427A2 (fr) | 1993-06-02 |
EP0544427A3 EP0544427A3 (en) | 1993-07-21 |
EP0544427B1 true EP0544427B1 (fr) | 1997-01-15 |
Family
ID=18027814
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP92310381A Expired - Lifetime EP0544427B1 (fr) | 1991-11-27 | 1992-11-13 | Circuit de contrÔle pour un système d'affichage avec un circuit d'attaque de source numérique, capable de générer des tensions d'attaque à plusieurs niveaux en partant d'une seule source d'énergie externe |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0544427B1 (fr) |
JP (1) | JPH05150737A (fr) |
KR (1) | KR960016342B1 (fr) |
DE (1) | DE69216785T2 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN115128573A (zh) * | 2022-08-30 | 2022-09-30 | 北京摩尔芯光半导体技术有限公司 | 用于光学相控阵的驱动电路、驱动方法及激光雷达装置 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3139892B2 (ja) * | 1993-09-13 | 2001-03-05 | 株式会社東芝 | データ選択回路 |
EP1041535A1 (fr) * | 1999-03-30 | 2000-10-04 | EM Microelectronic-Marin SA | Dispositif de commande d'un dispositif LCD ayant au moins un niveau de couleur |
JP3925467B2 (ja) * | 2003-06-20 | 2007-06-06 | セイコーエプソン株式会社 | 電気光学装置及びその駆動方法並びに電子機器 |
CN102842278B (zh) * | 2012-08-06 | 2015-09-02 | 北京大学深圳研究生院 | 栅极驱动电路单元、栅极驱动电路及显示器 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6125184A (ja) * | 1984-07-13 | 1986-02-04 | 株式会社 アスキ− | 表示制御装置 |
JP2779494B2 (ja) * | 1986-07-07 | 1998-07-23 | セイコーエプソン株式会社 | 駆動回路及び液晶表示装置 |
JPH0750389B2 (ja) * | 1987-06-04 | 1995-05-31 | セイコーエプソン株式会社 | 液晶パネルの駆動回路 |
JP2667204B2 (ja) * | 1988-06-18 | 1997-10-27 | 株式会社日立製作所 | 階調表示装置 |
DE3930259A1 (de) * | 1989-09-11 | 1991-03-21 | Thomson Brandt Gmbh | Ansteuerschaltung fuer eine fluessigkristallanzeige |
-
1991
- 1991-11-27 JP JP3312319A patent/JPH05150737A/ja active Pending
-
1992
- 1992-11-13 EP EP92310381A patent/EP0544427B1/fr not_active Expired - Lifetime
- 1992-11-13 DE DE69216785T patent/DE69216785T2/de not_active Expired - Fee Related
- 1992-11-21 KR KR1019920022056A patent/KR960016342B1/ko not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115128573A (zh) * | 2022-08-30 | 2022-09-30 | 北京摩尔芯光半导体技术有限公司 | 用于光学相控阵的驱动电路、驱动方法及激光雷达装置 |
Also Published As
Publication number | Publication date |
---|---|
JPH05150737A (ja) | 1993-06-18 |
EP0544427A2 (fr) | 1993-06-02 |
KR960016342B1 (ko) | 1996-12-09 |
DE69216785T2 (de) | 1997-07-24 |
EP0544427A3 (en) | 1993-07-21 |
DE69216785D1 (de) | 1997-02-27 |
KR930010837A (ko) | 1993-06-23 |
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