EP0599622B1 - Circuit de commande pour contrÔler un appareil d'affichage et méthode pour le même - Google Patents

Circuit de commande pour contrÔler un appareil d'affichage et méthode pour le même Download PDF

Info

Publication number
EP0599622B1
EP0599622B1 EP19930309360 EP93309360A EP0599622B1 EP 0599622 B1 EP0599622 B1 EP 0599622B1 EP 19930309360 EP19930309360 EP 19930309360 EP 93309360 A EP93309360 A EP 93309360A EP 0599622 B1 EP0599622 B1 EP 0599622B1
Authority
EP
European Patent Office
Prior art keywords
output
driving circuit
period
signal
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19930309360
Other languages
German (de)
English (en)
Other versions
EP0599622A1 (fr
Inventor
Hisao Okada
Shigeyuki Uehira
Junji Kawanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP4315421A external-priority patent/JP2849010B2/ja
Priority claimed from JP4315422A external-priority patent/JP2806718B2/ja
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of EP0599622A1 publication Critical patent/EP0599622A1/fr
Application granted granted Critical
Publication of EP0599622B1 publication Critical patent/EP0599622B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant

Definitions

  • the present invention relates to a method for driving a flat panel display apparatus, and also relates to a driving circuit for the display apparatus. More particularly, the invention relates to a method for driving a display apparatus which receives a digital image signal to produce a display image with gray scales in accordance with the received digital image signals, and it also relates to a driving circuit for such a display apparatus.
  • Figure 1 shows a data driver exemplifying a conventional driving circuit for driving a display apparatus which receives digital image data to produce a display image with gray scales in accordance with the received data.
  • the digital image data consists of two bits (D 0 , D 1 ).
  • This data driver supplies driving voltages to N pixels (where N is a positive integer) on a scanning line which has been selected by means of a scanning signal.
  • FIG. 2 shows a circuit constituting part of the data driver of Figure 1 .
  • This circuit which is denoted by the reference numeral 20 , supplies a driving voltage through a data line to the "n"th pixel (where n is an integer of 1 to N) of the above-mentioned N pixels provided along the single scanning line.
  • the circuit 20 includes sampling (primary) flip-flops 21 each for receiving one bit of the digital image data (D 0 , D 1 ), holding (secondary) flip-flops 22 each also for receiving one bit, a decoder 23 and four analog switches 24 to 27 . To the analog switches 24 to 27 , signal voltages V 0 to V 3 are respectively supplied from four different voltage sources.
  • D flip-flops or various other flip-flops can be used as the sampling flip-flops 21 .
  • the circuit 20 shown in Figure 2 operates as follows. On receiving the leading edge of a sampling pulse T smpn corresponding to the "n"th pixel, the sampling flip-flops 21 obtain the digital image data (D 0 , D 1 ) and hold the thus obtained data therein. When such image data sampling for the 1st to Nth pixels on a single scanning line is completed (i.e., sampling corresponding to one horizontal period is completed), an output pulse OE is applied to the holding flip-flops 22 . On receiving the output pulse OE, the holding flip-flops 22 obtain the digital image data (D 0 , D 1 ) from the sampling flip-flops 21 , and transfer the thus obtained digital image data to the decoder 23 .
  • the decoder 23 decodes each bit of the digital image data (D 0 , D 1 ), and turns on one of the analog switches 24 to 27 in accordance with the respective values of the thus decoded bits. As a result, one of the signal voltages V 0 to V 3 from the four different voltage sources, which corresponds to the thus turned-on analog switch 24 , 25 , 26 or 27 , is output from the circuit 20 .
  • a conventional data driver such as described above requires 2 n different voltage sources (where n is the number of bits constituting digital image data).
  • n is the number of bits constituting digital image data.
  • the number of required voltage sources doubles when the digital image data is enlarged by one bit.
  • Such voltage sources are connected through the analog switches of the data driver to a display apparatus, e.g., a liquid crystal panel, which provides a heavy load on the voltage sources.
  • a display apparatus e.g., a liquid crystal panel
  • each voltage source is required to have a sufficient performance to drive such a heavy load.
  • the increase in the number of such high-performance voltage sources is a significant factor in the higher production cost of the entire driving circuit.
  • high-performance voltage sources cannot readily be placed within the LSI circuit constituting the driving circuit, they must be located outside the LSI circuit. This means that signal voltages for driving the liquid crystal panel must be supplied from external voltage sources to the LSI circuit. As a result, with an increase in the number of voltage sources, the number of input terminals of the LSI circuit must be increased accordingly.
  • an oscillating voltage driving method and a driving circuit using this method have been proposed by EP-A-0 478 386 and Japanese Patent Application No. 4-129164, which has not been published.
  • external voltage sources are provided to supply gray-scale reference voltages which are used to further obtain a plurality of interpolated voltages, so that gray scales can be obtained using both the gray-scale reference voltages and the interpolated voltages.
  • the number of gray scales which can be obtained is larger than that of the voltage sources in the driving circuit.
  • FIG. 3 shows a circuit 30 constituting part of a data driver exemplifying the proposed driving circuit using the above-described oscillating voltage driving method.
  • the circuit 30 four interpolated voltages (V 0 +2V 2 )/3, (2V 2 +V 5 )/3, (V 2 +2V 5 )/3 and (2V 5 +V 7 )/3 can be obtained from four gray-scale reference voltages V 0 , V 2 , V 5 and V 7 which are supplied from external voltage sources. From the four gray-scale reference voltages and the four resultant interpolated voltages, eight gray scales are obtained. Thus, the provision of only four voltage sources for supplying gray-scale reference voltages makes it possible to obtain eight gray scales.
  • Figure 4 shows, by way of example, the waveform of a signal voltage V 1 which is output to a data line from the circuit 30 of Figure 3 , and the waveform of a signal voltage V COM applied across a common electrode (not shown) of a liquid crystal panel which is driven by this conventional data driver in accordance with a known alternating driving method. It is assumed in Figure 4 that the entire driving circuit operates under the ideal condition of no load.
  • the signal voltage V 1 is one of the four interpolated voltages described above, which is produced from the gray-scale reference voltages V 0 and V 2 in the case where the value of the digital image data is 1.
  • Voltages V 1 + and V 1 - indicate voltages applied to a pixel in a positive period (field) and in a negative period (field), respectively.
  • the waveforms of the gray-scale reference voltages V 0 and V 2 are shown in Figure 5 , for comparison with the signal voltage (interpolated voltage) V 1 .
  • the signal voltage V 1 periodically oscillates between the two gray-scale reference voltages V 0 and V 2 in such a manner that the ratio of the total time for V 0 to that for V 2 in one output period is 1:2.
  • a voltage such as this signal voltage V 1 which periodically oscillates between two different voltages, is known as an oscillating voltage.
  • This conventional data driver operates in accordance with a so-called “line inversion method" in which the polarity of signal voltages is changed from positive to negative or vice versa at the beginning of each horizontal period, thereby preventing the deterioration of the liquid crystal device.
  • One output period is usually set equal to one horizontal period.
  • Figure 6 shows a power supply circuit 60 for supplying the above-mentioned gray-scale reference voltages V 0 and V 2 to the data driver.
  • the power supply circuit 60 includes operational amplifiers 61 and 62 .
  • the oscillating voltage V 1 in Figure 4 can be obtained by allowing the power supply circuit 60 to alternately output the two gray-scale reference voltages V 0 and V 2 during one output period.
  • Figure 7 shows an equivalent circuit of a data line which is connected to the data driver and accordingly provides a load on it.
  • capacitance and resistance exist as distributed constants.
  • capacitance and resistance can be considered simply as concentrated constants R S and C S .
  • the concentrated constants R S and C S may be set to 50 k ⁇ and 100 pF, respectively.
  • Figure 8 shows an example of the waveform of the gray-scale reference voltage V 0 supplied from the power supply circuit 60 in which parasitic oscillation has occurred. This unnecessary parasitic oscillation causes problems such as an increase in power consumption and generation of heat in the power supply circuit 60.
  • a possible way to prevent such parasitic oscillation is to decrease the slewing rates of the operational amplifiers 61 and 62 of the power supply circuit 60.
  • the decrease in the slewing rates however, deteriorates the characteristics of the entire driving circuit, such as its current response characteristics or rise time.
  • a method of driving a display apparatus which includes a display section, the display section comprising: pixels; switching elements, each switching element being connected to a respective one of the pixels; a driving circuit for driving the display section; and signal lines connecting the switching elements to the driving circuit, whereby voltages are applied to the pixels to produce a display image;
  • the predetermined time period includes a period of time during which the driving circuit remains in a transient state, the transient state of the driving circuit arising at the start of the output period.
  • the oscillating voltage signal periodically oscillates between a first voltage and a second voltage.
  • a driving circuit for a display apparatus having a display section comprising: pixels; switching elements connected to respective ones of the pixels; and signal lines connected to the switching elements; wherein the driving circuit applies voltages to said pixels to produce a display image;
  • the predetermined time period includes a period of time during which the driving circuit remains in a transient state, the transient state of the driving circuit arising at the start of the output period.
  • the oscillating voltage signal periodically oscillates between a first voltage and a second voltage.
  • the voltage signal output control means includes: a plurality of switching means; and a selective control circuit for receiving digital image data and then turning on or off the switching means individually to control the on/off state thereof in accordance with the received digital image data, and wherein the switching means allow, only when they are turned on, different voltage signals respectively supplied thereto to be delivered to each of the signal lines, and the selective control circuit turns on one of the switching means to keep the switching means in the on state during the predetermined time period, and then controls the on/off state of at least one pair of the switching means to alternately turning them on from the end of the predetermined time period until the end of the output period.
  • the invention described herein makes possible the advantages of (1) providing a method for driving a display apparatus, which method enables rapid switching of gray-scale reference voltages, without causing any parasitic oscillation in a power supply circuit, and also without any deterioration in the characteristics of a driving circuit, such as its current response characteristics or rise time; and (2) providing a driving circuit which drives a display apparatus in accordance with such a method.
  • Figure 1 is a schematic diagram showing the circuit of a conventional data driver.
  • Figure 2 is a schematic diagram showing a circuit which constitutes part of the conventional data driver of Figure 1 .
  • Figure 3 is a schematic diagram showing a circuit which constitutes part of another conventional data driver.
  • Figure 4 shows the waveform of a signal voltage applied to a data line from the circuit 30 of Figure 3 , and the waveform of a voltage applied to a common electrode.
  • Figure 5 shows the waveforms of gray-scale reference voltages V 0 and V 2 .
  • Figure 6 is a schematic diagram showing a power supply circuit 60 for supplying the gray-scale reference voltages V 0 and V 2 .
  • Figure 7 is a schematic diagram showing an equivalent circuit of a data line which provides a load on a data driver.
  • Figure 8 shows the waveform of a gray-scale reference voltage V 0 supplied from a power supply circuit in which parasitic oscillation has occurred.
  • Figure 9 is a schematic diagram showing a liquid crystal display apparatus to be driven by a method and a driving circuit according to the invention.
  • Figure 10 is a timing chart showing the relationship among signals during one horizontal period.
  • Figure 11 is a timing chart showing the relationship among signals during one vertical period.
  • Figure 12 is a schematic diagram showing a circuit which constitutes part of a data driver 92 shown in Figure 9 .
  • Figure 13 shows the waveforms of an output pulse signal OE and signals t, c and t'.
  • Figure 14 shows the waveform of a signal voltage which is output to a data line 96 from the circuit of Figure 12 .
  • a matrix-type liquid crystal display apparatus is herein used as a display apparatus to be driven by a method and a driving circuit according to the invention. But it is understood that the method and driving circuit of the invention can also be applied to other types of display apparatus.
  • FIG. 9 is a schematic diagram showing the configuration of a matrix-type liquid crystal display apparatus to be driven by a method and a driving circuit according to the invention.
  • the liquid crystal display apparatus includes a display section 90 for displaying an image thereon, and a driving circuit 91 for driving the display section 90 .
  • the driving circuit 91 includes a data driver 92 and a scanning driver 93 which provide image signals and scanning signals, respectively, to the display section 90 .
  • the data driver is also sometimes referred to as a source driver or column driver.
  • the scanning driver is also sometimes referred to as a gate driver or row driver.
  • the display section 90 includes an M x N array of pixels 94 (M pixels in each column and N pixels in each row; where M and N are positive integers), and also includes switching elements 95 respectively connected to the pixels 94 .
  • the data driver 92 is provided with N output terminals S(i) (where i is an integer of 1 to N) each of which corresponds to one of the N columns of M switching elements 95 .
  • the N output terminals S(i) are respectively connected to the corresponding switching elements 95 by means of N data lines 96 .
  • the scanning driver 93 is provided with M output terminals G(j) (where j is an integer of 1 to M) each of which corresponds to one of the M rows of N switching elements 95 .
  • the M output terminals G(j) are respectively connected to the corresponding switching elements 95 by means of M scanning lines 97 .
  • As the switching elements 95 thin film transistors (TFTs) can be used. Alternatively, other types of switching elements may also be used.
  • TFTs thin film transistors
  • the data line is also sometimes referred to as a source line or column line.
  • the scanning line is also sometimes referred to as a gate line or row line.
  • the scanning driver 93 outputs high-scale voltages sequentially from its output terminals G(j) to the corresponding scanning lines 97 , in such a manner that the level of the voltage output from each output terminal G(j) is kept at a high level for a specific period of time.
  • This specific time period is designated as one horizontal period jH (where j is an integer of 1 to M).
  • the total length of time obtained by adding up all the horizontal periods jH i.e., 1H + 2H + 3H + ... + MH
  • one vertical period is designated as one vertical period.
  • the switching elements 95 connected via the scanning line 97 to the output terminal G(j) are turned on. While the switching elements 95 are kept in the on state, the pixels 94 respectively connected thereto are charged in accordance with voltages supplied to the corresponding data lines 96 from the output terminals S(i) of the data driver 92 . The voltages of the thus charged pixels 94 remain unchanged for about one vertical period until they are charged again by the subsequent voltages to be supplied from the data driver 92 .
  • Figure 10 shows the relationship among digital image data DA, sampling pulses T smpi , and an output pulse signal OE, during the "j"th horizontal period jH determined by a horizontal synchronizing signal H syn .
  • sampling pulses T smp1 , T smp2 , ..., T smpi , ..., T smpN are sequentially applied to the data driver 92
  • digital image data DA 1 , DA 2 ..., DA i ..., DA N are fed into the data driver 92 accordingly.
  • the "j"th output pulse OE j determined by the output pulse signal OE is then applied to the data driver 92 .
  • the data driver 92 On receiving the "j"th output pulse OE j , the data driver 92 outputs voltages in accordance with the digital image data DA 1 to DA N , respectively from its output terminals S(1) to S(N) to the corresponding data lines 96 .
  • Figure 11 shows the relationships among the horizontal synchronizing signal H syn , the digital image data DA, the output pulse signal OE, and the timing of voltage supply from the data driver 92 and scanning driver 93 , during one vertical period determined by a vertical synchronizing signal V syn .
  • a SOURCE (j) indicates the levels of voltages output from the data driver 92 , with such timing as shown in Figure 10 and in accordance with the N sets of digital image data DA which have been fed into the data driver 92 during the "j"th horizontal period jH.
  • the SOURCE (j) is shown as a hatched rectangular area to indicate a range of voltages output from all the N output terminals S(1) to S(N) of the data driver 92 .
  • the voltage supplied from the scanning driver 93 through its output terminal G(j) to the "j"th scanning line 97 is changed to and kept at a high level, thereby turning on all the N switching elements 95 connected to the "j"th scanning line 97 .
  • the N pixels 94 respectively connected to these N switching elements 95 are charged in accordance with the voltages applied to the corresponding data lines 96 from the data driver 92 .
  • the above-described process is repeated M times, i.e., for the 1st to Mth scanning lines 97 , so that an image corresponding to one vertical period is displayed.
  • the thus produced image serves as a complete display image on the display screen thereof.
  • the time interval between the rise of the "j"th output pulse OE j and the rise of the "j+1"th output pulse OE j+1 in the output pulse signal OE is herein designated as one output period.
  • one output period is made equal to one horizontal period. The reason for this is as follows: While the data driver 92 outputs, to the data lines 96 , voltages corresponding to digital image data for one horizontal (scanning) line, it also performs sampling of digital image data for the next horizontal line. The maximum length of time during which these voltages can be output from the data driver 92 is equal to one horizontal period.
  • one output period is equal to one horizontal period. According to the invention, however, one output period is not necessarily required to be equal to one horizontal period.
  • the data driver 92 of the driving circuit 91 shown in Figure 9 is presented as an example of the driving circuit according to the invention, which will be described in detail below by reference to Figures 12 to 14 .
  • Figure 12 shows one of N identical circuits 120 in the data driver 92 .
  • N circuits 120 supply signal voltages respectively through the N output terminals S(1) to S(N) of the data driver 92 to the corresponding data lines 96 .
  • the circuit 120 outputs a signal voltage through the "n"th output terminal S(n) to the corresponding data line 96 (where n is an integer of 1 to N).
  • digital image data consists of three bits (D 0 , D 1 , D 2 ).
  • the circuit 120 includes sampling (primary) flip-flops 121 and holding (secondary) flip-flops 122 both for receiving and holding the respective bits of the digital image data (D 0 , D 1 , D 2 ).
  • the circuit 120 also includes a selective control circuit 123 , and four analog switches 124 to 127 to which voltages of different levels are respectively supplied.
  • the selective control circuit 123 turns on or off the analog switches 124 to 127 individually to control the on/off state thereof in accordance with the received digital image data.
  • the selective control circuit 123 receives a signal t' output from an AND circuit 128 to which signals t and c are input.
  • the number of such AND circuits 128 required for the LSI circuit constituting the data driver 92 is, theoretically, only one.
  • the data lines 96 are so designed as to provide equal loads. Accordingly, in all the power supply circuits for the data driver 92 (which power supply circuits are of the same type as, for example, the power supply circuit 60 shown in Figure 6 ), substantially equal periods of time are required for high-level currents flowing therethrough at the beginning of one output period to decrease to their respective steady-state current levels. This results in that, in all the output terminals S(1) to S(N) of the data driver 92 , necessary time intervals between the start of one output period and the start of the oscillating voltage supply can be made substantially equal (these time intervals will be described in detail later).
  • all the output terminals S(1) to S(N) are allowed to output oscillating voltages substantially at the same point of time in one output period. Since the timing of oscillating voltage supply is determined by using the signal t' output from the AND circuit 128 (as will be described later), all the N circuits 120 corresponding to the output terminals S(1) to S(N) of the data driver 92 can share the single AND circuit 128 .
  • the signal c may be generated within the LSI circuit constituting the data driver 92 , thereby preventing an increase in the number of terminals of the LSI circuit.
  • the sampling flip-flops 121 On receiving the leading edge of the sampling pulse T smpn corresponding to the "n"th pixel, the sampling flip-flops 121 obtain the respective bits of the digital image data (D 0 , D 1 , D 2 ) and hold the thus obtained data therein. This sampling process is performed for all the N pixels connected to one of the scanning lines 97 (the "j"th scanning line), respectively by all the N circuits 120 of the data driver 92 . At the time when such sampling of image data for all the N pixels connected to the single scanning line 97 (i.e., sampling corresponding to one horizontal period) is completed, an output pulse OE is applied to the holding flip-flops 122 .
  • the holding flip-flops 122 On receiving the output pulse OE, the holding flip-flops 122 obtain the digital image data (D 0 , D 1 , D 2 ) from the sampling flip-flops 121 , and also output the received digital image data to the selective control circuit 123 .
  • the selective control circuit 123 is provided with input terminals d 0 , d 1 and d 2 , and output terminals S 0 , S 2 , S 5 and S 7 .
  • the three bits of the digital image data (D 0 , D 1 , D 2 ) are respectively input through the input terminals d 0 , d 1 and d 2 to the selective control circuit 123 .
  • the selective control circuit 123 outputs control signals respectively for turning on or off the analog switches 124 to 127 so as to control the on/off state thereof.
  • Gray-scale reference voltages V 0 , V 2 , V 5 and V 7 of different voltage levels are supplied to the four analog switches 124 to 127 , respectively. Each of these voltages is output to the data line 96 only when the corresponding analog switch 124 , 125 , 126 or 127 is on.
  • the relationship among the levels of these voltages is: V 0 ⁇ ⁇ V 5 V 7 or V 7 ⁇ V 5 ⁇ V 2 ⁇ V 0 .
  • the power supply circuit 60 shown in Figure 6 can be used as described above.
  • Table 1 is a logical table showing the relationship between inputs and outputs of the selective control circuit 123 .
  • the first section of Table 1 i.e., the first three columns from the left
  • the second section of Table 1 i.e., the next four columns
  • Each of the analog switches 124 to 127 is turned on when receiving a control signal with a value of 1 from the output terminal S 0 , S 2 , S 5 or S 7 connected thereto, and turned off when receiving a control signal with a value of 0.
  • Each of the blanks in the second section of Table 1 indicates that the value of the control signal is 0.
  • Each "t'" indicates that the control signal has a value of 1 when the value of the signal t' is 1, and that the control signal has a value of 0 when the value of the signal t' is 0.
  • each t ' indicates that the control signal has a value of 0 when the value of the signal t' is 1, and that the control signal has a value of 1 when the value of the signal t' is 0.
  • Figure 13 shows the waveforms of the above-described output pulse signal OE, and signals t, c and t'.
  • the signal t is a pulse signal which periodically alternates between the values of 0 and 1 with a duty ratio of 1:2. Specifically, the ratio of the time for the signal t having a value of O to that for the signal t having a value of 1 is 1:2.
  • the signal c is a pulse signal which is kept at a value of 0 only for a predetermined period of time from the rise of each output pulse OE. In other words, the value of the pulse signal c is kept at 0 only for a predetermined time period from the beginning of one output period, and then changes to 1 so that it is kept at 1 during the remaining part of the output period.
  • the signal c may be generated from the output pulse signal OE. Since the signal t' is an output from the AND circuit 128 which receives the signals t and c as its inputs, the signal t' is kept at a value of 0 during the above-mentioned predetermined time period from the beginning of one output period, and is then changed into a pulse signal identical to the signal t and remains unchanged until the start of the next output period.
  • the control signals output from the output terminals S 0 and S 2 have the values of the signal t ' and of the signal t', respectively.
  • the value of the signal t ' is kept at 0 as described above, so that the value of the t' is kept at 1. Therefore, during this time period, the output terminal S 0 outputs a control signal with a value of 1, thereby turning on the analog switch 124 to keep it in the on state.
  • the other analog switches 125 to 127 remain off.
  • the voltage V 0 alone is output to the data line 96 during the predetermined time period from the beginning of the output period.
  • the signal t' is changed into a pulse signal identical to the signal t, so that the value thereof alternates between 0 and 1 during the remaining part of the output period.
  • the analog switch 125 connected to the output terminal S 2 is turned on, with the other analog switches off, thereby allowing the voltage V 2 to be output to the data line 96 .
  • the value of the t ' becomes 1, so that the analog switch 124 connected to the output terminal S 0 is turned on with the other analog switches off, thereby allowing the voltage V 0 to be output to the data line 96 .
  • the signal voltage which is output from the circuit 120 to the data line 96 becomes an oscillating voltage which oscillates between the voltages V 0 and V 2 in the same cycle as that of the pulse signal t'.
  • Figure 14 shows the waveform of a signal voltage output from the circuit 120 of Figure 12 to the corresponding data line 96 .
  • the circuit 120 outputs only the voltage V 0 to the data line 96 for a predetermined time period from the beginning of one output period.
  • the voltage V 2 alone may be output to the data line 96 during this predetermined time period.
  • the solid line represents the waveform of the signal voltage obtained on the assumption that the entire driving circuit operates on the ideal condition of no load.
  • the broken lines represent changes in the potential of the data line 96 under the actual load provided by the liquid crystal panel.
  • a non-oscillating voltage i.e., only the voltage V 0 or V 2
  • V 0 or V 2 the voltage supplied to the data line 96 from the beginning of one output period until the potential of the data line 96 reaches the level of the output signal voltage. Therefore, no parasitic oscillation arises in the power supply circuit 60 .
  • Figure 14 also shows the signal c for comparison.
  • the period of time during which the signal c is kept at a value of 0 can be changed so as to adjust the time interval between the start of one output period and the start of oscillating voltage supply.
  • the data driver 92 starts to output an oscillating voltage after the potential of the data line 96 has reached approximately the level of the output signal voltage, thereby preventing parasitic oscillation from arising in the power supply circuit 60 .
  • the supply of oscillating voltage may be allowed to start as long as the transient state of the driving circuit has been changed into a substantially steady state. At the end of the transient state, the current reaches a lower level and the degree of decrease in the current level becomes small. At this time also, the supply of oscillating voltage may be allowed to start; this timing of oscillating voltage supply also makes it possible to prevent parasitic oscillation from arising in the power supply circuit 60. For example, it has been found that the sufficient effect of preventing parasitic oscillation can be obtained by starting the supply of oscillating voltage at the time when the current flowing through the power supply circuit 60 decreases to about 1/4 of its peak current level.
  • the necessary time interval between the start of one output period and the start of oscillating voltage supply depends on the characteristics of a liquid crystal panel serving as a load and of a power supply circuit.
  • the point of time at which the supply of oscillating voltage is allowed to start may vary over a certain range of time.
  • the driving circuit while the driving circuit is in a transient state in the initial part of each output period, non-oscillating signal voltages are output to the signal lines (i.e., the data lines described above), so that parasitic oscillation can be prevented from arising in the power supply circuit. Accordingly, the stable operation of the power supply circuit can be assured, thereby preventing increase in power consumption and generation of heat in the power supply circuit.
  • oscillating voltages are output to the signal lines after the elapse of a predetermined time period from the beginning of one output period, i.e., after the driving circuit has changed from its transient state to a substantially steady state. Therefore, a plurality of interpolated voltages (i.e., the oscillating voltages described above) can be obtained from gray-scale reference voltages by the oscillating voltage driving method without causing any unnecessary parasitic oscillation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Claims (7)

  1. Procédé pour commander un dispositif d'affichage qui inclut une section d'affichage, la section d'affichage comprenant des pixels (94); des éléments de commutation (95), chaque élément de commutation étant connecté à l'un respectif des pixels ; un circuit de commande (91) pour commander la section d'affichage ; et des lignes de transmission de signaux (S(i)....S(N)) connectant les éléments de commutation au circuit de commande, ce qui a pour effet que des tensions sont appliquées aux pixels pour produire une image d'affichage ;
    le procédé étant caractérisé en ce qu'il comprend les étapes consistant à :
    délivrer des signaux de tension non oscillants provenant dudit circuit de commande (91) pendant un intervalle de temps prédéterminé à partir du début d'une période de sortie, chaque signal de tension non oscillant étant envoyé à l'une respective desdites lignes de transmission de signaux ; et
    délivrer des signaux de tension oscillants à partir dudit circuit de commande, depuis la fin dudit intervalle de temps prédéterminé jusqu'à la fin de ladite période de sortie, chaque signal de tension oscillant étant envoyé à l'une respective desdites lignes de transmission de signaux, ledit signal de tension oscillant comprenant au moins une composante oscillante.
  2. Procédé selon la revendication 1, selon lequel ledit intervalle de temps prédéterminé inclut un intervalle de temps pendant lequel ledit circuit de commande reste dans un état transitoire, l'étape transitoire du circuit de commande commençant au début de ladite période de sortie.
  3. Procédé selon la revendication 1, selon lequel ledit signal de tension oscillant oscille périodiquement entre une première tension et une seconde tension.
  4. Circuit de commande pour un dispositif d'affichage, le dispositif d'affichage possédant une section d'affichage comprenant : des pixels (94) ; des éléments de commutation (95) connectés à certains des pixels ; et des lignes de transmission de signaux (S(i)...S(N)) connectées aux éléments de commutation ; le circuit de commande appliquant des tensions auxdits pixels pour produire une image d'affichage ;
    le circuit de commande étant caractérisé en ce qu'il comporte en outre :
    des moyens de commande de sortie de signaux de tension pour délivrer des signaux de tension non oscillants pendant un intervalle de temps prédéterminé à partir du début d'une période de sortie, chaque signal de tension non oscillant étant envoyé à l'une respective desdites lignes de transmission de signaux, et pour délivrer des signaux de tension oscillants depuis la fin dudit intervalle de temps prédéterminé jusqu'à la fin de ladite période de sortie, chaque signal de tension oscillant étant envoyé à l'une respective desdites lignes de transmission de signaux, chacun desdits signaux de tension oscillants comprenant au moins une composante oscillante.
  5. Circuit de commande selon la revendication 4, dans lequel ledit intervalle de temps prédéterminé inclut un intervalle de temps pendant lequel ledit circuit de commande reste dans un état transitoire, l'état transitoire du circuit de commande apparaissant au début de ladite période de sortie.
  6. Circuit de commande selon la revendication 4, dans lequel ledit signal de tension oscillant oscille périodiquement entre une première tension et une seconde tension.
  7. Circuit de commande selon la revendication 4, dans lequel lesdits moyens de commande de sortie de signaux de tension comprennent :
    une pluralité de moyens de commutation ; et
    un circuit de commande sélectif pour recevoir lesdites données d'images numériques, puis activer et désactiver lesdits moyens de commutation individuellement pour commander l'état fermé/ouvert de ces moyens en fonction des données d'images numériques reçues ; et
    dans lequel lesdits moyens de commutation permettent, uniquement lorsqu'ils sont fermés, l'envoi de signaux de tension, qui leur sont respectivement envoyés, à chacune desdites lignes de transmission de signaux, et
    lesdits circuits de commande sélective ferment l'un desdits moyens de commutation pour maintenir lesdits moyens de commutation à l'état fermé pendant ledit intervalle de temps prédéterminé, puis commandent l'état fermé/ouvert d'au moins un couple desdits moyens de commutation pour les fermer alternativement depuis la fin dudit intervalle de temps prédéterminé jusqu'à la fin de ladite période de sortie.
EP19930309360 1992-11-25 1993-11-24 Circuit de commande pour contrÔler un appareil d'affichage et méthode pour le même Expired - Lifetime EP0599622B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP315422/92 1992-11-25
JP315421/92 1992-11-25
JP4315421A JP2849010B2 (ja) 1992-11-25 1992-11-25 表示装置の駆動回路
JP4315422A JP2806718B2 (ja) 1992-11-25 1992-11-25 表示装置の駆動方法及び駆動回路

Publications (2)

Publication Number Publication Date
EP0599622A1 EP0599622A1 (fr) 1994-06-01
EP0599622B1 true EP0599622B1 (fr) 1998-02-04

Family

ID=26568300

Family Applications (2)

Application Number Title Priority Date Filing Date
EP19930309359 Expired - Lifetime EP0599621B1 (fr) 1992-11-25 1993-11-24 Circuit de commande pour appareil d'affichage améliorant le réglage des tensions
EP19930309360 Expired - Lifetime EP0599622B1 (fr) 1992-11-25 1993-11-24 Circuit de commande pour contrÔler un appareil d'affichage et méthode pour le même

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP19930309359 Expired - Lifetime EP0599621B1 (fr) 1992-11-25 1993-11-24 Circuit de commande pour appareil d'affichage améliorant le réglage des tensions

Country Status (2)

Country Link
EP (2) EP0599621B1 (fr)
DE (2) DE69313587T2 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0140041B1 (ko) 1993-02-09 1998-06-15 쯔지 하루오 표시 장치용 전압 발생 회로, 공통 전극 구동 회로, 신호선 구동 회로 및 계조 전압 발생 회로
KR0124975B1 (ko) * 1994-06-07 1997-12-01 김광호 박막 트랜지스터형 액정표시장치의 전력 구동회로
US6057820A (en) * 1996-10-21 2000-05-02 Spatialight, Inc. Apparatus and method for controlling contrast in a dot-matrix liquid crystal display

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2849740B2 (ja) * 1986-03-17 1999-01-27 セイコーインスツルメンツ株式会社 強誘電性液晶電気光学装置
DE69115414T2 (de) * 1990-09-28 1996-06-13 Sharp Kk Steuerschaltung für ein Anzeigegerät

Also Published As

Publication number Publication date
EP0599621A1 (fr) 1994-06-01
DE69316852T2 (de) 1998-08-06
EP0599622A1 (fr) 1994-06-01
DE69316852D1 (de) 1998-03-12
DE69313587T2 (de) 1998-03-19
DE69313587D1 (de) 1997-10-09
EP0599621B1 (fr) 1997-09-03

Similar Documents

Publication Publication Date Title
US7508479B2 (en) Liquid crystal display
US7463234B2 (en) Liquid crystal display and data latch circuit
US7872628B2 (en) Shift register and liquid crystal display device using the same
KR100293962B1 (ko) 액정표시패널을구동하는액정구동회로
EP0767449B1 (fr) Méthode et circuit d'attaque d'un panneau d'affichage à cristaux liquides à matrice active avec contrôle de la tension moyenne de commande
US7474305B2 (en) Data transfer method, image display device and signal line driving circuit, active-matrix substrate
US6567066B1 (en) Driving circuit of display device
US20050078076A1 (en) Scan driver, display device having the same, and method of driving display device
US5621426A (en) Display apparatus and driving circuit for driving the same
EP0676078B1 (fr) Circuit d'attaque selectif pour un affichage a cristaux liquides (lcd)
EP0479896B1 (fr) Systeme de balayage pour affichage a cristaux liquides
JPH10260664A (ja) 液晶駆動回路とこれを用いた液晶装置
WO2010061656A1 (fr) Dispositif d’affichage et procédé d’actionnement de ce dernier
US6121945A (en) Liquid crystal display device
EP0624862B1 (fr) Circuit de commande pour dispositif d'affichage
US5642126A (en) Driving circuit for driving a display apparatus and a method for the same
JP2002169518A (ja) 液晶表示装置
EP0599622B1 (fr) Circuit de commande pour contrÔler un appareil d'affichage et méthode pour le même
KR20190069182A (ko) 시프트레지스터 및 이를 포함하는 표시장치
US5680148A (en) Driving circuit for a display apparatus capable of display of an image with gray scales
EP0544427B1 (fr) Circuit de contrÔle pour un système d'affichage avec un circuit d'attaque de source numérique, capable de générer des tensions d'attaque à plusieurs niveaux en partant d'une seule source d'énergie externe
KR100332297B1 (ko) 공통전극의단계적충전및방전을이용한액정표시장치및그구동방법
JP2009198970A (ja) 液晶表示パネルの駆動装置
KR100488082B1 (ko) 액정표시장치의 패널구조 및 구동방법
JP2965822B2 (ja) 電源回路

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

17P Request for examination filed

Effective date: 19941118

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

17Q First examination report despatched

Effective date: 19961016

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

RIN1 Information on inventor provided before grant (corrected)

Inventor name: KAWANISHI,JUNJI

Inventor name: UEHIRA, SHIGEYUKI

Inventor name: OKADA, HISAO

REF Corresponds to:

Ref document number: 69316852

Country of ref document: DE

Date of ref document: 19980312

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20021108

Year of fee payment: 10

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20021120

Year of fee payment: 10

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20021128

Year of fee payment: 10

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20031124

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20040602

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20031124

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20040730

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST