EP0624862B1 - Circuit de commande pour dispositif d'affichage - Google Patents

Circuit de commande pour dispositif d'affichage Download PDF

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Publication number
EP0624862B1
EP0624862B1 EP19940303106 EP94303106A EP0624862B1 EP 0624862 B1 EP0624862 B1 EP 0624862B1 EP 19940303106 EP19940303106 EP 19940303106 EP 94303106 A EP94303106 A EP 94303106A EP 0624862 B1 EP0624862 B1 EP 0624862B1
Authority
EP
European Patent Office
Prior art keywords
grey
scale voltage
oscillating
scale
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19940303106
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German (de)
English (en)
Other versions
EP0624862A3 (fr
EP0624862A2 (fr
Inventor
Hisao Okada
Yuji Yamamoto
Mitsuyoshi Seo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Publication of EP0624862A2 publication Critical patent/EP0624862A2/fr
Publication of EP0624862A3 publication Critical patent/EP0624862A3/fr
Application granted granted Critical
Publication of EP0624862B1 publication Critical patent/EP0624862B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals

Definitions

  • the output means comprises
  • the switching means is an analogue switch.
  • a pair of gray-scale voltages are selected (specified) among a plurality of gray-scale voltages, and one of a plurality of oscillating signals is specified.
  • the driving circuit outputs a voltage signal which oscillates between the specified pair of gray-scale voltages at the oscillating frequency of the specified oscillating signal. Therefore, a plurality of interpolated gray scales can be realized between a plurality of applied gray-scale voltages.
  • the driving circuit of the invention by using the gray-scale voltage specifying means and the oscillating signal specifying means, it is possible to always realize an image display with multiple gray scales in both cases where the driving circuit directly outputs one of the plurality of gray-scale voltages and where the driving circuit alternately outputs the specified pair of gray-scale voltages.
  • the invention described herein makes possible the advantage of providing a driving circuit for a display apparatus, which has a simplified and small construction, and which can display an image with multiple gray scales in accordance with multi-bit video data.
  • Figure 1 is a diagram showing a construction of a liquid crystal display apparatus.
  • Figure 7 is a diagram showing a part of a configuration of a selection control circuit SCOL in the driving circuit in the example according to the invention.
  • Figure 9 is a diagram showing another part of the configuration of the selection control circuit SCOL in the driving circuit in the example according to the invention.
  • Figure 12 is a diagram showing a part of a configuration of a data driver in a driving circuit of a related art.
  • Figure 13 shows waveforms of signals t 1 -t 4 supplied to a selection control circuit SCOL .
  • Figure 14 is a diagram showing a part of a configuration of a selection control circuit SCOL in the conventional driving circuit.
  • a matrix type liquid crystal display apparatus is used as an example of a display apparatus. It is appreciated that the present invention is applicable to other types of display apparatus.
  • FIG 1 shows a construction of a matrix type liquid crystal display apparatus.
  • the liquid crystal display apparatus shown in Figure 1 includes a display section 100 for displaying a video image, and a driving circuit 101 for driving the display section 100 .
  • the driving circuit 101 includes a data driver 102 which provides video signals to the display section 100 and a scanning driver 103 which provides scanning signals to the display section 100 .
  • the data driver may be called “a source driver” or "a column driver”.
  • the scanning driver may be called "a gate driver” or "a row driver”.
  • the display section 100 includes an M x N array of pixels 104 (M pixels in each column and N pixels in each row; where M and N are positive integers), and also includes switching elements 105 respectively connected to the pixels 104 .
  • the switching elements 105 thin film transistors (TFTs) can be used. Alternatively, other types of switching elements may also be used.
  • the data line may be called “a source line” or "a column line”.
  • the scanning line may be called "a gate line” or "a row line”.
  • the switching element 105 connected to the output terminal G(j) When the level of the voltage which is output from the output terminal G(j) of the scanning driver 103 to the scanning line 107 is high, the switching element 105 connected to the output terminal G(j) is in the ON-state. When the switching element 105 is in the ON-state, the pixel 104 connected to the switching element 105 is charged in accordance with the voltage which is output from the output terminal S(j) of the data driver 102 to the corresponding data line 106 . The voltage of the thus charged pixel 104 remains unchanged for about one vertical period until it is charged again by the subsequent voltage to be supplied from the data driver 102 .
  • Figure 3 shows the relationship among the horizontal synchronizing signal H syn , the digital video data DA, the output pulse signal OE, and the timing of outputs of the data driver 102 and scanning driver 103 , during one vertical period determined by a vertical synchronizing signal V syn .
  • a SOURCE(j) indicates a level range of voltages output from the data driver 102 , with such timing as shown in Figure 2 and in accordance with the digital video data applied during the horizontal period jH.
  • the SOURCE(j) is shown as a hatched rectangular area to indicate a level range of voltages output from all the N output terminals S(1) to S(N) of the data driver 102 .
  • the voltage which is output from the jth output terminal G(j) of the scanning driver 103 to the jth scanning line 107 is changed to and kept at a high level, thereby turning on all the N switching elements 105 connected to the jth scanning line 107 .
  • the N pixels 104 respectively connected to these N switching elements 105 are charged in accordance with the voltage applied to the corresponding data lines 106 from the data driver 102 .
  • the time interval between the jth output pulse OE j and the (j+1)th output pulse OE j+1 in the output pulse signal OE is defined as "one output period".
  • one output period is equal to a period represented by SOURCE(j) shown in Figure 3 .
  • one output period is equal to one horizontal period. According to the present invention, however, one output period is not necessarily required to be equal to one horizontal period.
  • Figure 6 shows a configuration of a part of the data driver 102 in the driving circuit 101 .
  • the circuit 60 shown in Figure 6 outputs a video signal from an nth output terminal S(n) to one data line 106 .
  • the data driver 102 includes circuits 60 the number of which is equal to the number of the data lines 106 provided in the display section 100 .
  • the video data consists of 6 bits (D 0 , D 1 , D 2 , D 3 , D 4 , D 5 ).
  • the video data may have 64 kinds of values of 0 - 63, and a signal voltage applied to each pixel is one of nine gray-scale voltages V 0 , V 8 , V 16 , V 24 , V 32 , V 40 , V 48 , V 56 , and V 64 , and interpolated voltages which are produced from any pair of the gray-scale voltages chosen from V 0 , V 8 , V 16 , V 24 , V 32 , V 40 , V 48 , V 56 , and V 64
  • sampling flip-flop M SMP and the holding flip-flop M H for example, D-type flip-flops can be used. It is appreciated that such sampling and holding flip-flops can be realized by using other types of circuit elements.
  • the control signals are used for switching the ON/OFF states of the respective analog switches ASW 0 -ASW 8 .
  • the video data input to the selection control circuit SCOL is represented by d 0 , d 1 , d 2 , d 3 , d 4 , and d 5
  • the control signals output from the selection control circuit SCOL are represented by S 0 , S 8 , S 16 , S 24 , S 32 , S 40 , S 48 , S 56 , and S 64 .
  • Table 2 is a logical table for the lower three bits d 2 , d 1 , and d 0 of the 6-bit video data.
  • the 1st to 3rd columns of Table 2 indicate the values of video data bits d 2 , d 1 , and d 0 , respectively.
  • the 4th to 11th columns of Table 2 indicate which oscillating signal is specified from the oscillating signals t 0 -t 7 .
  • the oscillating signals t 0 -t 7 are clock signals having duty ratios of 8:0, 7:1, 6:2, 5:3, 4:4, 3:5, 2:6, and 1:7, respectively.
  • an oscillating signal has a duty ratio of k:0 or 0:k (k is a natural number)
  • the oscillating signal is defined as always being at a fixed level.
  • the oscillating signals t 5 , t 6 , and t 7 are the signals obtained by inverting the oscillating signals t 3 , t 2 , and t 1 .
  • Equation (6) can alternatively be represented as the following equation.
  • T (0) + (1)t 1 + (2)t 2 + (3)t 3 + (4)t 4 + (5)t 5 + (6)t 6 + (7)t 7
  • logical circuits 70 , 80 , 90 , and 95 shown in Figures 7 through 10 are obtained.
  • the selection control circuit SCOL is constructed, for example, by the logical circuits 70 , 80 , 90 , and 95 shown in Figures 7 through 10 .
  • the logical circuit 70 shown in Figure 7 selectively outputs oscillating signal specifying signals (0)-(7) for specifying one of a plurality of oscillating signals t 0 -t 7 , in accordance with the lower 3 bits d 2 , d 1 , and d 0 of the video data. More specifically, the video data d 2 , d 1 , and d 0 and the inverted signals which are respectively obtained by inverting the video data d 2 , d 1 , and d 0 by inverter circuits INV 0 to INV 2 are input into AND circuits AG 0 -AG 7 in such combinations that constitute 0-7 in binary notation. The oscillating signal specifying signals (0)-(7) are thus obtained as the outputs of the AND circuits AG 0 -AG 7 .
  • the logical circuit 90 shown in Figure 9 selectively outputs gray-scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and [56] for specifying a pair of gray-scale voltages from among a plurality of gray-scale voltages, in accordance with the upper three bits d 5 , d 4 , and d 3 of the video data. More specifically, the video data d 5 , d 4 , and d 3 and the inverted signals which are respectively obtained by inverting the video data d 5 , d 4 , and d 3 by inverter circuits INV 4 -INV 6 are input to AND circuits DG 0 -DG 7 in such combinations which constitute 0-7 in the binary notation. As the outputs of the AND circuits DG 0 -DG 7 , the gray-scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and [56] are obtained.
  • the logical circuit 95 shown in Figure 10 selectively outputs the control signals S 0 -S 64 , in accordance with the gray-scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and [56], the oscillating signal T, and the inverted oscillating signal T . More specifically, the gray-scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and [56], and the oscillating signal T are input into AND circuits EG 0 , EG 2 , EG 4 , EG 6 , EG 8 , EG 10 , EG 12 , and EG 14 , respectively.
  • the outputs of the AND circuits EG 7 and EG 8 are coupled to the inputs of an OR circuit FG 4 , respectively.
  • the outputs of the AND circuits EG 9 and EG 10 are coupled to the inputs of an OR circuit FG 5 , respectively.
  • the outputs of the AND circuits EG 11 and EG 12 are coupled to the inputs of an OR circuit FG 6 , respectively.
  • the outputs of the AND circuits EG 13 and EG 14 are coupled to the inputs of an OR circuit FG 7 , respectively.
  • the control signals S 0 , S 8 , S 16 , S 24 , S 32 , S 40 , S 48 , S 56 , and S 64 are obtained.
  • the control signals S 0 , S 8 , S 16 , S 24 , S 32 , S 40 , S 48 , S 56 , and S 64 are supplied to the corresponding analog switches ASW 0 -ASW 8 .
  • Each of the control signals S 0 , S 8 , S 16 , S 24 , S 32 , S 40 , S 48 , S 56 , and S 64 has either a high-level value or a low-level value. For example, if the control signal is at a high level, the corresponding analog switch is controlled to be in the ON-state. If the control signal is at a low level, the corresponding analog switch is controlled to be in the OFF-state. Alternatively, the relationship between the level of the control signal and the ON/OFF state of the analog signal can be set in a reverse manner.
  • a waveform of an oscillating voltage is specified in accordance with video data consisting of at least one bit selected from the plurality of bits. Then, in accordance with video data consisting of bits other than the above selected bit(s), a pair of gray-scale voltages are specified from a plurality of gray-scale voltages. As a result, a voltage signal of an appropriate level can be output for every value of video data.
  • the oscillating voltage is used for realizing a plurality of interpolated gray-scale voltages between the specified pair of gray-scale voltages which are specified from among the plurality of gray-scale voltages.
  • the duty ratio n:m of the oscillating signal or the control signal is interpreted to be k:0 or 0:k (k is a natural number).
  • the specified pair of gray-scale voltages among the plurality of gray-scale voltages may be alternately output.
  • the actual data driver requires selection control circuits SCOL the number of which is equal to the number of data lines.
  • the circuit scale of the selection control circuits SCOL largely affects the chip size of an integrated circuit (LSI) on which a data driver is installed.
  • LSI integrated circuit
  • the production cost of the integrated circuit can be reduced.
  • the number of bits of video data is increased in order to realize an image with a larger number of gray scales
  • miniaturization of the circuit scale of the data driver is of great use. Accordingly, it is possible to make further progress in the size and cost reduction of the integrated circuit.
  • the invention it is possible to obtain one or more interpolated voltages from voltages supplied from given voltage sources, whereby the number of voltage sources can be greatly decreased as compared with a conventional driving circuit which requires a large number of voltage sources. If the voltage sources are provided from the outside of the driving circuit, the number of input terminals of the driving circuit can be reduced. If the driving circuit is constructed as an LSI, the number of input terminals of the LSI can be reduced. According to the invention, it is possible to realize a driving LSI for displaying an image with multiple gray scales which could not be realized by the prior art example because of the increase in the number of terminals.
  • the following effects can be attained: (1) the production cost of a display apparatus and a driving circuit are largely reduced; (2) a driving circuit for multiple gray scales which could not be practically produced due to the chip size or the LSI installation can be readily produced; and (3) the power consumption is decreased because a large number of voltage sources are not required.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Claims (5)

  1. Circuit d'attaque pour attaquer un appareil d'affichage, l'appareil d'affichage comprenant des pixels et des lignes de données (S(1) ... S(n)) pour appliquer des tensions auxdits pixels et afficher, en service, une image à échelles de gris multiples conformément à des données vidéo se composant d'une multiplicité de bits, ledit circuit d'attaque comprenant:
    des moyens de sélection de tension d'oscillation pour sélectionner un signal parmi une multiplicité de signaux oscillants (t0 ... t7) oscillant entre un premier et un second niveaux prédéterminés et présentant des rapports cycliques respectifs différents les uns des autres, conformément à des données vidéo se composant de bits (d2, d1, d0) sélectionnés parmi ladite multiplicité de bits, et pour délivrer en sortie ledit signal oscillant sélectionné (T) et un signal oscillant inversé (T) qui est obtenu en inversant ledit signal oscillant sélectionné (T);
    des moyens de sélection de tension d'échelle de gris pour produire des signaux de sélection de tension d'échelle de gris qui sélectionnent une première tension d'échelle de gris et une seconde tension d'échelle de gris à partir d'une multiplicité de tensions d'échelle de gris (V0, V8, V16, V24, V32, V40, V48, V56, V64) fournies par des moyens d'alimentation en tension d'échelle de gris, conformément à des données vidéo se composant de bits (d5, d4, d3) autres que lesdits bits sélectionnés de ladite multiplicité de bits; et
    des moyens de sortie pour envoyer auxdites lignes de données ladite première tension d'échelle de gris et ladite seconde tension d'échelle de gris sélectionnées par lesdits moyens de sélection de tension d'échelle de gris, en fonction dudit signal oscillant (T) et dudit signal oscillant inversé (T), les moyens de sortie délivrant la première tension d'échelle de gris lorsque le signal oscillant (T) est audit premier niveau prédéterminé, et la seconde tension d'échelle de gris sélectionnée lorsque le signal oscillant inversé (T) est audit premier niveau prédéterminé.
  2. Circuit d'attaque selon la revendication 1, dans lequel ladite première tension d'échelle de gris et ladite seconde tension d'échelle de gris sont des tensions adjacentes parmi ladite multiplicité de tensions d'échelle de gris.
  3. Circuit d'attaque selon la revendication 1 ou la revendication 2, dans lequel ladite multiplicité de signaux oscillants comprend des signaux oscillants ayant, respectivement, des rapports cycliques égaux à 8:0, 7:1, 6:2, 5:3, 4:4, 3:5, 2:6 et 1:7.
  4. Circuit d'attaque selon l'une des revendications 1, 2 et 3, dans lequel les moyens de sortie comprennent:
    (a) des moyens de sortie de signal de commande pour envoyer un premier signal de commande, qui oscille suivant sensiblement le même rapport cyclique que celui dudit signal oscillant (T), à l'un desdits moyens de commutation qui reçoit ladite première tension d'échelle de gris sélectionnée par lesdits signaux de sélection de tension d'échelle de gris, et pour envoyer un second signal de commande, qui oscille suivant sensiblement le même rapport cyclique que celui dudit signal oscillant inversé (T), à l'un desdits moyens de commutation qui reçoit ladite seconde tension d'échelle de gris sélectionnée par lesdits signaux de sélection de tension d'échelle de gris; et
    (b) une multiplicité de moyens de commutation, chaque moyen de ladite multiplicité de moyens de commutation recevant un signal correspondant parmi ladite multiplicité de signaux de commande et une tension correspondante parmi la multiplicité de tensions d'échelle de gris, ladite tension d'échelle de gris fournie auxdits moyens de commutation étant envoyée auxdites lignes de données par l'intermédiaire desdits moyens de commutation, conformément audit signal de commande.
  5. Circuit d'attaque selon la revendication 4, dans lequel lesdits moyens de commutation sont des commutateurs analogiques.
EP19940303106 1993-05-14 1994-04-28 Circuit de commande pour dispositif d'affichage Expired - Lifetime EP0624862B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP11346593 1993-05-14
JP113465/93 1993-05-14
JP11346593 1993-05-14

Publications (3)

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EP0624862A2 EP0624862A2 (fr) 1994-11-17
EP0624862A3 EP0624862A3 (fr) 1995-05-17
EP0624862B1 true EP0624862B1 (fr) 1999-06-16

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EP19940303106 Expired - Lifetime EP0624862B1 (fr) 1993-05-14 1994-04-28 Circuit de commande pour dispositif d'affichage

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EP (1) EP0624862B1 (fr)
KR (1) KR0127102B1 (fr)
CN (1) CN1065059C (fr)
DE (1) DE69419070T2 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5673061A (en) * 1993-05-14 1997-09-30 Sharp Kabushiki Kaisha Driving circuit for display apparatus
TW306998B (fr) * 1993-11-26 1997-06-01 Sharp Kk
JPH08115060A (ja) * 1994-10-14 1996-05-07 Sharp Corp 表示装置の駆動回路及び液晶表示装置
JP3517503B2 (ja) * 1995-12-21 2004-04-12 株式会社日立製作所 Ｔｆｔ液晶ディスプレイの駆動回路
CN100585683C (zh) * 1997-02-17 2010-01-27 精工爱普生株式会社 显示装置
KR100509240B1 (ko) * 1997-02-17 2005-08-22 세이코 엡슨 가부시키가이샤 표시 장치
KR100593670B1 (ko) * 1999-08-25 2006-06-28 삼성전자주식회사 박막트랜지스터 액정표시장치의 소스드라이버의 계조전압을 선택하기 위한 디코딩회로
KR100555303B1 (ko) * 2002-12-11 2006-03-03 엘지.필립스 엘시디 주식회사 감마 전압 생성 장치 및 방법
JP4516280B2 (ja) * 2003-03-10 2010-08-04 ルネサスエレクトロニクス株式会社 表示装置の駆動回路
JP5000124B2 (ja) 2004-11-12 2012-08-15 三星電子株式会社 表示装置及びその駆動方法
KR101197043B1 (ko) * 2004-11-12 2012-11-06 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2642204B2 (ja) * 1989-12-14 1997-08-20 シャープ株式会社 液晶表示装置の駆動回路
DE69226723T2 (de) * 1991-05-21 1999-04-15 Sharp Kk Verfahren und Einrichtung zum Steuern einer Anzeigeeinrichtung
JPH05100635A (ja) * 1991-10-07 1993-04-23 Nec Corp アクテイブマトリクス型液晶デイスプレイの駆動用集積回路と駆動方法

Also Published As

Publication number Publication date
EP0624862A3 (fr) 1995-05-17
DE69419070T2 (de) 1999-11-18
CN1065059C (zh) 2001-04-25
EP0624862A2 (fr) 1994-11-17
KR0127102B1 (ko) 1997-12-29
CN1099177A (zh) 1995-02-22
DE69419070D1 (de) 1999-07-22

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