Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L21/8232—Field-effect technology
  • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
  • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
  • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L29/41725—Source or drain electrodes for field effect devices
  • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
  • H01L29/41783—Raised source or drain electrodes self aligned with the gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66568—Lateral single gate silicon transistors
  • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
  • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention relates to the field of MOS integrated circuits and, particularly to the process of forming source and drain regions of a CMOS integrated circuit device.
• MOS metal-oxide semiconductor
• FET field-effect transistor
• the source and drain regions are formed by doping the substrate in the area where these regions are to be formed. Ion implantation is one technique for doping the source and drain. Using gate alignment, the gate or the gate and an adjacent dielectric spacer are used to align the substrate area where the doping is to occur.
• a well known practice is to provide a first implant to define a first implanted area and a second implant to define a second implanted area. The second implanted area is the actual source or drain and the first implanted area provides a graded doping or lightly doped region between the source or the drain from the channel, in order to provide improved device integrity, especially higher breakdown drain voltages.
• the present invention provides for an improved method of forming source and drain regions in a semiconductor device, wherein the sharper definition, such as tighter control of source-drain spacing and source and drain doping profiles, of these regions permit for the fabrication of devices using submicron technology. Further, the improved method also provides for an ease of manufacture in fabricating the device.
• a "staircase" gate sidewall spacer is described in which tighter dimensional tolerances of the spacer provides for a tighter control of source-drain spacing and source and drain doping profiles, particularly as applied to "double doped" source and drain regions.
• the sidewall spacer is utilized to align areas of a substrate for ion implantation of the source and drain regions.
• the source and drain regions can be either an n-channel device or a p-channel device. By combining the n-channel and the p-channel, a CMOS device can be fabricated.
• a conformal oxide layer and then a conformal nitride layer are formed.
• anisotropic etching leaves an oxide spacer adjacent to the gate sidewall, primarily due to the selective etching of the overlying nitride layer.
• a staircase sidewall oxide spacer remains.
• an n- (or p-) implant is performed, followed by an n+ or (p+) implant to form the "double doped" source and drain regions.
• the first implant is performed at a higher energy level, ions penetrate the lower portion of the stair case shaped spacer.
• the second implant is achieved at a lower energy level than the first, so that the ions do not readily penetrate the spacer.
• a separation region of n-(or p-) resides between the n+ or (p+) region and the channel region.
• FIG. 1 is a cross-sectional view showing a formation of a gate and subsequent oxide layer to form a prior art MOS device.
• Figure 2 is a cross-sectional view showing a formation of n-/n+ source and drain regions for the prior art device of Figure 1.
• Figure 3 is a cross-sectional view showing the unpredictability of the formation of source and drain regions of the prior art device of Figure 2, due to variations in the slope of the sidewall oxide.
• Figure 4 is a cross-sectional view of the present invention showing a formation of a gate on a silicon substrate and a subsequent formation of an oxide layer above the gate and the substrate.
• Figure 5 is a cross-sectional view of a formation of a nitride layer over the oxide layer of Figure 4.
• Figure 6 is a cross-sectional view of a gate region of a device of the present invention, in which sidewall spacers remain after etching the oxide and nitride layers of Figure 5.
• Figure 7 is a cross-sectional view of the device of Figure 6 after removal of the nitride remnant on the sidewall spacers.
• Figure 8 is a cross-sectional view showing an n- implant to form n- source and drain regions to the device of Figure 7.
• Figure 9 is a cross-sectional view showing an n+ implant to form n+ source and drain regions to the device of Figure 8.
• Figure 10 is a cross-sectional view showing the source and drain regions of the device of Figure 9 after annealing, in which n-/n+ regions diffuse further into the substrate.
• Figure 11 is a cross-sectional view showing the formation of sidewall spacers to respective gates of both n-channel and p-channel areas of a CMOS device of the present invention.
• Figure 12 is a cross-sectional view showing an n- implant to form n- source and drain regions to the device of Figure 11.
• Figure 13 is a cross-sectional view showing an n+ implant to form n+ source and drain regions to the device of Figure 12.
• Figure 14 is a cross-sectional view showing a p- implant to form p- source and drain regions to the device of Figure 13.
• Figure 15 is a cross-sectional view showing a p+ implant to form p+ source and drain regions to the device of Figure 14.
• Figure 16 is a cross-sectional view showing the CMOS device of Figure 15 after annealing.
• Figure 17 is a cross-sectional view showing an alternative embodiment in which an elevated polysilicon layer is formed above a substrate and adjacent to sidewall spacers of the present invention.
• Figure 18 is a cross-sectional view showing a formation of n-/n+ source and drain regions underlying the elevated polysilicon of Figure 17.
• Figure 19 is a cross-sectional view showing a CMOS device of the alternative embodiment in which n-/n+ and p-/p+ source and drain regions are formed underlying elevated polysilicon.
• Figure 20 is a cross-sectional view showing a CMOS device of another alternative embodiment in which an elevated polysilicon layer is formed above a substrate and adjacent to sidewall spacers, but having a thickness that elevates the polysilicon layer above the foot of the spacer in order to implant a narrow region in the substrate.
• Figure 21 is a cross-sectional view of the elevated polysilicon device of Figure 20, but having a subsequent salicidation layer.
• a process for fabricating a semiconductor device using stepped spacer for improved formation of doped regions is described.
• a prior art technique is first described in order to provide a better understanding of the advantages derived by the practice of the present invention.
• numerous specific details are set forth, such as specific thicknesses, temperatures, etc., in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processes have not been described in detail in order not to unnecessarily obscure the present invention.
• Device 10 is a metal-oxide- semiconductor (MOS) device having a substrate 11, which substrate 11 is typically comprised of silicon. Circuit elements formed on substrate 11 are typically separated by field-oxide regions, such as field-oxide regions 12 of Figure 1. A gate 14 is then formed on substrate 11. Gate 14 is typically comprised of a polysilicon region 15 separated from the substrate 11 by a dielectric region 16, which dielectric 16 is typically comprised of an oxide such as silicon oxide (Si02) .
• MOS metal-oxide- semiconductor
• the gate 14 is used to define a channel region in the substrate 11 underlying the gate 14.
• a source and drain regions are then subsequently defined as the regions of the substrate bounding the channel region, such that the source and drain regions do not extend appreciably into the substrate 11 underlying gate 14.
• an oxide layer 17 is deposited prior to forming the source and drain regions.
• oxide layer 17 is etched to expose portions of substrate 11 for the purpose of forming the source and drain regions as shown in Figure 2.
• the etching process is typically anisotropic such that a portion of oxide layer 17 remains adjacent to the vertical sides of gate 14. In some instances, a portion of the oxide layer 17 also remains above gate 14.
• the portion of the oxide layer 17 remaining adjacent to gate 14 is commonly referred to as a spacer, thus gate 14 is bounded by spacer regions 22, as shown in the cross-sectional illustration of Figure 2.
• a masking technique is used to expose only those areas which will be subjected to implantation.
• a n- region 23 is formed due to an n- implantation.
• a second masking step is utilized to define an area for performing the n+ implantation.
• the n+ region 24 resides within n- region 23 and this demarcation is especially important in the region proximate to the channel region underlying the gate 14.
• An annealing step is used to anneal the source and drain, which annealing step extends the n- and n+ regions further toward the channel region and in some instances, the n- region extends into the channel region, but not extending appreciably into the channel region underlying the gate 14.
• Spacers 22 are used to ensure that n- and n+ region 23 and 24 profiles are distinct and that the n- ,or both n- and n+ regions 23 and 24, do not extend appreciably into the channel region underlying the gate 14.
• two separate masks and masking steps are necessary to first implant the n- region 23 and a second step to implant the n+ region 24 in order to provide a separation of the n+ region from the channel region for the purpose of providing better source and drain isolation from the channel region.
• the n+ region is doped first, followed by the doping of the n-region.
• An advantage of the n+ being performed first is that ion channeling effects can be reduced slightly.
• the width of the region underlying each of the sidewall spacers 22 is commonly termed a "footprint".
• a footprint for one of the sidewall spacers 22 is shown by the footprint distance 27.
• the width of footprint 27 is a critical measurement for determining the extent of the horizontal penetration of n- region 23 in the substrate.
• a loose tolerance of the width of footprint 27 will necessarily result in a wide disparity of the extent of the penetration of n- region 23 and, hence, will more than likely impact the extent of the penetration of n+ region 24.
• the recognition of this variance is a key factor to the understanding the motivation behind the practice of the present invention. Therefore, it is desirable to maintain a small variance about a mean value specified for the width of the footprint 27.
• a variation in the slope of the sidewall spacer 22 causes a corresponding difference in the width of the footprint 27 and this variation in the slope is illustrated by slope (shown as dotted lines) 30 and 31.
• This difference in the width of the footprint 27 will cause n+ region 24 and/or n- region 23 to vary correspondingly (shown as doped regions 32 and 33) from the channel region underlying the gate 14.
• Any significant variation of the location of n+ region 24 and/or n- region 23, will ultimately affect the operating parameters of the device 10, such as threshold, punchthrough voltage, and source-drain leakage current.
• doped region 33 can extend significantly toward or even into the channel region. When region 33 extends appreciably into the channel region, it can present an undesirable, or even fatal (in the case of extremely short channel devices) , condition for the transistor.
• a semiconductor device of the present invention provides for the shortcomings in the prior art device in order to fabricate semiconductor devices utilizing submicron technology under 1.0 microns, more notably the use of 0.8, 0.5 and 0.35 micron and smaller technologies. Furthermore, it is appreciated that techniques have been suggested for improving steps for submicron "double doped" source and drain. One such technique utilizing an inverse T-gate structure for submicron LDD transistor is described in Huang et al.,"A Novel Submicron LDD Transistor with Inverse T-Gate Structure", IEEE IDEM, 1986, pp 742-745. Referring to Figure 4, a semiconductor device 40 of the preferred embodiment is shown. Device 40 is a MOS device having a substrate 41 which is typically comprised of silicon.
• Field oxide regions 42 are formed on the substrate 41 to localize the formation of circuit elements. Field oxide regions are shown in Figure 4 to isolate an area of device 40 for the formation of a given circuit element.
• a gate 44 is formed on substrate 41, which gate 41 is comprised of a polysilicon region 45 separated from the substrate 41 by a dielectric region 46.
• the dielectric region is typically comprised of an oxide, such as silicon dioxide (Si02) .
• oxide layer 47 is deposited over the device 40.
• oxide layer 47 is comprised of a conformally coated silicon dioxide (Si02) and is deposited by a well- known suitable chemical vapor deposition (CVD) process in order to obtain the conformal topology (conformal meaning that the deposited layer conforms to the underlying topology) .
• CVD oxide layer 47 is deposited to a thickness range of approximately 100-1000 angstroms.
• Si02 is preferred in that Si02 provides for minimal and controllable interface charge states afforded by Si02 on the underlying silicon.
• a CVD conformal nitride layer 48 is next deposited over the CVD oxide layer 47.
• Nitride layer 48 is deposited by CVD, such as by thermal decomposition of silane SiH4 and ammonia NH4 to a thickness of approximately 100-1000 angstroms.
• the nitride layer 48 of the preferred embodiment is comprised of silicon nitride Si3N4, although any disposable material with good etch selectivity against Si02 and Si can be used. Polysilicon can be used but is less preferred because of its conductance should any residue remain in the subsequent steps below.
• both layers 47 and 48 are selectively etched to expose portions of the substrate 41 between the FOX regions 42 and gate 44.
• the exposed substrate areas will later form the source and drain regions about gate 44.
• Nitride layer 48 is etched with high selectivity to Si02 first and then Si02 layer 47 is etched with high selectivity to both silicon and nitride. This technique allows for end-point detection and highly defined staircase structure shown in Figure 6. A dry anisotropic etch is used for both etch cycles.
• the nitride etch provides for a more uniform etch cycle than the oxide etch, as well as having a better anisotropic properties. Additionally, because of the use of the nitride etch, the FOX regions 42 are not etched away which allows for controlled isolation (field inversion voltage threshold) . It is to be noted that in the prior art device 10 of Figure 1, oxide etching of the oxide layer 17 can cause portions of the FOX regions 12 to be etched away if the oxide layer 17 is not uniform in thickness.
• nitride etch is used and, therefore, because of better selectivity, FOX regions 42 are not etched, at least not as severe as the oxide etch of the prior art device 10 and allowing for controlled isolation and controlled metal line parasitic capacitance.
• FIG. 6 it illustrates device 40 after the nitride etching cycle. Because of the anisotropic properties of nitride etch, a portion of the oxide 47 adjacent to the sidewalls of the gate 44 remains intact. This sidewall spacer 52 is wider at the base. proximate to the substrate 41, because a portion 53 of the nitride layer 48 remains adjacent to spacer 52 due to the conformal topology of the earlier formed layers 47 and 48 and the fact that the nitride appears thicker due to the anisotropic etch on the sharp sidewall definition of gate 44. Subsequently, the nitride portion 53 is selectively removed by either isotropic or anisotropic nitride etch.
• nitride remnant 53 After the removal of nitride remnant 53, only the sidewall spacer 52 remains adjacent to gate 44. Due to the earlier overlying nitride 53 protecting the underlying oxide spacer 52, a staircase shape is provided for the shape of sidewall spacers 52, as is shown in Figure 7.
• the thickness of the upper portion of spacer 52 is substantially equivalent to the thickness 51 of the lower portion of spacer 52.
• the thickness 50 of the spacer 52 adjacent to the gate 44 sidewall is determined by the thickness of conformal oxide layer 47.
• Figure 7 shows a footprint 54 of one oxide sidewall spacer 52.
• Footprint 54 can be separated by the disjunction 57 (which forms the staircase shape) of the surface of spacer 52 into footprint 55 and 56.
• Footprint 55 being determined by the width of the spacer 52 portion from the disjunction 57 to the gate 44 sidewall, which width being equivalent to the thickness 50.
• Footprint 56 being determined by the width of the spacer 52 portion from the disjunction 57 to the distal end of the lower portion of spacer 52.
• the measurement of footprint 54 and, hence, footprints 55 and 56 can be kept to a close tolerance.
• Those parameters being dependent on thickness of layer 47 and 48 and the nitride etch step described above. That is, the width of the footprint 55 is determined by the thickness of the deposition of oxide layer 47, while the width of footprint 56 is determined by the thickness of the deposition of the nitride layer 48. The sum of the thicknesses of the two layers 47 and 48, therefore, determines the width of the total footprint 54.
• the slope formation of the spacer 22 of the prior art device 10 tended to vary causing the footprint 27 to vary, such slope variations are reduced because the overlying nitride area 53 is not present.
• the underlying spacer regions 52 are protected and thereby maintain a sharp profile and a smaller variance of footprints 55 and 56.
• a mask layer 60 is formed, wherein the mask layer 60 retains exposed those areas where n- implantation is to occur.
• n- implantation is achieved by using one of a variety of well-known self- aligned implantation techniques.
• the energy of the n- implantation is selected to be of sufficient value in order to have the ions penetrate through the lower portion 58 of the spacer 52 to reach the portion of the substrate corresponding to footprint 56, yet not of a high enough value to penetrate gate 44 and upper portion 59 of spacer 52.
• the n- implantation step also implants the ions well into the exposed substrate 41.
• gate 44 and the upper portion 59 of the spacers 52, adjacent to the gate 44 provides for self-alignment during this implantation step.
• Each of the n- regions 63, formed on the opposites sides of gate 44 is formed in the substrate and extends into the substrate region underlying the lower portion 58 of the spacer 52 which is designated as footprint 56.
• the depth of the n- implant in the substrate underlying footprint 56 is not as deep as the implant region of the exposed substrate.
• FIG 9 it illustrates the subsequent n+ implantation step.
• a different masking layer need not be used for the n+ implant, unlike the case with the prior art device of Figure 2.
• the use of the same masking layer for both the n- and the n+ implants means that only one mask and masking step cycle need be used during fabrication of device 40 of the present invention.
• the same masking layer 60 is used for the n+ ion implant.
• the use of the same masking step for both implants reduces the step count and allows for cost and yield-risk reduction in manufacturing.
• the lower portion 58 functions as a mask to prevent appreciable penetration of the n+ ions into the substrate region underlying the spacer.
• the n+ source and drain regions 64 in the substrate 41 substantially extends from the edge of the footprint 56 toward the FOX regions 42.
• a "double doped" source and drain regions are present in which n+ region 64 is separated from the channel region underlying gate 44 by a n- region 63.
• the n+ region 64 can be implanted first and, then, subsequently followed by the n- implant to form n- region 63.
• performing the n+ implant may afford added control of the n- profile, since part of the region may be amorphized thus limiting ion channeling effects.
• FIG 10 it shows a subsequent annealing step in which the n- and n+ regions 63 and 64 are diffused further into the substrate, including diffusion toward the channel region.
• precise control can be obtained as to the extent of the horizontal diffusion of n- and n+ regions 63 and 64 toward the channel region.
• the n- region 63 can be extended to a position just underlying the sidewall of gate 44. This control allows turn-on characteristics and simultaneously provides for minimal overlap capacitance for source or drain to gate. That is, boundary of the n- region 63 diffuses from the footprint area 56 to footprint area 55, while the boundary of the n+ region 64 diffuses into the footprint area 56 (see Figure 7) during the annealing step.
• an equivalent technique can be used to provide for source and drain regions in a p-channel device.
• p-implantation is performed.
• p+ implant is used.
• either p- or p+ implant can be performed first.
• CMOS complementary-metal-oxide semiconductor
• n-channel device 40a which is equivalent to device 40 of Figure 9, is formed in the p-well 41a.
• a p+/p- mask layer 60b is formed, exposing the p-channel device area for implantation as is shown in Figure 14.
• a p- implant is performed according to the earlier described process.
• a p+ implant is achieved.
• the p-channel device 40b fabricated in the n-well 41b is equivalent to the earlier described device 40 of Figure 9, except that it is a p-channel device having p- and p+ implants.
• CMOS device 70 shown in Figure 16, having the n-channel and the p-channel devices fabricated according to the practice of the present invention.
• the CMOS device 70 being fabricated utilizing submicron technology, such as 0.8, 0.5, 0.35 and smaller micron technology. Again, either the n- or the n+, as well as the p- or the p+, implants can be performed first.
• a polysilicon layer 73 is formed above each of the exposed substrate areas.
• the formation and use of such "elevated polysilicon” (elevated poly) layer is well known and such techniques are described in Oh et al. , "A New MOSFET Structure with Self-Aligned Polysilicon Source and Drain Electrodes", IEEE Electron Device Letters, Vol. EDL-5, No.10, Oct. 1984, pp 400-402; and in Yamada et al., "Spread Source/Drain (SSD) MOSFET Using Selective Silicon Growth for 64Mbit DRAMs, IEEE IEDM, 1989, pp 35- 38.
• n- and n+ implants 63c and 64c are performed according to the earlier described steps in practicing the present invention.
• diffusion is achieved as earlier described to control the doping profiles under the foot region.
• salicidation is the formation of metal silicide on both the source and drain and/or the self-aligned gate regions
• a silicide forming metal such as titanium or cobalt for example
• the thickness of the lower portion 58c (foot portion of the staircase) of spacer 52c can be designed less than, equal to, or greater than the thickness of the polysilicon 73. Subsequent source/drain regions can then be formed in the polysilicon 73, as well as in the base substrate.
• CMOS device 77 is shown in which it is equivalent to the CMOS device 70 described in reference to Figure 16, except that the source and drain regions of both n-channel device and p-channel device elements 63d, 64d, 63e, 64e have the elevated poly 73a.
• a significant advantage of using an elevated poly technique is that the implant ions are implanted or deposited into the elevated poly prior to diffusing dopant into the substrate. Hence, implant damage and doping initially is contained primarily in the elevated poly and not in the actual single crystal substrate. This may decrease the source/drain to substrate capacitance and reduce junction leakage. Implantation into fine grain polysilicon elevated drains provides a fast lateral diffusion medium so that shadowing effects that normally exist by implanting past masking gates into crystalline silicon are overcome.
• polysilicon 73f is thicker than the lower portion (foot) of the spacer 52f. By making the lower portion of the spacer thinner than the elevated drains, one can selectively dope the n- regions.
• a depression 65 is formed between the spacer 52f and the polysilicon 73f.
• n- implant is performed at a controlled energy level, an n- region forms in the substrate substantially under the depression 65.
• the n+ implant is implanted at low energy into the elevated polysilicon and finally diffused into the substrate underlying the polysilicon 73f and to a limited extent into the substrate underlying the depression 65.
• a narrow n- pocket region 63f is formed between the n+ region 64f and the channel region.
• n- or n+ implant can be performed first. This technique is also applicable to p-channel devices as well.
• the resultant structure, with subsequent salicide etalization layer 74 is shown in Figure 21.

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