EP0508232B1 - Circuit électronique pour la mesure de périodes de temps courtes - Google Patents

Circuit électronique pour la mesure de périodes de temps courtes Download PDF

Info

Publication number
EP0508232B1
EP0508232B1 EP92105260A EP92105260A EP0508232B1 EP 0508232 B1 EP0508232 B1 EP 0508232B1 EP 92105260 A EP92105260 A EP 92105260A EP 92105260 A EP92105260 A EP 92105260A EP 0508232 B1 EP0508232 B1 EP 0508232B1
Authority
EP
European Patent Office
Prior art keywords
pulse
ring oscillator
inverters
electronic circuitry
osc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP92105260A
Other languages
German (de)
English (en)
Other versions
EP0508232A3 (en
EP0508232A2 (fr
Inventor
Augustin Braun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MSC MICROCOMPUTERS SYSTEMS COMPONENTS VERTRIEBS GmbH
Original Assignee
MSC MICROCOMPUTERS SYSTEMS COMPONENTS VERTRIEBS GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MSC MICROCOMPUTERS SYSTEMS COMPONENTS VERTRIEBS GmbH filed Critical MSC MICROCOMPUTERS SYSTEMS COMPONENTS VERTRIEBS GmbH
Publication of EP0508232A2 publication Critical patent/EP0508232A2/fr
Publication of EP0508232A3 publication Critical patent/EP0508232A3/de
Application granted granted Critical
Publication of EP0508232B1 publication Critical patent/EP0508232B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an ac

Definitions

  • the invention relates to an electronic circuit for measuring a short time interval, which is in the form of an electrical measuring pulse.
  • time difference meters it is common to design time difference meters as high-frequency counters or analog circuits using a "dual slope" method. If short time intervals are to be measured with a high degree of accuracy, correspondingly high counting frequencies are required for high-frequency counters. A desired accuracy of 500 picoseconds, for example, already requires a frequency of at least 2 gigahertz. Such high frequencies can, however, only be achieved with the very fastest ECL technologies, which is associated with corresponding design outlay, for example for housing and cooling, and therefore leads overall to a very expensive device.
  • the object of the present invention is therefore to provide a time difference meter of simple circuitry design, with which short time intervals can be measured with the greatest accuracy.
  • an electronic circuit consisting of a ring oscillator comprising a chain of inverters connected in series, a controllable logic element which switches the ring oscillator on or off in response to the measuring pulse representing the time interval, and at least one pulse counter which detects the Number of whole clock periods of the oscillating ring oscillator one of the inverters counts, further a phase indicator that records the phase position of the ring oscillator when it is switched off, and finally an arithmetic-logic unit connected to the pulse counter and the phase indicator, which uses the recorded phase position and the count of the pulse counter to measure the measurement result as a multiple of the running time of a Inverters outputs.
  • the core of the proposed circuit is the controlled ring oscillator. This is started with the positive edge of the measuring pulse in phase synchronization with the measuring pulse and then oscillates at its natural frequency, which results from the running times of the series-connected inverter stages and their number.
  • the pulse counter counts the entire periods of the oscillating ring oscillator as long as the measuring pulse is present.
  • the falling edge of the measuring pulse which corresponds to the end of the time interval to be measured, switches off the ring oscillator via the controllable logic element.
  • the phase position of the last clock period at the moment of the end of the measuring pulse is recorded using the phase indicator provided. All necessary information is thus available in the pulse counter and in the phase indicator in order to exactly determine the length of the measuring pulse or the time interval to be measured with an accuracy that corresponds to the running time of an inverter.
  • the accuracy of the proposed electronic time difference meter is determined by the running time of the inverter used.
  • ASICs user-specific integrated circuits
  • CMOS complementary metal-oxide-semiconductor
  • inverter runtimes in the range of 200 pico-seconds can be easily achieved today.
  • the proposed measuring circuit is thus far superior to conventional high-frequency counters; in addition, it can be produced very inexpensively on a single chip. Another advantage is the low current consumption of the circuit.
  • the inverter chain must not be too short, otherwise the amplitude of the ring oscillator will not reach its full height in the first periods, which could also lead to incorrect counts in the pulse counters.
  • a NAND gate offers itself as a logic element for switching the ring oscillator on and off.
  • the running time of a NAND element in the technology used here is about twice as long as the running time of an inverter stage.
  • the controllable element therefore comprises, in addition to the NAND gate, two additional inverters which divide the running time of the NAND gate into two inverter running times.
  • the ring oscillator 14 comprises inverters. Together with the two additional inverters on the NAND gate, there are a total of 16 inverter stages connected in series, which is a power of two, so that the subsequent logical arithmetic operations are simplified.
  • the switching off of the ring oscillator caused by the end of the measuring pulse can occur in any phase position of its clock. If there is only a single pulse counter, the measuring pulse end could just fall on a counting edge under unfavorable circumstances and the counter would cause setup / hold time violations, which could result in the counter reading being incorrect. An error of 1 would mean, for example, with 16 total inverter stages, a measurement inaccuracy of 32 inverter run times. In an advantageous further development of the circuit according to the invention, two parallel pulse counters are therefore provided, each of which is operated offset by about half a clock period. This ensures that at least one of the two pulse counters is always switched off in a defined manner.
  • each with a counter clock offset by about half a clock period are preferably connected to the outputs of two successive inverters.
  • the two pulse counters are each preceded by a clock generator which is designed as a controllable divider.
  • These clock generators have the task of converting the periodic clock of the ring oscillator, which is tapped off at the output of the respective inverter stage, into a counting pulse with a precisely known number of edges.
  • the clock generators preferably each comprise a flip-flop, the clock input of which is connected to the output of an inverter of the ring oscillator and the output of which acts on the input of the associated pulse counter, as well as a controllable inverter, at the input of which the measuring pulse is applied and whose output is connected to the data input of the Flip-flops is connected.
  • An exclusive-or gate is expediently used as the controllable inverter, which causes a counting pulse with half the clock rate to be emitted at the output of the flip-flop, as long as the measuring pulse is present on the input side.
  • the transit times that are unavoidable due to the exclusive-OR element can be compensated for by a delay section with a corresponding transit time upstream of the clock input of the flip-flop.
  • the phase indicator preferably consists of a memory chain and an evaluation logic.
  • the memory chain comprises the same number of memory elements as existing inverters, each memory element being assigned to exactly one inverter and storing its logic state when the ring oscillator is switched off.
  • the associated evaluation logic compresses the contents of the memory chain into a number representing the phase position of the last clock period of the ring oscillator and additionally detects the logic state of the first memory element.
  • the phase position of the last clock period of the ring oscillator at the moment of switching off is recorded by the falling edge of the measuring pulse. Based on the "frozen" last phase position and the logic value of the first memory element, it can be decided which of the two pulse counters contains the correct count.
  • An embodiment is particularly preferred in which the memory elements of the memory chain are D flip-flops, the data inputs of which are connected to the outputs of the associated inverters and the measuring pulse is applied to the clock inputs.
  • the measuring circuit implemented as an integrated CMOS circuit in FIG. 1 essentially consists of a ring oscillator OSC, two pulse counters C1, C2 with associated clock generators G1, G2, a phase indicator consisting of a memory chain SPK and memory elements S1 - S16, and an arithmetic-logic unit ALU.
  • the ring oscillator OSC is preceded by a NAND gate NA as a controllable logic element, the running time of which is divided into two inverters I1, I2.
  • the measuring pulse whose length is to be measured is present at the input of the NAND gate NA.
  • Downstream of the NAND gate NA is a chain of 14 inverters I3-I16 arranged one behind the other.
  • Two pulse counters C1 and C2 are provided here, each of which is preceded by a clock generator G1 or G2.
  • the input of the clock generator G1 is connected to the output of the inverter I10, while the input of the second clock generator G2 is connected to the output of the subsequent inverter I11.
  • the memory chain SPK comprises 16 identical memory elements S1-S 16, which are designed here as D flip-flops, with exactly one inverter I1-I 16 being assigned to each memory element S1-S 16.
  • the clock input of the flip-flop FL is connected to the output of the corresponding inverter I10 or I11 of the ring oscillator OSC (see FIG. 1); its output Q acts directly on the associated pulse counter C1 or C2, which is constructed in the usual way from a chain of further D flip-flops.
  • the exclusive-OR gate EX is used as a controllable inverter, one input A of which has the measuring pulse applied, the other input B of which has the output Q of the flip-flop FL is connected, and its output acts directly on the data input D of the flip-flop FL.
  • the clock input of the flip-flop FL is preceded by a correspondingly dimensioned delay line D2.
  • the measuring circuit works as follows:
  • the ring oscillator OSC With the rising edge of the measuring pulse, the length of which is to be determined exactly, the ring oscillator OSC is started in phase synchronization via the NAND gate NA. This then oscillates with its natural frequency, which results from the running times of the inverters I1-I16 and their number, until the falling edge of the measuring pulse switches it off again.
  • Figure 3 shows the clock periods of the ring oscillator OSC during the time interval T2 - T1, which corresponds to the length of the measuring pulse.
  • the ring oscillator OSC oscillates, its entire clock periods are counted by the pulse counters C1 and C2.
  • the clock signals tapped at the outputs of the inverters I10 and I11 of the ring oscillator OSC are converted into a count signal with half the number of pulses or double the pulse width.
  • the transit time D1 of the measuring pulse up to the data input D of the flip-flop FL is compensated by the delay line D2 to be run through in parallel by the clock signal so that the measuring pulse and the clock signal arrive at the flip-flop FL in phase synchronization.
  • the falling edge of the measuring pulse switches off the clock generators G1 and G2 - and thus the connected pulse counters C1, C2.
  • the current state of the inverter chain which represents the phase position of the last clock period, is transferred to the memory elements S1-S16 of the memory chain SPK assigned to each inverter I1-I16 carry.
  • the evaluation logic LOG compresses the contents of the memory chain SPK into a five-bit number, which indicates the phase position at which the ring oscillator OSC was switched off.
  • the arithmetic-logic unit ALU can now use the information supplied by the evaluation logic LOG to check which phase position has been switched off under defined conditions, which of the two pulse counters C1 and C2.
  • the arithmetic-logic unit ALU then calculates the measurement result in the form of a number from the count of the selected pulse counter C1 or C2 and the recorded phase position at the switch-off time and the logic state of the first memory element S1, which represents the length of the measurement pulse as a multiple of the running time of one of the inverters I1 - I16 indicates.
  • the length of the time interval T2 - T1 between the rising and falling edge of the measuring pulse which is thus determined up to an inverter running time, can then be further processed.
  • the running times of the inverters can vary from chip to chip and are also subject to fluctuations in temperature and voltage, it is necessary to carry out calibrations before starting up the measuring circuit and also during operation. This can be done, for example, by placing two measuring pulses of known length on the measuring circuit and by simple arithmetic obtaining a calibration curve with the aid of which the later measured values can be converted into time differences.
  • the arithmetic required for this can be implemented by downstream processors of a simple type.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Unknown Time Intervals (AREA)

Claims (13)

  1. Circuit électronique pour la mesure d'un bref intervalle de temps, représenté par une impulsion de mesure électrique, caractérisé par:
    - un oscillateur annulaire (OSC), composé d'une chaîne d'inverseurs (I3 - I16) montés les uns derrière les autres et d'un élément logique contrôlé, qui connecte et déconnecte l'oscillateur annulaire (OSC) en réponse à l'impulsion de mesure,
    - un compteur d'impulsions (C1), au moins, qui compte le nombre de toutes les périodes d'horloge de l'oscillateur annulaire (OSC), oscillant, sur l'un des inverseurs (I10),
    - un indicateur de phase, qui fixe l'état de phase de la dernière période d'horloge de l'oscillateur annulaire (OSC) au moment de la déconnexion,
    - une unité arithmétique et logique (ALU), reliée au compteur d'impulsions (C1) et à l'indicateur de phase, et qui délivre le résultat de mesure sous forme d'un multiple du temps de propagation d'un inverseur (I1 - I16), à l'aide de la position de phase fixée et de l'état de comptage du compteur d'impulsions (C1).
  2. Circuit électronique suivant la revendication 1, caractérisé en ce que l'oscillateur annulaire (OSC) comporte un nombre suffisant d'inverseurs (I3 - I16), pour garantir un amorçage défini des oscillations.
  3. Circuit électronique suivant l'une des revendications 1 ou 2, caractérisé en ce que l'élément contrôlé comporte une porte NAND (NA) et deux inverseurs supplémentaires (I1, I2).
  4. Circuit électronique suivant les revendications 2 et 3, caractérisé en ce que l'oscillateur annulaire (OSC) comporte 14 inverseurs (I3 - I16).
  5. Circuit électronique suivant l'une des revendications 1 à 4, caractérisé en ce que:
    - deux compteurs d'impulsions (C1, C2) sont prévus, le premier (C1) comptant le nombre de toutes les périodes d'horloge de l'oscillateur annulaire (OSC), oscillant, sur l'un des inverseurs (I10), et le second compteur (C2) comptant le nombre des périodes d'horloge de l'oscillateur annulaire (OSC) sur l'un des inverseurs suivants (I11),
    - l'unité arithmétique et logique (ALU) est reliée aux deux compteurs d'impulsions (C1, C2) et décide, à l'aide de l'état de phase fixée par l'indicateur de phase, lequel des deux compteurs d'impulsions (C1) ou (C2) comporte l'état de comptage correct.
  6. Circuit électronique suivant la revendication 5, caractérisé en ce que les compteurs d'impulsions (C1) et (C2) sont reliés aux sorties de deux inverseurs successifs (I10, I11).
  7. Circuit électronique suivant l'une des revendications 5 ou 6, caractérisé en ce qu'un générateur de rythme (G1, G2), réalisé sous forme de diviseur de fréquence contrôlé, est respectivement monté en amont des compteurs d'impulsions (C1) et (C2).
  8. Circuit électronique suivant la revendication 7, caractérisé en ce que les générateurs de rythme (G1, G2) comportent:
    - un flip-flop D (FL), dont l'entrée impulsions est reliée à la sortie d'un inverseur (I10, I11) de l'oscillateur annulaire (OSC), et dont la sortie (Q) agit sur l'entrée du compteur d'impulsions (C1, C2) correspondant,
    - un inverseur contrôlé, à l'entrée (A) duquel s'applique l'impulsion de mesure, et dont la sortie est reliée à l'entrée données (D) du flip-flop (FL).
  9. Circuit électronique suivant la revendication 8, caractérisé en ce que l'inverseur contrôlé est un élément OU- exclusif (EX), sur l'une des entrées (A) duquel s'applique l'impulsion de mesure, dont l'autre entrée (B) est reliée à la sortie (Q) du flip-flop D (FL), et qui agit côté sortie sur l'entrée données (D) du flip-flop D (FL).
  10. Circuit électronique suivant la revendication 9, caractérisé en ce qu'une ligne à retard (D2), qui compense le temps de propagation (D1) de l'impulsion de mesure jusqu'à l'entrée données (D) du flip-flop D, est montée en amont de l'entrée impulsions du flip-flop D (FL).
  11. Circuit électronique suivant l'une des revendications 1 à 10, caractérisé en ce que l'indicateur de phase comporte:
    - une chaîne de mémorisation (SPK) avec des éléments de mémoire (S1 - S16) en nombre égal à celui des inverseurs (I1 - I16) prévus, chaque élément de mémoire étant exactement associé à un inverseur, et son état logique étant mémorisé au moment de la déconnexion,
    - une logique d'évaluation (LOG), qui comprime le contenu de la chaîne de mémorisation (SPK) en un chiffre, représentant l'état de phase de la dernière période d'horloge de l'oscillateur annulaire (OSC), et détermine en sus l'état logique du premier élément de mémoire (S1).
  12. Circuit électronique suivant la revendication 11, caractérisé en ce que les éléments de mémoire (S1 - S16) de la chaîne de mémorisation (SPK) sont des flips-flops D, dont les entrées données sont reliées aux sorties des inverseurs (I1 - I16) correspondants, et sur les entrées impulsions desquels s'applique l'impulsion de mesure.
  13. Circuit électronique suivant l'une des revendications 1 à 12, caractérisé en ce qu'il est réalisé sous forme de circuit intégré CMOS.
EP92105260A 1991-04-09 1992-03-27 Circuit électronique pour la mesure de périodes de temps courtes Expired - Lifetime EP0508232B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4111350A DE4111350C1 (fr) 1991-04-09 1991-04-09
DE4111350 1991-04-09

Publications (3)

Publication Number Publication Date
EP0508232A2 EP0508232A2 (fr) 1992-10-14
EP0508232A3 EP0508232A3 (en) 1994-05-25
EP0508232B1 true EP0508232B1 (fr) 1996-03-06

Family

ID=6429076

Family Applications (1)

Application Number Title Priority Date Filing Date
EP92105260A Expired - Lifetime EP0508232B1 (fr) 1991-04-09 1992-03-27 Circuit électronique pour la mesure de périodes de temps courtes

Country Status (2)

Country Link
EP (1) EP0508232B1 (fr)
DE (2) DE4111350C1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10119080B4 (de) * 2001-04-19 2005-05-04 Acam-Messelectronic Gmbh Verfahren und Schaltanordnung zur Widerstandsmessung
DE102007032227A1 (de) 2006-02-14 2009-01-22 Smartlogic Gmbh Elektronische Schaltung zur Messung eines Zeitintervalls

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2296142B (en) * 1994-12-16 1998-03-18 Plessey Semiconductors Ltd Circuit arrangement for measuring a time interval
DE19620736C1 (de) * 1996-04-03 1997-05-28 Hydrometer Gmbh Elektronische Schaltung zum hochauflösenden Messen von Zeiten
US6369563B1 (en) * 1996-11-23 2002-04-09 Mts Systems Corporation Method for high resolution measurement of a position
EP0885373B1 (fr) * 1996-12-19 2003-04-16 Mts Systems Corporation Procede de mesure haute resolution d'un intervalle de temps
JP3048962B2 (ja) * 1997-06-20 2000-06-05 日本電気アイシーマイコンシステム株式会社 時間測定方法及び時間測定システム
US6641315B2 (en) 1997-07-15 2003-11-04 Silverbrook Research Pty Ltd Keyboard
US6557977B1 (en) 1997-07-15 2003-05-06 Silverbrook Research Pty Ltd Shape memory alloy ink jet printing mechanism
US6648453B2 (en) 1997-07-15 2003-11-18 Silverbrook Research Pty Ltd Ink jet printhead chip with predetermined micro-electromechanical systems height
US6886917B2 (en) 1998-06-09 2005-05-03 Silverbrook Research Pty Ltd Inkjet printhead nozzle with ribbed wall actuator
US6445326B1 (en) * 2000-06-22 2002-09-03 Xyron Corporation High speed precision analog to digital convertor
DE102005024648B4 (de) * 2005-05-25 2020-08-06 Infineon Technologies Ag Elektrische Schaltung zum Messen von Zeiten und Verfahren zum Messen von Zeiten
EP1964261B1 (fr) 2005-12-12 2011-03-02 Nxp B.V. Circuit électrique et procédé pour générer un signal d'horloge
JP2009518990A (ja) * 2005-12-12 2009-05-07 エヌエックスピー ビー ヴィ 電気カウンタ回路
EP3339985B1 (fr) 2016-12-22 2019-05-08 ams AG Convertisseur temps-numérique et procédé de conversion
EP3772640B1 (fr) 2019-08-09 2022-06-22 Sciosense B.V. Circuit électrique pour mesure de contrainte

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2132043A (en) * 1982-12-22 1984-06-27 Philips Electronic Associated Timer circuit
FR2564216B1 (fr) * 1984-05-11 1986-10-24 Centre Nat Rech Scient Convertisseur temps-numerique ultrarapide
GB8717173D0 (en) * 1987-07-21 1987-08-26 Logic Replacement Technology L Time measurement apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10119080B4 (de) * 2001-04-19 2005-05-04 Acam-Messelectronic Gmbh Verfahren und Schaltanordnung zur Widerstandsmessung
DE102007032227A1 (de) 2006-02-14 2009-01-22 Smartlogic Gmbh Elektronische Schaltung zur Messung eines Zeitintervalls
DE102007032227B4 (de) * 2006-02-14 2009-10-29 Smartlogic Gmbh Elektronische Schaltung zur Messung eines Zeitintervalls

Also Published As

Publication number Publication date
DE4111350C1 (fr) 1992-09-10
EP0508232A3 (en) 1994-05-25
EP0508232A2 (fr) 1992-10-14
DE59205532D1 (de) 1996-04-11

Similar Documents

Publication Publication Date Title
EP0508232B1 (fr) Circuit électronique pour la mesure de périodes de temps courtes
DE102008046831B4 (de) Ereignisgesteuerte Zeitintervallmessung
DE2838549A1 (de) Impulsbreitenmesschaltung
DE2948330C2 (de) Verfahren und Vorrichtung zur Frequenzmessung
EP0173833B1 (fr) Montage et procédé pour la mesure et la digitalisation d'une résistance
DE2848159A1 (de) Taktpulspruefeinrichtung
DE69320286T2 (de) Baudratengenerator mit niedriger Leistung
DE102005024648A1 (de) Elektrische Schaltung zum Messen von Zeiten und Verfahren zum Messen von Zeiten
EP0017251B1 (fr) Dispositif de commutation pour déterminer la durée moyenne de la période d'un signal périodique
EP0585806B1 (fr) Comparateur de phase numérique et boucle à verrouillage de phase
DE3234575A1 (de) Verfahren und anordnung zum messen von frequenzen
DE2943227C1 (de) Vorrichtung zum Messen der Frequenz eines Impulsgenerators
DE2552079A1 (de) Schaltungsanordnung zur bestimmung des mittelwertes einer frequenz
DE3426420C2 (fr)
DE3536019C2 (fr)
DE2543342A1 (de) Schaltungsanordnung und verfahren zur messung der genauigkeit eines zeitmessers
DE19620736C1 (de) Elektronische Schaltung zum hochauflösenden Messen von Zeiten
DE2613930C3 (de) Digitaler Phasenregelkreis
DE2704317B2 (de) Gangmessgerät für Uhren
EP0527995B1 (fr) Circuit electrique de mesure de la frequence de signaux laser a effet doppler
DE2847626C2 (de) Vorrichtung zur Bestimmung der Dichte von Flüssigkeiten und Gasen
DE69504000T2 (de) Zeitintervalmessvorrichtung
DE69627536T2 (de) Verfahren zur hochauflösenden messung einer zeitspanne
DE2363873A1 (de) Anordnung zur dichtebestimmung
DE3219283C2 (de) Mittelwert-Frequenzmesser

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): CH DE FR GB IT LI

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): CH DE FR GB IT LI

17P Request for examination filed

Effective date: 19940826

17Q First examination report despatched

Effective date: 19950619

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

ITF It: translation for a ep patent filed
AK Designated contracting states

Kind code of ref document: B1

Designated state(s): CH DE FR GB IT LI

ET Fr: translation filed
REG Reference to a national code

Ref country code: CH

Ref legal event code: NV

Representative=s name: TROESCH SCHEIDEGGER WERNER AG

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 19960308

REF Corresponds to:

Ref document number: 59205532

Country of ref document: DE

Date of ref document: 19960411

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20010323

Year of fee payment: 10

Ref country code: GB

Payment date: 20010323

Year of fee payment: 10

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020327

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20020327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20021129

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20050327

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 20090325

Year of fee payment: 18

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20090328

Year of fee payment: 18

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100331

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20101001

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100331