EP0508232B1 - Electronic circuit for measuring short time-intervals - Google Patents

Description

The invention relates to an electronic circuit for measuring a short time interval, which is in the form of an electrical measuring pulse.

It is common to design time difference meters as high-frequency counters or analog circuits using a "dual slope" method. If short time intervals are to be measured with a high degree of accuracy, correspondingly high counting frequencies are required for high-frequency counters. A desired accuracy of 500 picoseconds, for example, already requires a frequency of at least 2 gigahertz. Such high frequencies can, however, only be achieved with the very fastest ECL technologies, which is associated with corresponding design outlay, for example for housing and cooling, and therefore leads overall to a very expensive device.

The object of the present invention is therefore to provide a time difference meter of simple circuitry design, with which short time intervals can be measured with the greatest accuracy.

The object is achieved by an electronic circuit consisting of a ring oscillator comprising a chain of inverters connected in series, a controllable logic element which switches the ring oscillator on or off in response to the measuring pulse representing the time interval, and at least one pulse counter which detects the Number of whole clock periods of the oscillating ring oscillator one of the inverters counts, further a phase indicator that records the phase position of the ring oscillator when it is switched off, and finally an arithmetic-logic unit connected to the pulse counter and the phase indicator, which uses the recorded phase position and the count of the pulse counter to measure the measurement result as a multiple of the running time of a Inverters outputs.

The core of the proposed circuit is the controlled ring oscillator. This is started with the positive edge of the measuring pulse in phase synchronization with the measuring pulse and then oscillates at its natural frequency, which results from the running times of the series-connected inverter stages and their number.

The pulse counter counts the entire periods of the oscillating ring oscillator as long as the measuring pulse is present. The falling edge of the measuring pulse, which corresponds to the end of the time interval to be measured, switches off the ring oscillator via the controllable logic element. The phase position of the last clock period at the moment of the end of the measuring pulse is recorded using the phase indicator provided. All necessary information is thus available in the pulse counter and in the phase indicator in order to exactly determine the length of the measuring pulse or the time interval to be measured with an accuracy that corresponds to the running time of an inverter.

The accuracy of the proposed electronic time difference meter is determined by the running time of the inverter used. In modern, user-specific integrated circuits (ASICs) in CMOS technology, inverter runtimes in the range of 200 pico-seconds can be easily achieved today. The proposed measuring circuit is thus far superior to conventional high-frequency counters; in addition, it can be produced very inexpensively on a single chip. Another advantage is the low current consumption of the circuit.

To ensure that the ring oscillator swings out safely, the inverter chain must not be too short, otherwise the amplitude of the ring oscillator will not reach its full height in the first periods, which could also lead to incorrect counts in the pulse counters.

In the CMOS technology preferred here, a NAND gate offers itself as a logic element for switching the ring oscillator on and off. The running time of a NAND element in the technology used here is about twice as long as the running time of an inverter stage. The controllable element therefore comprises, in addition to the NAND gate, two additional inverters which divide the running time of the NAND gate into two inverter running times.

In a preferred embodiment, the ring oscillator 14 comprises inverters. Together with the two additional inverters on the NAND gate, there are a total of 16 inverter stages connected in series, which is a power of two, so that the subsequent logical arithmetic operations are simplified.

The switching off of the ring oscillator caused by the end of the measuring pulse can occur in any phase position of its clock. If there is only a single pulse counter, the measuring pulse end could just fall on a counting edge under unfavorable circumstances and the counter would cause setup / hold time violations, which could result in the counter reading being incorrect. An error of 1 would mean, for example, with 16 total inverter stages, a measurement inaccuracy of 32 inverter run times. In an advantageous further development of the circuit according to the invention, two parallel pulse counters are therefore provided, each of which is operated offset by about half a clock period. This ensures that at least one of the two pulse counters is always switched off in a defined manner. Which counter contains the correct count after the ring oscillator has been switched off is determined by the arithmetic-logic unit using the decided phase position of the ring oscillator in the phase indicator. In principle, however, the circuit according to the invention also works with only one pulse counter.

In order to operate the two pulse counters, each with a counter clock offset by about half a clock period, these are preferably connected to the outputs of two successive inverters.

In a further development of the invention, the two pulse counters are each preceded by a clock generator which is designed as a controllable divider. These clock generators have the task of converting the periodic clock of the ring oscillator, which is tapped off at the output of the respective inverter stage, into a counting pulse with a precisely known number of edges.

The clock generators preferably each comprise a flip-flop, the clock input of which is connected to the output of an inverter of the ring oscillator and the output of which acts on the input of the associated pulse counter, as well as a controllable inverter, at the input of which the measuring pulse is applied and whose output is connected to the data input of the Flip-flops is connected. An exclusive-or gate is expediently used as the controllable inverter, which causes a counting pulse with half the clock rate to be emitted at the output of the flip-flop, as long as the measuring pulse is present on the input side.

The transit times that are unavoidable due to the exclusive-OR element can be compensated for by a delay section with a corresponding transit time upstream of the clock input of the flip-flop.

The phase indicator preferably consists of a memory chain and an evaluation logic. The memory chain comprises the same number of memory elements as existing inverters, each memory element being assigned to exactly one inverter and storing its logic state when the ring oscillator is switched off. The associated evaluation logic compresses the contents of the memory chain into a number representing the phase position of the last clock period of the ring oscillator and additionally detects the logic state of the first memory element. In the chain of memory elements, the phase position of the last clock period of the ring oscillator at the moment of switching off is recorded by the falling edge of the measuring pulse. Based on the "frozen" last phase position and the logic value of the first memory element, it can be decided which of the two pulse counters contains the correct count.

An embodiment is particularly preferred in which the memory elements of the memory chain are D flip-flops, the data inputs of which are connected to the outputs of the associated inverters and the measuring pulse is applied to the clock inputs.

When the circuit is implemented as an integrated CMOS circuit, so-called "matching effects" can be exploited, since all the logic functional elements present on the chip have practically the same dynamic behavior and are hardly subject to any scattering. This results in a further increase in measuring accuracy or is a basic prerequisite for high-precision measurements.

Figur 1

ein Schaltschema der Meßschaltung;

Figur 2

ein Schaltbild der in der Schaltung nach Figur 1 verwendeten Taktgeneratoren;

Figur 3

den an die Meßschaltung von Figur 1 angelegten Meßpuls über den zugehörigen Taktperioden des Ringoszillators, in einem Zeit-Spannungs-Diagramm.

An embodiment of the measuring circuit according to the invention is explained below with reference to the accompanying drawings. Show it:

Figure 1

a circuit diagram of the measuring circuit;

Figure 2

a circuit diagram of the clock generators used in the circuit of Figure 1;

Figure 3

the measuring pulse applied to the measuring circuit of Figure 1 over the associated clock periods of the ring oscillator, in a time-voltage diagram.

The measuring circuit implemented as an integrated CMOS circuit in FIG. 1 essentially consists of a ring oscillator OSC, two pulse counters C1, C2 with associated clock generators G1, G2, a phase indicator consisting of a memory chain SPK and memory elements S1 - S16, and an arithmetic-logic unit ALU.

The ring oscillator OSC is preceded by a NAND gate NA as a controllable logic element, the running time of which is divided into two inverters I1, I2. The measuring pulse whose length is to be measured is present at the input of the NAND gate NA. Downstream of the NAND gate NA is a chain of 14 inverters I3-I16 arranged one behind the other.

Two pulse counters C1 and C2 are provided here, each of which is preceded by a clock generator G1 or G2. The input of the clock generator G1 is connected to the output of the inverter I10, while the input of the second clock generator G2 is connected to the output of the subsequent inverter I11.

The memory chain SPK comprises 16 identical memory elements S1-S 16, which are designed here as D flip-flops, with exactly one inverter I1-I 16 being assigned to each memory element S1-S 16.

According to FIG. 2, the clock generators G1 and G2, respectively upstream of the pulse counters C1 and C2, each contain a D flip-flop FL and an exclusive-OR gate EX. The clock input of the flip-flop FL is connected to the output of the corresponding inverter I10 or I11 of the ring oscillator OSC (see FIG. 1); its output Q acts directly on the associated pulse counter C1 or C2, which is constructed in the usual way from a chain of further D flip-flops.

The exclusive-OR gate EX is used as a controllable inverter, one input A of which has the measuring pulse applied, the other input B of which has the output Q of the flip-flop FL is connected, and its output acts directly on the data input D of the flip-flop FL. In order to compensate for the transit time D1 on its way via the exclusive-OR gate EX to the data input D of the flip-flop FL, the clock input of the flip-flop FL is preceded by a correspondingly dimensioned delay line D2.

The measuring circuit works as follows:

With the rising edge of the measuring pulse, the length of which is to be determined exactly, the ring oscillator OSC is started in phase synchronization via the NAND gate NA. This then oscillates with its natural frequency, which results from the running times of the inverters I1-I16 and their number, until the falling edge of the measuring pulse switches it off again. Figure 3 shows the clock periods of the ring oscillator OSC during the time interval T₂ - T₁, which corresponds to the length of the measuring pulse.

As long as the ring oscillator OSC oscillates, its entire clock periods are counted by the pulse counters C1 and C2. In the upstream clock generators G1 and G2 (see FIG. 2), the clock signals tapped at the outputs of the inverters I10 and I11 of the ring oscillator OSC are converted into a count signal with half the number of pulses or double the pulse width. The transit time D1 of the measuring pulse up to the data input D of the flip-flop FL is compensated by the delay line D2 to be run through in parallel by the clock signal so that the measuring pulse and the clock signal arrive at the flip-flop FL in phase synchronization. The falling edge of the measuring pulse switches off the clock generators G1 and G2 - and thus the connected pulse counters C1, C2.

After switching off the ring oscillator OSC in response to the negative edge of the measuring pulse, the current state of the inverter chain, which represents the phase position of the last clock period, is transferred to the memory elements S1-S16 of the memory chain SPK assigned to each inverter I1-I16 carry. The evaluation logic LOG compresses the contents of the memory chain SPK into a five-bit number, which indicates the phase position at which the ring oscillator OSC was switched off.

The arithmetic-logic unit ALU can now use the information supplied by the evaluation logic LOG to check which phase position has been switched off under defined conditions, which of the two pulse counters C1 and C2. The arithmetic-logic unit ALU then calculates the measurement result in the form of a number from the count of the selected pulse counter C1 or C2 and the recorded phase position at the switch-off time and the logic state of the first memory element S1, which represents the length of the measurement pulse as a multiple of the running time of one of the inverters I1 - I16 indicates.

The length of the time interval T₂ - T₁ between the rising and falling edge of the measuring pulse, which is thus determined up to an inverter running time, can then be further processed.

Since the running times of the inverters can vary from chip to chip and are also subject to fluctuations in temperature and voltage, it is necessary to carry out calibrations before starting up the measuring circuit and also during operation. This can be done, for example, by placing two measuring pulses of known length on the measuring circuit and by simple arithmetic obtaining a calibration curve with the aid of which the later measured values can be converted into time differences. The arithmetic required for this can be implemented by downstream processors of a simple type.

List of reference numbers

OSC

Ring oscillator

N / A

Nand gate

I1 - I16

Inverter

C1, C2

Pulse counter

G1, G2

Clock generators

FL

Flip-flop (from G1, G2)

D

Data input (from FL)

Q

Output (from FL)

EX

Exclusive OR link (from G1, G2)

A, B

Inputs (from EX)

D1

running time

D2

Delay stretch

SPK

Storage chain

S1 - S16

Storage elements

LOG

Evaluation logic

ALU

arithmetic-logical unit

Claims (13)

1. Electronic circuitry for measuring a short time interval present in the form of an electrical measurement pulse, characterised by:

   - a ring oscillator (OSC) consisting of a chain of serially connected inverters (I3-I16) and a controllable logic member which switches the ring oscillator (OSC) on and off in response to the measurement pulse;

   - at least one pulse counter (C1) which counts the number of the complete clock periods of the oscillating ring oscillator (OSC) at one of the inverters (I10);

   - a phase indicator which registers the phase angle of the last clock period of the ring oscillator (OSC) at the instant of switching off;

   - an arithmetical-logical unit (ALU) connected with the pulse counter (C1) and the phase indicator which outputs the measurement result as a multiple of the running time of an inverter (I1-I16) by way of the registered phase angle and the state of the pulse counter (C1).
2. Electronic circuitry according to claim 1, characterised in that
   the ring oscillator (OSC) has a sufficient number of inverters (I3-I16) in order to assure a defined start of the oscillation.
3. Electronic circuitry according to claim 1 or claim 2, characterised in that
   the controllable member consists of a NAND-gate (NA) and two additional inverters (I1, I2).
4. Electronic circuitry according to claims 2 and 3, characterised in that
   the ring oscillator (OSC) includes fourteen inverters (I3-I16).
5. Electronic circuity according to any one of claims 1 to 4, characterised in that

   - two pulse counters (C1, C2) are provided, wherein the first one (C1) counts the number of the complete clock periods of the oscillating ring oscillator (OSC) at one of the inverters (I10) and the second pulse counter (C2) counts the number of clock periods of the ring oscillator (OSC) at one of the next succeeding inverters (I11);

   - the arithmetical-logical unit (ALU) is connected with both pulse counters (C1, C2) and decides by way of the phase angle registered by the phase indicator which of the two pulse counters (C1) or (C2) contains the correct state of count.
6. Electronic circuitry according to claim 5, characterised in that
   the pulse counters (C1) and (C2) are connected with the outputs of two successive inverters (I10, I11).
7. Electronic circuitry according to one of claims 5 or 6, characterised in that
   a respective clock generator (G1, G2) formed as a controllable part is connected before the pulse counters (C1) and (C2).
8. Electronic circuitry according to claim 7, characterised in that
   the timing generators (Gl, G2) contain:

   - a D-type (delay) flip-flop (FL) whose clock input is connected with the output of an inverter (I10, I11) of the ring oscillator (OSC) and whose output (Q) operates on the input of the associated pulse counter (C1, C2);

   - a controllable inverter to the input (A) of which the measurement pulse is applied and the output of which is connected with the data input (D) of the flip-flop (FL).
9. Electronic circuitry according to claim 8, characterised in that
   the controllable inverter is an exclusive-OR-member (EX) to one output (A) of which the measurement pulse is applied and another input (B) of which is connected with the output (Q) of the delay flip-flop (FL) and on its output side the member operates on the data input (D) of the delay flip-flop (FL).
10. Electronic circuitry according to claim 9, characterised in that
    a delay line (D2) is connected before the timer input of the delay flip-flop (FL) which compensates for the running time (D1) of the measurement pulse to the data input (D) of the delay flip-flop.
11. Electronic circuitry according to any one of claims 1 to 10, characterised in that
    the phase indicator contains:

    - a memory chain (SPK) with memory elements (S1-S16) of the same number as the number of inverters (I1-I16) present, whereby each memory element is associated with exactly one inverter whose logic state it stores at the instant of turning off;

    - an evaluation logic (LOG) which compresses the contents of the memory chain (SPK) into a number representing the phase angle of the last clock period of the ring oscillator (OSC) and additionally detects the logic state of the first memory element (S1).
12. Electronic circuitry according to claim 11, characterised in that
    the memory elements (S1-S16) of the memory chain (SPK) are delay flip-flops the data inputs of which are connected with the outputs of the associated inverters (I1-I16), the measurement pulse being applied to their clock inputs.
13. Electronic circuitry according to one of claims 1 to 12, characterised in that
    it is realised as an integrated CMOS circuit.

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