DE2363873A1 - ARRANGEMENT FOR DETERMINING DENSITY - Google Patents

Description

Dipl.-Phys. Leo Thul

7000 Stuttgart 3Θ
Short street 8

INTERNATIONAL STANDARD ELECTRIC CORPORATION

M.H. November 2

Arrangement for density determination

The invention relates to an arrangement for determining density, in particular for determining the density of liquids, with a device that emits output pulses, the frequency of which is f to the density d to be determined according to the relationship

d = -Rf + .S,
in which R and S are constants, is approximately proportional.

Such a device is known from US Pat. No. 3,677,067. To determine the density of the examined substance, in particular the examined liquid, from the output signal of such a device, analog computing

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devices used. However, these become finite Errors introduced and therefore "accuracy" in the density determination cannot be avoided.

The object of the invention is to provide an arrangement for determining density indicate that works digitally and is therefore more accurate. To solve this problem is an arrangement of the type described above designed in such a way that a gate circuit to which the output pulses are applied is provided is that of synchronizing switching means with gate pulses the duration To is controlled so that it sends pulses of the frequency Tf, where T is a constant, to a down counter supplies during periodically occurring periods of time, each of which is large compared to the reciprocal mechanism from Tf that switching means are provided which are controlled by sampling pulses supplied by the synchronization switching means, the down counter periodically before the occurrence of the first of the gate circuit the down counter supplied pulse to a value specified by adjusting means

γ _ STTo
R.

set the down counter for each of them from the pulse supplied to the gate circuit reduces its count by one, and that after each blocking of the Gate circuit occurring, read pulses supplied by the synchronization switching means the takeover of the then each counter reading reached by the down counter in control an output memory, which in turn is connected to Be-'nutζerschaltmittel connected.

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The invention and its other features are described below and advantages explained in more detail with reference to the drawings; in these shows

Pig. 1 shows the block diagram of an embodiment of the inventive arrangement,

! "Fig. 2 shows a more detailed circuit diagram of some Parts of the arrangement according to Figure 1,

I ¹ Ig. 3 a function table for a counter,

Figure 4- is a more detailed block diagram a counter,

Fig. 5 shows a function table for a storage register according to Pig's arrangement. 1,

6 is a more detailed block diagram for a storage register and a Logic of the arrangement according to Pig. 1,

Pig. 7 shows some pulse diagrams for the method of puncture according to the arrangement Fig. 1 are characteristic.

In Pig. 1 is one connected to a gate circuit 11 Pulse source 10 shown. This pulse source 10 symbolizes a device, e.g. a vibration densitometer, as e.g. US Pat. No. 3,677,067 is known which emits an output signal with a frequency f from which the density d of a liquid

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into which its probe was immersed, all in one "certain area" can be determined from the equation.

d = -Ef + S.

R and S are generally positive constants that are empirical "Can be determined by measuring the frequencies emitted by the device when the probe is in two various liquids "of known density" are immersed.

Essentially, the mode of operation of the arrangement according to FIG. 1 is that a down counter is set to a predetermined one Vert is set and then counts down the output pulses supplied by the measuring device. The after A count that can be read off a predetermined counting period is proportional to the density of the liquid to be determined.

The predetermined value Y to which the down counter is set is determined according to the equation

STTo

V =

In this equation, To denotes the length of the gate pulses which are fed to gate circuit 11 via line 16 will. T is an arbitrarily chosen constant, the value of which for the arrangement shown in FIG. 1 is equal to one can be. Therefore T = 1 applies.

The predetermined value V is periodically stored in a main storage register D read. This is in connection with a logic 13, which is supplied via the input 14 pulses when the gate circuit 11 is controlled to be conductive. The frequency of these pulses is - in general terms - Tf. For the special case of the arrangement according to FIG. Tf = f, since T = 1.

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Pie of the gate circuit 11 via the line 16 supplied Gate pulses are generated by a logic 15. These goal impulses always have the same length To, which is large in relation to the reciprocal of Tf.

The logic 15 also has two further output lines and 18 on. during the gate pulse occurring on line 16 is denoted pg, the one occurring on line 17 becomes Sampling pulse with pr and the one occurring on line 18 Read pulse denoted by pe. The pulse repetition frequencies the pulse trains pg, pr and pe are given with fg, fr and fc, where fg = fr ~ fc.

The size of the periodically in the main storage register D inscribed predetermined value V can be set or changed by actuating switches that are arranged in the switch matrix A. Depending on the position, these switches of switch matrix A are either positive Potential "V1 or connected to ground. The output side Signals appearing at the switches are sampled and periodically and transferred to the main storage register D read in. For this purpose, the sampling pulse pr is over a line 21 of a sampling gate B is supplied.

The sampling gate circuit D is connected between the switch matrix A and an OR circuit matrix C and the output signal this OR circuit matrix G controls the setting of the main memory register B,

Once the predetermined value Y is in the main storage register D is written, the logic 13 controls a countdown process in the main memory register D, to this Purpose, the output signals of logic 13 are the ^ aupt- * storage register D assigned via the OR circuit matrix G

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leads. The pulses to be counted arrive via the input to logic 13. The logic receives further input signals from the main storage register D supplied.

As can be seen from the above, form the order matrix C with the logic 13 and the main storage register D a down counter, which, from usual Can be type of construction. The entire backwards count is in 1 indicated by the dash-dotted line and denoted by 23.

The main storage register becomes periodic at the output scanned by means of a reading gate circuit 24, which can be designed in accordance with the scanning gate circuit B. The reading gate circuit 24 receives reading gate pulses via line 25, which it uses to sample the output signals of the main storage register D, i.e. the given count of the down counter 23. the Output signals from the reading gate circuit 24 arrive at a Output storage register 26 and from there to a display device 27. The display device 2? can optionally be set up for binary-coded decimal operation.

All circuits mentioned can be of conventional design. In the case of the display device 27, it can be the simplest The case may be a series of lamps, each of which is connected to the 1 output of a corresponding flip-flop of the output storage register 26 is connected.

The on lines 21 and 25 or at the input 14 of the Logic 13 occurring pulses are all supplied by the logic. This is generated by a 2 nHz crystal oscillator controlled. A rectangular shaper 29 is after the oscillator 28.

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switched, followed by two frequency dividers 30 and 31, each of which divides by a thousand. The output signals Cp des second frequency divider 31 arrive at logic 15. The logic 15 works together with someone connected to it Storage register 32 more or less as a counter. The output 18 of the logic 15 is connected to the line 25 via a delay element 33, while the output line is connected directly to line 21. The one with the impulses The gate circuit 11 applied to the pulse source 10 and the gate pulse pg ″ supplied on line 16 is on the output side connected to a monoflop 3 ^.

As can be seen from FIG. 2, the switch matrix A is used for the periodic setting of the flip-flops of the main memory register D on chosen values. The switch matrix A comprises a row as two-pole changeover switches A1, A2, A3 ·· An trained switches.

The scanning gate circuit B comprises switches B1A, B2A, B3A .. BnA, each of which with the obt. ^. Pole of the corresponding Switch of the switch matrix A is connected. The sampling gate circuit B further includes a second set of switches B1B, B2B, B3B ... BnB, each of which is connected to the lower pole of the corresponding switch of switch matrix A. is. Each of the switches of the scanning gate matrix B is connected to the line 21, via which the closing the switch is controlled. The switches of the scanning gate matrix B can be electronic switches, more commonly Act type.

The OR circuit matrix C comprises a first set of OR circuits C1A, C2A, C3A ... CnA, which have first inputs C1A1, C2A1, C3A1 ... CnA1, as well as second inputs C1A2,

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C2A2, C3A2 ... CnA2. The OR circuit matrix C further comprises a second set of OR circuits CIB, C2B, C3B ... CnB, which have first inputs C1B1, C2B1, C3BI .... CnB1, as well as second inputs C1B2, C2B2, C3B2 ... CnB2 exhibit. Each of the inputs C1A1-, C2A1, C3AI ... CnA1 is at the output of the corresponding switch B1A, B2A, .B3A ... BnA connected. Each of the inputs G1B1, C2B1, C3BI ... CnB1 is at the output of the corresponding switch B1B, B2B, B3B ... BnB connected. The entrances C1A2, C2A2, C3A2 ... CnA2 and C1B2, C2B2, C3B2 ... CnB2 are each with corresponding outputs of logic 13 tied together.

The main storage register C comprises a set of flip-flops D1, D2, D3 ... Dn. Each of these flip-flops has a 1 input D1A, D2A, D3A ... DnA, via which it is controlled in the 1 state and which is connected to the output of the corresponding OR circuit C1A, C2A, C3A ... CnA. The flip-flops D1, D2, D3 ... Dn also have O-inputs D1B, D2B, D3B ... DnB, via which they are controlled in the O state and each of which is connected to the output of the corresponding OR circuit C1B, C2B, C3B ... CnB.

As can be seen from FIG. 2, the outputs are the Flip-flops D1, D2, D3 ... Dn, both with logic I3 and also connected to the reading gate circuit 24.

Fig. 3 shows the function table for a typical down counter. Details of a corresponding down counter 35 are shown in FIG. 4-. The counter according to FIG. 4 has a storage register 36 with only three flip-flops X, X and Z. With the logic shown, the down counter can only ^{be 1 based on count readings 1}

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"count down to 5. The counter 35 ä.ev FIG Signals corresponding to the value to be set are fed to the OR circuits 47 Ms 52 via the lines 53 Ms 58 clem. The OR circuits 47 Ms 52 therefore serve the purpose of setting the counter to a predetermined value before the start of the counting process. As a result, the OR circuits 47 ″ to 52 not only allow the control of the flip flops X, Y and Z according to a downward counting logic, they also allow a value to be read into the memory register 36. Usually, the control signals on the lines 53 Ms 58 occur at a point in time which does not coincide with the time of appearance of the clock pulses which are fed to each of the AND circuits 37 to Ms 41 via line 59. The OR circuits 47 to 52 therefore fulfill exactly the same function as the OR circuits of the OR Circuit matrix C according to FIG. 2.

As previously mentioned, memory registers 32 and logic form I5 (Fig. 1) a counter. The logic of this counter is shown in • Fig. 5 shown.

Storage register 32 and logic I5 are shown in greater detail in FIG. As can be seen from FIG. 6, the storage register 36 comprises only two flip-flops M and N. The logic 15 has four AND circuits 60 to 63, as well as four OR circuits 64 to 67 and four further AND circuits 68 to ΊΛ. .

The pulses fed from the frequency divider 31 to the logic I5 are referred to as clock pulses Cp and arrive in Fig. 6 via line 74 to logic 15. The logic of the gate

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circuits of the logic 15 can then be expressed as follows: The logic of the AND circuit 60 is MN. The logic of the AND circuit 61 is MN. The logic of the AND circuit 62 is MN. The logic of the AND circuit 63 is M. The logic of the OR circuit 64 is MN + MN. The logic of the OR circuit 65 is MN + MN. The logic the OR circuit 66 is MN + MN. The logic of the OR circuit 67 is MN + MN.

The logic of the AND circuit 68 is Cp (MN + M). The logic of the AND circuit 69 is Cp (MN + MN). The logic of the AND circuit 70 is Cp Qffl + MN). The logic of the AND circuit 71 is Cp (MN + M).

The output of the AND circuit 60 is sent via a differential element 72 and a monoflop 72 'to the delay element 33 leading line 18 connected. The output of the AND circuit 61 is via a differentiator 73 and a monoflop 73 'are connected to line 17. The clock pulse Cp appearing at the output of the frequency divider 31 can be that in lines a and e of FIG have the shape shown. The duty cycle can be one however, this is by no means critical. The period can be half a second, although this is not critical either is.

The gate pulse occurring at the output 16 of the logic 15 is shown in line b of FIG. This impulse also occurs on the output line designated 16 in FIG. 6 on.

The pulses supplied by the pulse source 10 of FIG can have the form shown in line c of FIG. For the purpose of a better overview, the illustration

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In line c of FIG. 7, however, a greatly reduced frequency used. The real frequency of the pulses supplied by the pulse source 10 is approximately in practice 4 KHz. '■

The pulses occurring on line 18 (FIGS. 1 and 6) are shown in FIG. 7 in line f.

The output signal of the delay element 33 is in Line g of Fig. 7 is shown. The delay of the pulses in line g compared to the pulses in line f is in Fig. 7 Q. The on line 17 (Fig. 1 and Fig. 6) Occurring sampling pulses are shown in line h of FIG.

The delay element 33 can be of any conventional design. In certain cases the Delay element 33 can be dispensed with entirely.

The pulses shown in lines g and h e'er FIG can possibly be much shorter than shown. In certain cases, these impulses can also be used occur simultaneously. Although in some cases this is not absolutely necessary, the leading edge should of a read pulse (line g) preferably not before the trailing edge of the gate pulse (line b), · the leading edge of the scanning pulse (line h) not before the trailing edge of the reading pulse (line g) and the leading edge of the gate pulse (line b) not before the trailing edge of the Sampling pulse (line h) occur.

As can be seen from the above, the outputs of the logic 13 of the OR circuit matrix C are switched off with the exception of the duration of a monoflop 34 (Fig. 1)

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delivered impulses * So the AND circuits deliver 37 "to 41 of FIG. 4 no output signal, if not just above Line 59 has a pulse.

The output storage register 26 can be attached to any user scarf tcircuits must be connected. This term is intended to mean any display device, process control device, or include other facilities.

Although in the drawings for the OR circuits the .for common symbols were used, these can also be designed as wired OR circuits.

Instead of the OR circuits, "neither-up circuits" can be used as well. can be used with or without an inverter.

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Claims (8)

Patent claims 1.' Arrangement for density determination, in particular for Determination of density of liquids with a device that emits output pulses, the frequency of which is f to the density d to be determined according to the relationship d = -Ef + S, in which R and S are constants, is approximately proportional, characterized in that a gate circuit (11) is provided to which the output pulses are applied and which is controlled by synchronizing switching means (15, 28 to 32) with gate pulses (pg) of duration To, that they are pulses of the frequency Tf, where T is a constant, fed to a down counter 23 during periodically occurring periods of time, each of which is large compared to the reciprocal of Tf, that switching means (B) are provided which, controlled by the synchronizing switching means ( 15, 28 to 32), the down counter (23) is periodically fed to the down counter (23) by the gate circuit (11) before the first pulse occurs. given value set that the down counter (23) for each the pulse supplied to it by the gate circuit (11) reduces its count by one, and that in each case after the gate circuit (11) has been blocked, the synchronizing switching means (15, 28 up to 32) delivered read pulses (pe) the acceptance of the then respectively reached counter status of the return 409827/0755 down counter (23) in an output storage (26) control, which in turn is connected to user switching means (27). 2. Arrangement according to claim 1, characterized in that the gate pulses (pg), scanning pulses (pr) and read pulses (pe) are synchronized with one another. Arrangement according to Claim 2, characterized in that the interfering pulses (pg), scanning pulses (pr) and reading pulses (pe) have the same frequency, that the pulses of these three pulse trains do not overlap in time and that a gate pulse is sent to each scanning pulse (pr) (pg) and this is followed by a read pulse (pe). 4 ·. Arrangement according to claim 3 ■> characterized in that the duration of the gate, scanning and reading pulses is constant. 5- Arrangement according to one of Claims 1 to A, characterized in that the value V predetermined by the adjusting means (A) cannot be changed. 6. Arrangement according to one of claims ί to 4, characterized in that the value V predetermined by the adjusting means (A) is adjustable. - 15 - 409827/0755 M.H. November 2 - 15 - 7. Arrangement according to one of claims 1 to 6, characterized in that the down counter (32) · comprises a main storage register (D), a logic (13) and an OR circuit matrix (C) that the OR circuit matrix (C) has a first set of OR circuits (CIA ... CnA), each of which has a first input (C1A1 ... CnA1) with a corresponding sampling circuit of a first set of sampling circuits (B1A ... BnA) for the adjusting means (A) and with its output connected to a corresponding input of a first set of inputs (D1A ... DnA) of the main memory register (D) that the OR circuit matrix (C) a second set of OR circuits (C1B ... CnB), each of which has a first input (C1B1 ... CnBI) with a corresponding sampling circuit of a second set of sampling circuits (B1B. BnB) for the actuating means (A) and its output with a corresponding input a second set of inputs (D1B ... DaB) of the main memory register (D) is connected and that the respective second inputs (C1A2, .. CnA2; C1B2 ... "CnB2) of the OR circuits of both sets (C1A ... CnA; C1B ... CnB) are connected to the corresponding outputs of the logic (13). 8. Arrangement according to one of claims 1 to 7, characterized in that the user switching means (27) comprise a device indicating the count stored in the output storage register (26). 409827/0755 Blank page