EP0508232A2 - Circuit électronique pour la mesure de périodes de temps courtes - Google Patents

Circuit électronique pour la mesure de périodes de temps courtes Download PDF

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Publication number
EP0508232A2
EP0508232A2 EP92105260A EP92105260A EP0508232A2 EP 0508232 A2 EP0508232 A2 EP 0508232A2 EP 92105260 A EP92105260 A EP 92105260A EP 92105260 A EP92105260 A EP 92105260A EP 0508232 A2 EP0508232 A2 EP 0508232A2
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EP
European Patent Office
Prior art keywords
pulse
ring oscillator
electronic circuit
osc
inverters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP92105260A
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German (de)
English (en)
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EP0508232B1 (fr
EP0508232A3 (en
Inventor
Augustin Braun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MSC MICROCOMPUTERS SYSTEMS COMPONENTS VERTRIEBS GmbH
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MSC MICROCOMPUTERS SYSTEMS COMPONENTS VERTRIEBS GmbH
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Publication of EP0508232A2 publication Critical patent/EP0508232A2/fr
Publication of EP0508232A3 publication Critical patent/EP0508232A3/de
Application granted granted Critical
Publication of EP0508232B1 publication Critical patent/EP0508232B1/fr
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an AC

Definitions

  • the invention relates to an electronic circuit for measuring a short time interval, which is in the form of an electrical measuring pulse.
  • time difference meters it is common to design time difference meters as high-frequency counters or analog circuits using a "dual slope" method. If short time intervals are to be measured with high accuracy, correspondingly high counting frequencies are required for high-frequency counters. A desired accuracy of 500 picoseconds, for example, already requires a frequency of at least 2 gigahertz. Such high frequencies can, however, only be achieved with the very fastest ECL technologies, which is associated with corresponding design outlay, for example for housing and cooling, and therefore leads overall to a very expensive device.
  • the object of the present invention is therefore to provide a time difference meter with a simple circuit design, with which short time intervals can be measured with the greatest accuracy.
  • an electronic circuit consisting of a ring oscillator comprising a chain of inverters connected in series, a controllable logic element which switches the ring oscillator on or off in response to the measuring pulse representing the time interval, and at least one pulse counter which detects the Number of whole clock periods of the oscillating ring oscillator on one of the inverters, a phase indicator of the ring oscillator at the time of switching off, and finally an arithmetic-logic unit connected to the pulse counter and the phase indicator, which uses the recorded phase position and the count of the pulse counter to measure the measurement result as a multiple of the running time of one Inverters outputs.
  • the core of the proposed circuit is the controlled ring oscillator. This is started with the positive edge of the measuring pulse in phase synchronization with the measuring pulse and then oscillates at its natural frequency, which results from the running times of the series-connected inverter stages and their number.
  • the pulse counter counts the entire periods of the oscillating ring oscillator as long as the measuring pulse is present.
  • the falling edge of the measuring pulse which corresponds to the end of the time interval to be measured, switches off the ring oscillator via the controllable logic element.
  • the phase position of the last clock period at the moment of the end of the measuring pulse is recorded using the phase indicator provided. All the necessary information is thus available in the pulse counter and in the phase indicator in order to exactly determine the length of the measuring pulse or the time interval to be measured with an accuracy that corresponds to the running time of an inverter.
  • the measuring accuracy of the proposed electronic time difference meter is determined by the running time of the inverters used.
  • ASICs user-specific integrated circuits
  • CMOS complementary metal-oxide-semiconductor
  • inverter runtimes in the range of 200 pico-seconds can be easily achieved today.
  • the proposed measuring circuit is thus far superior to conventional high-frequency counters; in addition, it can be produced very inexpensively on a single chip. Another advantage is the low current consumption of the circuit.
  • the inverter chain must not be too short, otherwise the amplitude of the ring oscillator will not reach its full height in the first periods, which could also lead to incorrect counts in the pulse counters.
  • a NAND gate offers itself as a logic element for switching the ring oscillator on and off.
  • the running time of a NAND element in the technology used here is about twice as long as the running time of an inverter stage.
  • the controllable element therefore comprises, in addition to the NAND gate, two additional inverters which divide the running time of the NAND gate into two inverter running times.
  • the ring oscillator 14 comprises inverters. Together with the two additional inverters on the NAND gate, there are a total of 16 inverter stages connected in series, which is a power of two, so that the subsequent logical arithmetic operations are simplified.
  • the switching off of the ring oscillator caused by the end of the measuring pulse can occur in any phase position of its clock. If there is only a single pulse counter, the measuring pulse end could fall onto a counting edge under unfavorable circumstances, and setup / hold time violations would occur in the counter, as a result of which the counter reading could be incorrect.
  • An error of 1 would mean, for example, with 16 total inverter stages, a measurement inaccuracy of 32 inverter runtimes.
  • two parallel pulse counters are therefore provided, each of which is operated offset by about half a clock period. This ensures that at least one of the two pulse counters is always switched off in a defined manner.
  • each with a counter clock offset by about half a clock period are preferably connected to the outputs of two successive inverters.
  • the two pulse counters are each preceded by a clock generator which is designed as a controllable divider.
  • These clock generators have the task of converting the periodic clock of the ring oscillator tapped at the output of the respective inverter stage into a counting pulse with a precisely known number of edges.
  • the clock generators preferably each comprise a flip-flop, the clock input of which is connected to the output of an inverter of the ring oscillator and the output of which acts on the input of the associated pulse counter, and a controllable inverter, at the input of which the measuring pulse is applied and whose output is connected to the data input of the Flip-flops is connected.
  • An exclusive-OR gate is expediently used as the controllable inverter, which causes a counting pulse with half the clock rate to be emitted at the output of the flip-flop, as long as the measuring pulse is present on the input side.
  • the transit times that are unavoidable due to the exclusive-OR element can be compensated for by a delay section with a corresponding transit time connected upstream of the clock input of the flip-flop.
  • the phase indicator preferably consists of a memory chain and an evaluation logic.
  • the memory chain comprises the same number of memory elements as existing inverters, each memory element being assigned to exactly one inverter and storing its logic state when the ring oscillator is switched off.
  • the associated evaluation logic compresses the contents of the memory chain into a number representing the phase position of the last clock period of the ring oscillator and additionally detects the logic state of the first memory element.
  • the phase position of the last clock period of the ring oscillator is recorded at the moment of switching off by the falling edge of the measuring pulse. Based on the last phase position "frozen" and the logic value of the first memory element, it can be decided which of the two pulse counters contains the correct count.
  • An embodiment is particularly preferred in which the memory elements of the memory chain are D-type flip-flops, the data inputs of which are connected to the outputs of the associated inverters and the measuring pulse is applied to the clock inputs.
  • the measuring circuit in the form of an integrated CMOS circuit in FIG. 1 essentially consists of a ring oscillator OSC, two pulse counters C1, C2 with associated clock generators G1, G2, a phase indicator consisting of a memory chain SPK and memory elements S1 - S16 and an arithmetic-logic unit ALU.
  • the ring oscillator OSC is preceded by a NAND gate NA as a controllable logic element, the running time of which is divided into two inverters I1, I2.
  • the measuring pulse whose length is to be measured is present at the input of the NAND gate NA.
  • Downstream of the NAND gate NA is a chain of 14 inverters I3 - I16 arranged one behind the other.
  • Two pulse counters C1 and C2 are provided here, each of which is preceded by a clock generator G1 or G2.
  • the input of the clock generator G1 is connected to the output of the inverter I10, while the input of the second clock generator G2 is connected to the output of the subsequent inverter I11.
  • the memory chain SPK comprises 16 identical memory elements S1-S 16, which are designed here as D flip-flops, with exactly one inverter I1-I 16 being assigned to each memory element S1-S 16.
  • the clock input of the flip-flop FL is connected to the output of the corresponding inverter I10 or I11 of the ring oscillator OSC (see FIG. 1); its output Q acts directly on the associated pulse counter C1 or C2, which is constructed in the usual way from a chain of further D flip-flops.
  • the exclusive-or gate EX is used as a controllable inverter, one input A of which has the measuring pulse applied, the other input B of which has the output Q of the flip-flop FL is connected, and its output acts directly on the data input D of the flip-flop FL.
  • the clock input of the flip-flop FL is preceded by a correspondingly dimensioned delay line D2.
  • the measuring circuit works as follows: With the rising edge of the measuring pulse, the length of which is to be exactly determined, the ring oscillator OSC is started in phase synchronization via the NAND element NA. This then oscillates with its natural frequency, which results from the running times of the inverters I1-I16 and their number, until the falling edge of the measuring pulse switches it off again.
  • Figure 3 shows the clock periods of the ring oscillator OSC during the time interval T2 - T1, which corresponds to the length of the measuring pulse.
  • the ring oscillator OSC oscillates, its entire clock periods are counted by the pulse counters C1 and C2.
  • the clock signals tapped at the outputs of the inverters I10 and I11 of the ring oscillator OSC are converted into a count signal with half the number of pulses or double the pulse width.
  • the transit time D1 of the measuring pulse up to the data input D of the flip-flop FL is compensated by the delay path D2 to be run in parallel by the clock signal so that the measuring pulse and clock signal arrive at the flip-flop FL in phase synchronization.
  • the falling edge of the measuring pulse switches off the clock generators G1 and G2 - and thus the connected pulse counters C1, C2.
  • the instantaneous state of the inverter chain which represents the phase position of the last clock period, is transferred to the memory elements S1-S16 of the memory chain SPK assigned to each inverter I1-I16 wear.
  • the evaluation logic LOG compresses the contents of the memory chain SPK into a five-bit number, which indicates the phase position at which the ring oscillator OSC was switched off.
  • the arithmetic-logic unit ALU can now use the information provided by the evaluation logic LOG to check which phase position which of the two pulse counters C1 and C2 has been switched off under defined conditions.
  • the arithmetic-logic unit ALU then calculates the measurement result in the form of a number from the count of the selected pulse counter C1 or C2 and the recorded phase position at the switch-off time and the logic state of the first memory element S1, which represents the length of the measurement pulse as a multiple of the running time of one of the inverters I1 - I16 indicates.
  • the length of the time interval T2 - T1 between the rising and falling edge of the measuring pulse which is thus determined up to an inverter running time, can then be further processed.
  • the runtimes of the inverters can vary from chip to chip and are also subject to fluctuations in temperature and voltage, it is necessary to carry out calibrations before starting up the measuring circuit and during operation. This can be done, for example, by placing two measuring pulses of known length on the measuring circuit and by simple arithmetic obtaining a calibration curve, with the aid of which the later measured values can be converted into time differences.
  • the arithmetic required for this can be implemented by simple processors connected downstream.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
EP92105260A 1991-04-09 1992-03-27 Circuit électronique pour la mesure de périodes de temps courtes Expired - Lifetime EP0508232B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4111350A DE4111350C1 (fr) 1991-04-09 1991-04-09
DE4111350 1991-04-09

Publications (3)

Publication Number Publication Date
EP0508232A2 true EP0508232A2 (fr) 1992-10-14
EP0508232A3 EP0508232A3 (en) 1994-05-25
EP0508232B1 EP0508232B1 (fr) 1996-03-06

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EP92105260A Expired - Lifetime EP0508232B1 (fr) 1991-04-09 1992-03-27 Circuit électronique pour la mesure de périodes de temps courtes

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EP (1) EP0508232B1 (fr)
DE (2) DE4111350C1 (fr)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2296142A (en) * 1994-12-16 1996-06-19 Plessey Semiconductors Ltd Circuit arrangement for measuring a time interval
US6369563B1 (en) * 1996-11-23 2002-04-09 Mts Systems Corporation Method for high resolution measurement of a position
DE10119080A1 (de) * 2001-04-19 2002-11-14 Acam Messelectronic Gmbh Widerstandsmessung
EP0886198A3 (fr) * 1997-06-20 2003-02-26 Nec Corporation Méthode de mesure de temps et système de mesure de temps permettant de disciminer si les résultats de la mesure ont la précision de mesure désirée
EP0885373B1 (fr) * 1996-12-19 2003-04-16 Mts Systems Corporation Procede de mesure haute resolution d'un intervalle de temps
EP1314253A4 (fr) * 2000-06-22 2004-03-31 Xyron Corp Convertisseur a/n de precision a grande vitesse
US6918707B2 (en) 1997-07-15 2005-07-19 Silverbrook Research Pty Ltd Keyboard printer print media transport assembly
US7067067B2 (en) 1997-07-15 2006-06-27 Silverbrook Research Pty Ltd Method of fabricating an ink jet printhead chip with active and passive nozzle chamber structures
US7192120B2 (en) 1998-06-09 2007-03-20 Silverbrook Research Pty Ltd Ink printhead nozzle arrangement with thermal bend actuator
US7252366B2 (en) 1997-07-15 2007-08-07 Silverbrook Research Pty Ltd Inkjet printhead with high nozzle area density
WO2007069139A3 (fr) * 2005-12-12 2008-04-17 Nxp Bv Circuit de compteur électrique
US7999593B2 (en) 2005-12-12 2011-08-16 Nxp B.V. Electric circuit for and method of generating a clock signal
EP3339985A1 (fr) * 2016-12-22 2018-06-27 ams AG Convertisseur temps-numérique et procédé de conversion
US12072254B2 (en) 2019-08-09 2024-08-27 Sciosense B.V. Electric circuitry with differently oriented ring oscillators for strain measurement

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19620736C1 (de) * 1996-04-03 1997-05-28 Hydrometer Gmbh Elektronische Schaltung zum hochauflösenden Messen von Zeiten
DE102005024648B4 (de) * 2005-05-25 2020-08-06 Infineon Technologies Ag Elektrische Schaltung zum Messen von Zeiten und Verfahren zum Messen von Zeiten
DE102006006624B4 (de) 2006-02-14 2008-10-16 Smartlogic Gmbh Elektronische Schaltung zur Messung eines Zeitintervalls

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2132043A (en) * 1982-12-22 1984-06-27 Philips Electronic Associated Timer circuit
FR2564216B1 (fr) * 1984-05-11 1986-10-24 Centre Nat Rech Scient Convertisseur temps-numerique ultrarapide
GB8717173D0 (en) * 1987-07-21 1987-08-26 Logic Replacement Technology L Time measurement apparatus

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2296142A (en) * 1994-12-16 1996-06-19 Plessey Semiconductors Ltd Circuit arrangement for measuring a time interval
EP0717329A2 (fr) 1994-12-16 1996-06-19 Plessey Semiconductors Limited Circuit disposé pour la mesure d'une intervalle de temps
US5684760A (en) * 1994-12-16 1997-11-04 Plessey Semiconductors, Ltd. Circuit arrangement for measuring a time interval
GB2296142B (en) * 1994-12-16 1998-03-18 Plessey Semiconductors Ltd Circuit arrangement for measuring a time interval
EP0717329A3 (fr) * 1994-12-16 1999-02-17 Mitel Semiconductor Limited Circuit disposé pour la mesure d'une intervalle de temps
US6369563B1 (en) * 1996-11-23 2002-04-09 Mts Systems Corporation Method for high resolution measurement of a position
EP0885373B1 (fr) * 1996-12-19 2003-04-16 Mts Systems Corporation Procede de mesure haute resolution d'un intervalle de temps
EP0886198A3 (fr) * 1997-06-20 2003-02-26 Nec Corporation Méthode de mesure de temps et système de mesure de temps permettant de disciminer si les résultats de la mesure ont la précision de mesure désirée
US7252366B2 (en) 1997-07-15 2007-08-07 Silverbrook Research Pty Ltd Inkjet printhead with high nozzle area density
US6918707B2 (en) 1997-07-15 2005-07-19 Silverbrook Research Pty Ltd Keyboard printer print media transport assembly
US7067067B2 (en) 1997-07-15 2006-06-27 Silverbrook Research Pty Ltd Method of fabricating an ink jet printhead chip with active and passive nozzle chamber structures
US7192120B2 (en) 1998-06-09 2007-03-20 Silverbrook Research Pty Ltd Ink printhead nozzle arrangement with thermal bend actuator
EP1314253A4 (fr) * 2000-06-22 2004-03-31 Xyron Corp Convertisseur a/n de precision a grande vitesse
DE10119080A1 (de) * 2001-04-19 2002-11-14 Acam Messelectronic Gmbh Widerstandsmessung
US6690183B2 (en) 2001-04-19 2004-02-10 Acam-Messelectronic Gmbh Resistance measurement
WO2007069139A3 (fr) * 2005-12-12 2008-04-17 Nxp Bv Circuit de compteur électrique
US7999593B2 (en) 2005-12-12 2011-08-16 Nxp B.V. Electric circuit for and method of generating a clock signal
EP3339985A1 (fr) * 2016-12-22 2018-06-27 ams AG Convertisseur temps-numérique et procédé de conversion
WO2018114401A1 (fr) * 2016-12-22 2018-06-28 Ams Ag Convertisseur temps-numérique et procédé de conversion
TWI662794B (zh) * 2016-12-22 2019-06-11 奧地利商Ａｍｓ有限公司 時間至數位轉換器及轉換方法
CN110226133A (zh) * 2016-12-22 2019-09-10 ams有限公司 时间数字转换器和转换方法
US10671025B2 (en) 2016-12-22 2020-06-02 Ams Ag Time-to-digital converter and conversion method
CN110226133B (zh) * 2016-12-22 2020-10-30 ams有限公司 时间数字转换器和转换方法
US12072254B2 (en) 2019-08-09 2024-08-27 Sciosense B.V. Electric circuitry with differently oriented ring oscillators for strain measurement

Also Published As

Publication number Publication date
DE59205532D1 (de) 1996-04-11
EP0508232B1 (fr) 1996-03-06
DE4111350C1 (fr) 1992-09-10
EP0508232A3 (en) 1994-05-25

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