Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2007—Display of intermediate tones
  • G09G3/2011—Display of intermediate tones by amplitude modulation
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3685—Details of drivers for data electrodes
  • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0243—Details of the generation of driving signals
  • G09G2310/0259—Details of the generation of driving signals with use of an analog or digital ramp generator in the column driver or in the pixel circuit
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0264—Details of driving circuits
  • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters

Definitions

• the present invention generally relates to control circuits for display devices and, more particularly, it relates to a system for applying brightness signals to the pixels of a display device such as a liquid crystal display.
• display devices such as liquid crystal displays, consist of a matrix of pixels arranged horizontally in rows and vertically in columns.
• the data to be displayed is applied in the form of brightness signals (gray scale) to data lines which are individually associated with each of the pixel columns.
• the rows of pixels are scanned sequentially and the pixels within the activated row are loaded at different brightness levels based on the levels of brightness signals applied to each column.
• each pixel is composed of at least three pixel elements, each of which emits one of the three primary colors of light, red, green or blue.
• each pixel element is associated with a switching device making it possible to activate or deactivate each of the pixel elements.
• the switching device is a semiconductor device, for example a thin film transistor (TFT), which receives the brightness information from a set of semiconductor circuits. Since both the switching devices and the circuit assemblies are constituted by semiconductor devices, it is preferable to manufacture the switching devices and the circuit assembly by a technology either of amorphous silicon or of polycrystalline silicon.
• Liquid crystal displays are made of liquid crystal material sandwiched between two substrates. At least one of these substrates, and generally both, are transparent to light, and the surfaces of the substrates surrounding the liquid crystal material carry configurations of transparent conductive electrodes arranged in a configuration allowing the formation of individual pixel elements.
• the aim sought in the industry is to manufacture the various components of the control circuits on the substrates and around the periphery of the display at the same time as the semiconductor switching elements are manufactured.
• Amorphous silicon offers a preferable technology for the manufacture of liquid crystal displays, as this material can be manufactured at low temperatures.
• a low manufacturing temperature is important since it allows the use of materials for the substrate which are conventional, readily available and inexpensive.
• amorphous silicon technology is considered to be unusable because of the low mobility of amorphous silicon which makes it impossible to operate at the speeds necessary for the production of television type displays.
• the manufacture of control circuit assemblies on the same substrates as the display matrix required the use of polycrystalline silicon, given the greater mobility of the carriers thereof. this.
• polycrystalline silicon has the disadvantage of requiring manufacture at high temperatures, which requires the use of special and expensive substrate materials.
• a system for applying brightness signals to each of the pixel columns in a display having a matrix of pixels arranged in columns and in rows has a plurality of signal transmission gates arranged to apply the brightness signals individually to the columns of pixels.
• Each of the transmission doors has a control electrode to pass and block the transmission doors in response to a control signal exceeding a threshold.
• the system includes means for preloading the control electrodes at the threshold.
• the brightness signals are applied to the electrode columns by means of the transmission doors.
• the present invention can be used with that described in the PCT application filed on the same date, having as inventors Leopold A. Harwood and Dora Plus, entitled “Control circuit for liquid crystal display and signal decoder for such a circuit” and claiming priority from US Application No. 71600050.
• Figure 1 shows a preferred embodiment of the invention
• Figure 2 shows a preferred embodiment of a comparator circuit for use in the preferred embodiment of Figure 1;
• FIG. 3 represents a preferred embodiment of a comparator circuit using CMOS technology.
• FIG. 4 is a time diagram of the comparator circuit of Figure 2.
• a set of analog circuits 11 receives an analog information signal representative of the data to be displayed coming from an antenna 12.
• the input signal is a television video signal
• the set of analog circuits 11 resembles that of a conventional television of known type.
• the tube is replaced by a liquid crystal display device as described here.
• the analog circuit 11 supplies a signal carrying analog data on a line 13 as the input signal of a digital-analog converter (D / A) 14.
• D / A digital-analog converter
• the television signal from the set of analog circuits 11 is intended to be displayed on a liquid crystal network 16 consisting of a large number of pixel elements, such as the liquid crystal cell 16a, arranged horizontally in m rows and vertically in n columns.
• the liquid crystal network 16 comprises nc innate data lines 17, either one for each of the vertical columns of the liquid crystal cells, and m selection lines 18, or one for each of the horizontal rows of s liquid crystal cells.
• the A / D converter 14 includes an output bus 19 for supplying levels of brightness, or gray scale codes, to digital storage means 21 having several output lines 22.
• the output lines 22 of digital storage means 21 control the voltages applied to the data lines 17 for the columns of the cells liquid crystal 16a by digital / analog converters (D / A) 23, comparators 24 and transmission gates 26. Each of the output lines 22 therefore controls the voltage applied to the liquid crystal cell in a given column when an associated transmission door 26 is open, according to the scanning of the selection lines 18.
• a display device using counters and a preferred embodiment of the storage means 21, in the form of a shift register, are described in US patents nos. 4,766,430 and 4,742,346, the lessons of which are incorporated into the present application.
• a reference ramp generator 33 provides a reference ramp voltage signal on an output line 27. Line 27 is coupled, through a line 32, to comparators 24 in each of the columns of liquid crystal cells.
• a data ramp generator 34 provides a data ramp to the columns of the pixel elements by connecting the output line 28 to each of the transmission gates 26.
• the transmission gates 26 are layered transistors thin. the control electrodes of which are coupled to the outputs of the comparators 24 by lines 29.
• the digitized brightness signals coming from the digital storage means 21 are applied by the output lines 22 to the digital / analog converters 23, the output line 31 of which is connected to an input of a comparator 24
• the reference ramp generator 33 provides a reference ramp to the other input of each of the comparators 24 via the lines 32.
• the reference ramp may be non-linear in order to compensate for any cases of non-linearity generated in any part. of the television transmitter / receiver system or of the comparators 24.
• the output lines 29 of the comparators 24 are in the high position, and the transmission doors 26 are passable.
• the voltages on the output lines 29 make the transmission doors passable and blocked, and thus serve as control signals for the transmission doors.
• the data ramp on line 28, coming from the data ramp generator 34, is thus applied to each pixel element which is inside the activated row and which is associated with a passing transmission gate 26.
• the output line 29 of the comparator 24 goes to low level, blocking the associated transmission door 26.
• the pixel element associated with the blocked transmission door is thus loaded at the level established by the analog light signal from the D / A converter 23.
• FIG. 2 represents a preferred embodiment of an analog comparator 24.
• the analog comparator 24 comprises several doors of transfer doors 36 to 41 which, in the preferred embodiment shown here, are thin film transistors (TFT) .
• TFT thin film transistors
• the output line 31 of the D / A converter 23 supplies the brightness signal as an input to the transfer gate 36 which is therefore the data input device of the comparator 24.
• the input transfer gate 36 is coupled to a transfer gate 37 which functions as a data input switch for the comparator 24.
• a storage capacitor 43 is coupled to a node D between the input transfer gate 36 and the switchable transfer gate 37, and to the mass.
• the data input to the transfer gate 36 charges the capacitor 43 at the data level.
• the control electrode of the transfer door 37 is set high, the door is turned on and transfers the signal from node D to node A.
• the switchable transfer doors 37 for all the columns of the display are turned on simultaneously.
• the lines 32 which in FIG. 1 are represented as connecting the output line 27 of the generator 33 of the reference ramp to the comparators 24, are connected to a reference ramp transfer gate 38, itself connected to the node A.
• the reference ramp transfer gate 38 controls the timing of the reference ramp and the timing of the preloading of node A.
• a coupling capacitor 44 connects node A to node B.
• Node B is coupled to the control electrode a detection transfer gate 39, which is connected between the node C and the ground.
• the transfer gate 39 serves as a voltage detector on the node B to monitor the comparator output voltage on the node C. However, the node B being coupled to the node A through the coupling capacitor 44, the transfer gate actually detects the voltage on node A.
• a transfer door with automatic zero setting 41 is disposed between the nodes B and C.
• the control electrode and the drain of the transfer door 39 are connected and the voltages on the nodes B and C become the same.
• a switchable load 40 is connected between a supply voltage V + and the output node C.
• the load switchable 40 can also be a thin film transistor (TFT).
• TFT thin film transistor
• the switchable load control electrode 40 is connected to a load control input terminal 49.
• a first period 55 which lasts 10 microseconds, the input transfer gate 36 is blocked and the switchable transfer gate 37 is turned on to transfer data from node D to node A.
• the display is activated at the start, there is no data available at node D to generate a display line and therefore, during the first line time, the voltage transferred from node D to node A has any value it possesses at this very moment, and it has no effect.
• the phenomena that occur with transfer gates 38, 39, 40 and 41 are of no importance due to the unavailability of data at that time.
• the switchable transfer gate 37 is blocked and the input transfer gate 36 is rendered busy.
• node D is preloaded at the maximum data voltage, for example at + 12 volts.
• the input transfer gate 36 is turned on for a period 54 of two microseconds, and the node D is pulled towards the bottom, from the +12 volts level to the data voltage available on line 31. This state of node D persists until the start of the second time-line T,
• the second line beat begins at T and is
• the line time periods 52 are the same as those of the first line time 51, as indicated by the same references, and refer to the input transfer door 36 and the switchable transfer door 37.
• the time periods -line 53 refer to devices 37 to 41.
• the initial time period 55 is 10 microseconds and, as indicated above, this period is that of the data transfer during which data is transferred from node D to node A.
• Node B is coupled to node A through the coupling capacitor 44 and the transfer gate 41 with reset at automatic zero is turned on during this period.
• the node A charges at the data voltage while the nodes B and C recover at the threshold voltage of the transfer gate 39.
• the transfer gate of the reference ramp 38 is turned on to apply the reference ramp voltage to the node A.
• the node A is pulled down by the reference ramp and therefore node B is also pulled down.
• the voltages on nodes A and B also increase and when node B reaches the threshold voltage of the detection transfer gate 39 the gate begins to drive.
• the voltage on node B continues to increase and gradually pulls the voltage on node C down and blocks the transmission gate 26 when the reference voltage reaches the threshold voltage of the transmission gate 26.
• the element pixel associated with the blocked transmission door is therefore loaded at the level established by the brightness signal applied to the comparator 24.
• An additional period 60 of ten microseconds allows the line selection device to have time to deselect the horizontal line 18 and to prepare the display for the next line.
• the last period 61 of time-line 53 is three microseconds.
• the transfer gate 38 of the reference ramp generator is turned on to precondition the node A at -3 volts. This operation resets the voltage on node A and eliminates the input information from the previous line time.
• the switchable load 40 is also activated for a short period of time, which is preferably shorter than the three microsecond period, to raise the node C to a voltage level higher than the door threshold voltage transfer 39.
• the transfer door with automatic reset 41 is also turned on and remains on until it is blocked later.
• node B When the transfer door with automatic reset 41 is turned on, the node B is directly connected to the node C and the detection transfer door 39 re-establishes itself at its threshold voltage after deactivation of the switchable load.
• the preloading of nodes C and D is an important characteristic, because it leads to a “pull down” type operation and allows the rapid operation necessary for the comparator circuit while using either a low mobility amorphous silicon technology or indeed a polycrystalline silicon technology.
• FIG. 3 An embodiment of a comparator capable of being produced by CMOS technology is shown in FIG. 3.
• the detection transfer gate 39 and the switchable load 40 of the embodiment of FIG. 2 are replaced by a CMOS inverter 54.
• CMOS inverter 54 It can also be envisaged that a CMOS transmission door is used in place of the transfer door 41 with automatic reset.
• the other transfer doors 36, 37, 38 and 26 of the embodiment shown in FIG. 2 can also be replaced by CMOS transmission doors, and the basic operation is very similar to that of the amorphous silicon embodiment of FIG. 2.
• the inverter 54 functions as the voltage detector on node B.
• the output node C and the node input B are short-circuited in order to position the tripping point of the inverter on its own transition point, typically of the order of half a volt VDD. This reduces the sensitivity of the detector 54 to variations in device parameters, such as threshold voltage and mobility, which increases the accuracy of the device.
• the invention represents a remarkable improvement over the prior art because it allows the use of all silicon technologies in order to integrate the sets of control circuits on the same substrate as the liquid crystals in a device for display having an operating speed useful for display on color television.
• the invention also has the advantage of providing a converter circuit which converts an amplitude-dependent analog signal into a time-based digital signal, using only seven active components and two capacitors.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Chemical & Material Sciences (AREA)
• Crystallography & Structural Chemistry (AREA)
• Liquid Crystal Display Device Control (AREA)
• Control Of Indicators Other Than Cathode Ray Tubes (AREA)
• Liquid Crystal (AREA)

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• 1990
  • 1990-10-19 US US07/600,046 patent/US5170155A/en not_active Expired - Lifetime
• 1991
  • 1991-10-18 JP JP03517067A patent/JP3128073B2/ja not_active Expired - Fee Related
  • 1991-10-18 WO PCT/FR1991/000821 patent/WO1992007351A1/fr active IP Right Grant
  • 1991-10-18 DE DE69124988T patent/DE69124988T2/de not_active Expired - Lifetime
  • 1991-10-18 EP EP91918020A patent/EP0506906B1/de not_active Expired - Lifetime
  • 1991-10-18 KR KR1019920701417A patent/KR100221106B1/ko not_active IP Right Cessation
• 1999
  • 1999-12-28 JP JP37465899A patent/JP3270034B2/ja not_active Expired - Fee Related

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