EP0487101A2 - Elektrische Anordnung mit einem dopierten amorphen Siliziumkanal - Google Patents

Elektrische Anordnung mit einem dopierten amorphen Siliziumkanal Download PDF

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Publication number
EP0487101A2
EP0487101A2 EP91119957A EP91119957A EP0487101A2 EP 0487101 A2 EP0487101 A2 EP 0487101A2 EP 91119957 A EP91119957 A EP 91119957A EP 91119957 A EP91119957 A EP 91119957A EP 0487101 A2 EP0487101 A2 EP 0487101A2
Authority
EP
European Patent Office
Prior art keywords
amorphous silicon
dopant
semiconductor layer
layer
silicon semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP91119957A
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English (en)
French (fr)
Other versions
EP0487101A3 (en
EP0487101B1 (de
Inventor
Yoshio Kishimoto
Masaaki Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
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Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of EP0487101A2 publication Critical patent/EP0487101A2/de
Publication of EP0487101A3 publication Critical patent/EP0487101A3/en
Application granted granted Critical
Publication of EP0487101B1 publication Critical patent/EP0487101B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1604—Amorphous materials
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells

Definitions

  • the present invention relates to a semiconductor device for use in an information processing due to a neural network and more particularly to an electrically plastic device which shows an electrically non-linear characteristic (conductivity or capacitance) upon receiving an input energy (size or time variation).
  • An information processing due to a neural network has been already known to be an excellent method for treating the information processing in a similar way to that of the human brain.
  • a neuron tip previously proposed is classified into two groups; a semiconductor device and an optical device.
  • the semiconductor device is rather in a high potential for the practical realization of the neuron tip but is still in a difficult position to obtain a plastic function suitable for the neuron tip.
  • the previous development for the neural network has been directed to a modification of bipolar or CMOS silicon semiconductor provided with an analog operation.
  • FET electric field effect transistor
  • OTA transconductance amplifier
  • capacitor array capacitor array
  • switched resistor array switched resistor array
  • An amorphous silicon has a number of irregular lattice defects and dangling bonds combined with hydrogen atoms in a different way from that of a single crystal silicon. Therefore, a molecular formula of the amorphous silicon is exactly expressed by SiH x .
  • the amorphous silicon has another feature that it can be formed into a porous structure. Accordingly, the dopant in the amorphous silicon can move freely throughout the defective lattice and controls the electric conductivity in a wide range. The reversible movement of the dopant in the amorphous silicon is disclosed at a paper, R. Konenkamp, Solid State Communication, 73 (5), p.323 (1990).
  • An object of the present invention is therefore to provide an electrically plastic device which solves the above problem.
  • a further object of the present invention is to provide an electrically plastic device characterized by a high gain and an excellent performance based on the description of Japanese Patent Publication (Has 1-192961, examined)
  • the present invention is to provide an electrically plastic device comprising; an amorphous silicon semiconductor layer including movable dopant formed between a pair of electrodes; and at least one gate electrode formed on said amorphous silicon semiconductor layer through an insulating layer or a high-resistance layer; whereby the operation of said gate electrode controls the conductivity of said amorphous semiconductor layer in regulating the dopant distribution.
  • the amorphous silicon semiconductor layer is superposed on a movable dopant supporting layer.
  • a dopant permeable separation layer is interposed between the amorphous silicon semiconductor layer and the movable dopant supporting layer.
  • Fig. 1 is a cross-sectional view of the electrically plastic device according to the embodiment of the present invention.
  • Fig. 2 is a cross-sectional view for showing the electrically plastic device and its circuit having two terminals according to another embodiment of the present invention.
  • Fig. 3 is a graph showing a relationship between a gate voltage and a drain current of the electrically plastic device according to the present invention.
  • Fig. 4 is an equivalent circuit illustrating the operation of the electrically plastic device according to the present invention.
  • Fig. 5 is an equivalent circuit of the modification of the electrically plastic device according to the present invention.
  • Fig. 6 is a graph showing a relationship between the gate voltage and the drain current of the electrically plastic device according to the present invention.
  • Fig. 7 is a block diagram of a neural network formed by using a plurality of the electrically plastic devices according to the present invention.
  • an ion conductive substrate 4 of glass or ceramic plate acts as a supporting layer for a movable dopant and has an amorphous silicon semiconductor layer 3, an insulating layer 6 and a gate electrode 5 formed thereon.
  • a pair of electrodes 1 and 2 are formed on the ion conductive substrate 4 so as to come in contact with the insulating layer 6 and the amorphous silicon semiconductor layer 3.
  • the insulating layer 6 can be substituted with a high-resistance layer.
  • This structure is suitable for the case in which the movable dopant supporting layer is composed of an ion conductive substrate made of a glass or ceramic plate.
  • a polymeric compounds instead of the glass or ceramic can be used for the ion conductive substrate acting as a movable dopant supporting layer.
  • the electrically plastic device can be more easily manufactured in a reverse order to that for the glass or ceramic plate. That is, an aluminum plate having an aluminum oxide film formed thereon is used for a gate electrode. A next step is to form an amorphous silicon layer on the aluminum oxide film and the a movable dopant supporting layer on the amorphous silicon layer.
  • an ion conductive substrate 7 has a movable dopant supporting layer 4 formed thereon.
  • An amorphous silicon semiconductor layer 3 is formed on the movable dopant supporting layer 4 and has a pair of electrodes 1 and 2 formed at the terminals thereof.
  • a gate electrode 5 is formed between the pair of electrodes 1 and 2 through an insulating layer 6.
  • the resultant device can be operated in a high speed and in a high sensitivity when the electrodes 1 and 2 (source and drain) are formed between the amorphous silicon layer and the movable dopant supporting layer as shown in Fig. 1.
  • a structure having the movable dopant supporting layer 4 integrated with the amorphous silicon semiconductor layer 3 is an essential part of the electrically plastic device according to the present invention.
  • a more useful structure having a threshold value for controlling of the movement of the dopant can be achieved by providing a dopant permeable separation layer between the amorphous silicon semiconductor layer and the movable dopant supporting layer in accordance with the present invention.
  • the dopant permeable separation layer is electrically insulating and precisely controls exactly the movement of the dopant to stabilize the switching characteristics between the pair of electrodes (source and drain).
  • a dopant permeable separation layer can be composed of a porous film having an ion permeable property and suitably composed of a separator material for use in a battery.
  • a cation dopant D+ is movable and has a polarity reverse to that of the carrier of the amorphous silicon semiconductor to move depending on the voltage applied across the electrodes.
  • the channel impedance markedly varies with the movement of the cation dopant, which is greatly affected by the electric charge and ion radius of the dopant and the structure and the density of the amorphous silicon semiconductor and so on.
  • Fig. 4 shows a case in which the amorphous silicon semiconductor and the cation dopant are used for an easy illustration, but it should be noted that the scope of the present invention is not limited to only the case using the cation dopant.
  • An insulating layer at the gate can be substituted with a high-resistance layer 8 as shown in Fig. 5 which is an equivalent circuit of the substituted device.
  • the high-resistance layer 8 preferably has a high resistivity ranging from 105 to 1012 ohm-cm. It is necessary for the as-doped amorphous silicon semiconductor layer 3 between the pair of electrodes to have a markedly higher conductivity than the movable dopant supporting layer 4 as shown clearly in the equivalent circuit shown in Fig.5.
  • the device according to the present invention is characterized in that the amorphous silicon layer shows a large change in the conduction thereof with a magnitude ranging from (x104) to (x108) which locates between the source and the drain.
  • the response speed of the device can be greatly improved.
  • Fig. 3 is a graph showing, as an example, a controlling operation characteristic of the electrically plastic device according to the present invention comprising an n-type amorphous silicon semiconductor and the cation dopant. It is noted that Fig. 3 shows a case in which the movement of the dopant is shorter than the pulse width, so that in response to the negative gate pulse the learning operation is carried out and in response to the positive gate pulse the reset operation is carried out.
  • a neural network can be formed by using a plurality of these elements as shown in Fig. 7. In the neural network, the elements after undergoing the learning operation show a very low impedance. The neural network executes the learning or the reset in a time of msec order but can operate preferably at a high speed of micro sec order after the learning. The operation of this neural network can be expressed by an I D - V G characteristic as shown in Fig. 6, which is corresponding to a characteristic obtained by combining the enhancement form and the depression form of MOSFET.
  • the amorphous silicon semiconductor layer 3 can formed by various methods such as evaporation, glow discharge sputtering, CVD, MBE and the like.
  • the electrically plastic device according to the present invention can be formed by using an electrically conductive polymer.
  • the amorphous silicon semiconductor layer is different in the following point from the conductive polymer that the amorphous silicon semiconductor layer does not show any expansion and shrinkage during the doping and de-doping of the dopant. It is possible to change the electronic structure of the amorphous silicon semiconductor layer by chemically modifying the surface of the amorphous silicon semiconductor layer with a chemical or physical absorption or the chemical bonding.
  • the amorphous silicon semiconductor layer can be changed in the resistivity by doping non-movable dopant and can form either an n-type or p-type semiconductor.
  • the non-movable dopant interacts with the movable dopant to change the resistivity of the amorphous silicon semiconductor layer in an adjusting way.
  • the interaction between the non-movable dopant and the movable dopant can be used for the threshold value control.
  • the neural network is preferably formed from the amorphous silicon semiconductor layer having a high electric resistance. It is not suitable for the neural network to consist of the semiconductor having the non-movable dopant in a high concentration doped therein.
  • the movable dopant supporting layer is a layer in which the dopant moves easily, and is preferably low conductivity.
  • the movable dopant supporting layer is consisting of an ion-conductive material such as glass, ceramic or organic material.
  • the glasses or ceramics can be used both as an electric conduction substrate in addition to the movable dopant supporting layer.
  • Material suitable for the movable dopant supporting layer is an ion conductive glass or ceramic conductor including an alkali ion such as Na- ⁇ -Al2O3, Na x WO3, a proton conductor, reversible ion conductor containing Ag+ or cu+ ion and sodium glass.
  • a porous ceramic such as zeolite, or lithium ion-or halogen ion-containing conductor. It is possible to use polyion complex compound or an ion-conductive polymeric compound.
  • the movable dopant supporting layer can be formed from an anisotropic conduction film which is of a high insulating property in a parallel direction to the film and of a high conduction property in a perpendicular direction to the film.
  • the amorphous silicon semiconductor layer produces the movement of the dopant due to the operation of the gate electrode, upon having the dopant injected therein.
  • the movable dopant supporting layer must be composed of a material to contain the movable dopant stable and reversible against the redox. It is desirable that the movable dopant supporting layer consists of ion-conductive glasses or ceramics forming a complex compound with the movable dopant.
  • This structure provides the electrically plastic device with the threshold value characteristic and the ensured memory characteristic. An ion inclusion compound can be used for this structure.
  • the electronic redox usually occurs with the movement of the movable dopant at the operation of the gate electrode but can be made reversible and stable with this structure of the device according to the present invention.
  • An electrically plastic device is not limited to the structure shown in Figs. 1 and 2 and can be formed into a structure having a substrate of a silicon single crystal which has an insulating film of SiO2 formed thereon.
  • An use of a plurality of the electrically plastic devices according to the present invention makes it possible to form an integrated circuit in a similar way to the fabrication process of semiconductor integrated circuits and to accomplish neuron tips.
  • a pair of electrodes 1 and 2 are formed on an ion-conductive sodium glass substrate 4 having Na ions as ion carriers as shown in Fig. 1.
  • An amorphous silicon semiconductor layer 3 in a thickness of 10 micron millimeter is formed on the sodium glass substrate 4.
  • a gate electrode 5 is formed on the amorphous silicon semiconductor layer 3 through an insulating layer 6.
  • An electrically plastic device can be formed into a structure described above and a pulse voltage in applied to the gate electrode for the operation.
  • the electrically plastic device according to the present invention shows a non-linear switching characteristic as shown in Fig. 3.
  • a negative gate pulse is applied to execute the learning and a positive gate pulse is applied for the purpose of the reset.
  • a network shown in Fig. 7 is formed from a plurality of the electrically plastic devices and are supplied with a gate voltage applied to terminals at given positions. Then, the devices positioned on a line of the shortest distance between the output and input terminals shows a low impedance. Accordingly, the devices can study a relation between the output signal and the input signal through the variation in the electric resistance.
  • an ion conductive ceramic layer 4 in a thickness of 1mm having a Na- ⁇ -aluminum oxide layer in a thickness of 3 ⁇ m and an amorphous silicon semiconductor layer 3 in a thickness of 1 ⁇ m sequentially are formed on a substrate 7.
  • a pair of electrodes 1 and 2 are formed on the amorphous silicon semiconductor layer 3.
  • a gate electrode 5 is formed on the amorphous silicon semiconductor layer 3 through an insulating layer 6 as shown in Fig. 2 so as to complete an electrically plastic device.
  • the gate and the source of the electrically plastic device are made short circuited so that a negative gate pulse of 10 V is applied for the purpose of the learning and the positive gate pulse of 10 V is applied for the purpose of the reset.
  • a channel impedance shows a great variation of 106 ohmbetween the operations of the negative and positive gate pulses.
  • a network shown in Fig. 7 is formed from a plurality of the electrically plastic devices. Then, by repeating the learning, a low impedance can be obtained with the devices positioned on a line of the shortest distance between the output and input terminals. Accordingly, the network can study a relation between the output signal and the input signal by the variation in the electric resistance.
  • An amorphous silicon semiconductor layer in a thickness of 3 ⁇ m is formed on a silicon substrate having a silicon dioxide film formed thereon.
  • a pair of Au-Ni electrodes are formed on the amorphous silicon semiconductor layer and have a movable dopant supporting layer in a thickness of 5 ⁇ m is formed on the semiconductor layer between the pair of electrodes.
  • the movable dopant supporting layer is composed of tungsten bronze compound (Na x WO3) having Na+ ions as an ion carrier.
  • An electrically plastic device obtained in such a way can be operated by using the silicon substrate as a gate electrode and shows a switching characteristic and a source-drain current-time characteristic similar to those of the Example 1.
  • a neural network is formed by using a plurality of these electrically plastic devices. The operation of the neural network produces a network having a resistance pattern corresponding to a learning signal.
EP91119957A 1990-11-22 1991-11-22 Elektrische Anordnung mit einem dotierten amorphen Siliziumkanal Expired - Lifetime EP0487101B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP31873390 1990-11-22
JP2318733A JPH0770731B2 (ja) 1990-11-22 1990-11-22 電気可塑性素子
JP318733/90 1990-11-22

Publications (3)

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EP0487101A2 true EP0487101A2 (de) 1992-05-27
EP0487101A3 EP0487101A3 (en) 1994-06-08
EP0487101B1 EP0487101B1 (de) 2000-11-15

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EP91119957A Expired - Lifetime EP0487101B1 (de) 1990-11-22 1991-11-22 Elektrische Anordnung mit einem dotierten amorphen Siliziumkanal

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US (1) US5315131A (de)
EP (1) EP0487101B1 (de)
JP (1) JPH0770731B2 (de)
DE (1) DE69132469T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6603143B2 (en) * 1999-03-18 2003-08-05 Hyundai Electronics Industries Co., Ltd. Semiconductor device and method for fabricating same

Families Citing this family (166)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5787042A (en) * 1997-03-18 1998-07-28 Micron Technology, Inc. Method and apparatus for reading out a programmable resistor memory
US6103403A (en) * 1997-05-15 2000-08-15 University Of Kentucky Research Foundation Intellectual Property Development Clathrate structure for electronic and electro-optic applications
WO1999028914A2 (en) * 1997-12-04 1999-06-10 Axon Technologies Corporation Programmable sub-surface aggregating metallization structure and method of making same
US6635914B2 (en) * 2000-09-08 2003-10-21 Axon Technologies Corp. Microelectronic programmable device and methods of forming and programming the same
US6487106B1 (en) 1999-01-12 2002-11-26 Arizona Board Of Regents Programmable microelectronic devices and method of forming and programming same
WO2000048196A1 (en) * 1999-02-11 2000-08-17 Arizona Board Of Regents Programmable microelectronic devices and methods of forming and programming same
US7675766B2 (en) * 2000-02-11 2010-03-09 Axon Technologies Corporation Microelectric programmable device and methods of forming and programming the same
WO2002021542A1 (en) * 2000-09-08 2002-03-14 Axon Technologies Corporation Microelectronic programmable device and methods of forming and programming the same
US6653193B2 (en) 2000-12-08 2003-11-25 Micron Technology, Inc. Resistance variable device
US6638820B2 (en) 2001-02-08 2003-10-28 Micron Technology, Inc. Method of forming chalcogenide comprising devices, method of precluding diffusion of a metal into adjacent chalcogenide material, and chalcogenide comprising devices
JP4742429B2 (ja) * 2001-02-19 2011-08-10 住友電気工業株式会社 ガラス微粒子堆積体の製造方法
US6727192B2 (en) * 2001-03-01 2004-04-27 Micron Technology, Inc. Methods of metal doping a chalcogenide material
US6818481B2 (en) 2001-03-07 2004-11-16 Micron Technology, Inc. Method to manufacture a buried electrode PCRAM cell
US6734455B2 (en) * 2001-03-15 2004-05-11 Micron Technology, Inc. Agglomeration elimination for metal sputter deposition of chalcogenides
WO2002091494A1 (en) * 2001-05-07 2002-11-14 Advanced Micro Devices, Inc. Switch element having memeory effect
DE60220912T2 (de) * 2001-05-07 2008-02-28 Advanced Micro Devices, Inc., Sunnyvale Speichervorrichtung mit einem sich selbst einbauenden polymer und verfahren zur herstellung derselben
CN1276518C (zh) * 2001-05-07 2006-09-20 先进微装置公司 使用复合分子材料的浮置栅极存储装置
AU2002340793A1 (en) * 2001-05-07 2002-11-18 Coatue Corporation Molecular memory device
AU2002340795A1 (en) 2001-05-07 2002-11-18 Advanced Micro Devices, Inc. Reversible field-programmable electric interconnects
US6873540B2 (en) * 2001-05-07 2005-03-29 Advanced Micro Devices, Inc. Molecular memory cell
US7102150B2 (en) 2001-05-11 2006-09-05 Harshfield Steven T PCRAM memory cell and method of making same
US6951805B2 (en) * 2001-08-01 2005-10-04 Micron Technology, Inc. Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry
US6806526B2 (en) 2001-08-13 2004-10-19 Advanced Micro Devices, Inc. Memory device
US6768157B2 (en) 2001-08-13 2004-07-27 Advanced Micro Devices, Inc. Memory device
US6838720B2 (en) * 2001-08-13 2005-01-04 Advanced Micro Devices, Inc. Memory device with active passive layers
US6858481B2 (en) 2001-08-13 2005-02-22 Advanced Micro Devices, Inc. Memory device with active and passive layers
DE60130586T2 (de) 2001-08-13 2008-06-19 Advanced Micro Devices, Inc., Sunnyvale Speicherzelle
US6737312B2 (en) 2001-08-27 2004-05-18 Micron Technology, Inc. Method of fabricating dual PCRAM cells sharing a common electrode
US6955940B2 (en) 2001-08-29 2005-10-18 Micron Technology, Inc. Method of forming chalcogenide comprising devices
US6784018B2 (en) 2001-08-29 2004-08-31 Micron Technology, Inc. Method of forming chalcogenide comprising devices and method of forming a programmable memory cell of memory circuitry
US6881623B2 (en) * 2001-08-29 2005-04-19 Micron Technology, Inc. Method of forming chalcogenide comprising devices, method of forming a programmable memory cell of memory circuitry, and a chalcogenide comprising device
US6646902B2 (en) 2001-08-30 2003-11-11 Micron Technology, Inc. Method of retaining memory state in a programmable conductor RAM
US6709958B2 (en) * 2001-08-30 2004-03-23 Micron Technology, Inc. Integrated circuit device and fabrication using metal-doped chalcogenide materials
WO2003032392A2 (en) * 2001-10-09 2003-04-17 Axon Technologies Corporation Programmable microelectronic device, structure, and system, and method of forming the same
US6815818B2 (en) 2001-11-19 2004-11-09 Micron Technology, Inc. Electrode structure for use in an integrated circuit
US6791859B2 (en) * 2001-11-20 2004-09-14 Micron Technology, Inc. Complementary bit PCRAM sense amplifier and method of operation
US6873538B2 (en) * 2001-12-20 2005-03-29 Micron Technology, Inc. Programmable conductor random access memory and a method for writing thereto
US6909656B2 (en) 2002-01-04 2005-06-21 Micron Technology, Inc. PCRAM rewrite prevention
US20030143782A1 (en) * 2002-01-31 2003-07-31 Gilton Terry L. Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures
KR100433407B1 (ko) * 2002-02-06 2004-05-31 삼성광주전자 주식회사 업라이트형 진공청소기
US6867064B2 (en) * 2002-02-15 2005-03-15 Micron Technology, Inc. Method to alter chalcogenide glass for improved switching characteristics
US6791885B2 (en) * 2002-02-19 2004-09-14 Micron Technology, Inc. Programmable conductor random access memory and method for sensing same
US6809362B2 (en) * 2002-02-20 2004-10-26 Micron Technology, Inc. Multiple data state memory cell
US6847535B2 (en) 2002-02-20 2005-01-25 Micron Technology, Inc. Removable programmable conductor memory card and associated read/write device and method of operation
US7087919B2 (en) * 2002-02-20 2006-08-08 Micron Technology, Inc. Layered resistance variable memory device and method of fabrication
US6891749B2 (en) * 2002-02-20 2005-05-10 Micron Technology, Inc. Resistance variable ‘on ’ memory
US7151273B2 (en) * 2002-02-20 2006-12-19 Micron Technology, Inc. Silver-selenide/chalcogenide glass stack for resistance variable memory
US6937528B2 (en) * 2002-03-05 2005-08-30 Micron Technology, Inc. Variable resistance memory and method for sensing same
US6849868B2 (en) 2002-03-14 2005-02-01 Micron Technology, Inc. Methods and apparatus for resistance variable material cells
US6751114B2 (en) * 2002-03-28 2004-06-15 Micron Technology, Inc. Method for programming a memory cell
US6855975B2 (en) * 2002-04-10 2005-02-15 Micron Technology, Inc. Thin film diode integrated with chalcogenide memory cell
US6858482B2 (en) * 2002-04-10 2005-02-22 Micron Technology, Inc. Method of manufacture of programmable switching circuits and memory cells employing a glass layer
US6864500B2 (en) * 2002-04-10 2005-03-08 Micron Technology, Inc. Programmable conductor memory cell structure
US6731528B2 (en) * 2002-05-03 2004-05-04 Micron Technology, Inc. Dual write cycle programmable conductor memory system and method of operation
US6825135B2 (en) 2002-06-06 2004-11-30 Micron Technology, Inc. Elimination of dendrite formation during metal/chalcogenide glass deposition
US6890790B2 (en) * 2002-06-06 2005-05-10 Micron Technology, Inc. Co-sputter deposition of metal-doped chalcogenides
US7015494B2 (en) * 2002-07-10 2006-03-21 Micron Technology, Inc. Assemblies displaying differential negative resistance
US7209378B2 (en) * 2002-08-08 2007-04-24 Micron Technology, Inc. Columnar 1T-N memory cell structure
US7018863B2 (en) * 2002-08-22 2006-03-28 Micron Technology, Inc. Method of manufacture of a resistance variable memory cell
US6867114B2 (en) 2002-08-29 2005-03-15 Micron Technology Inc. Methods to form a memory cell with metal-rich metal chalcogenide
US7010644B2 (en) 2002-08-29 2006-03-07 Micron Technology, Inc. Software refreshed memory device and method
US7163837B2 (en) 2002-08-29 2007-01-16 Micron Technology, Inc. Method of forming a resistance variable memory element
US6831019B1 (en) 2002-08-29 2004-12-14 Micron Technology, Inc. Plasma etching methods and methods of forming memory devices comprising a chalcogenide comprising layer received operably proximate conductive electrodes
US7364644B2 (en) * 2002-08-29 2008-04-29 Micron Technology, Inc. Silver selenide film stoichiometry and morphology control in sputter deposition
US6867996B2 (en) * 2002-08-29 2005-03-15 Micron Technology, Inc. Single-polarity programmable resistance-variable memory element
US6864521B2 (en) * 2002-08-29 2005-03-08 Micron Technology, Inc. Method to control silver concentration in a resistance variable memory element
US7294527B2 (en) 2002-08-29 2007-11-13 Micron Technology Inc. Method of forming a memory cell
US20040040837A1 (en) * 2002-08-29 2004-03-04 Mcteer Allen Method of forming chalcogenide sputter target
US7012276B2 (en) * 2002-09-17 2006-03-14 Advanced Micro Devices, Inc. Organic thin film Zener diodes
US6813178B2 (en) * 2003-03-12 2004-11-02 Micron Technology, Inc. Chalcogenide glass constant current device, and its method of fabrication and operation
US7022579B2 (en) * 2003-03-14 2006-04-04 Micron Technology, Inc. Method for filling via with metal
US7050327B2 (en) * 2003-04-10 2006-05-23 Micron Technology, Inc. Differential negative resistance memory
US6930909B2 (en) 2003-06-25 2005-08-16 Micron Technology, Inc. Memory device and methods of controlling resistance variation and resistance profile drift
US6961277B2 (en) * 2003-07-08 2005-11-01 Micron Technology, Inc. Method of refreshing a PCRAM memory device
US7061004B2 (en) * 2003-07-21 2006-06-13 Micron Technology, Inc. Resistance variable memory elements and methods of formation
US6903361B2 (en) * 2003-09-17 2005-06-07 Micron Technology, Inc. Non-volatile memory structure
US7251118B2 (en) * 2003-10-02 2007-07-31 Donald Nevin Method and apparatus for large scale storage of electrical potential
US7098068B2 (en) * 2004-03-10 2006-08-29 Micron Technology, Inc. Method of forming a chalcogenide material containing device
US7583551B2 (en) * 2004-03-10 2009-09-01 Micron Technology, Inc. Power management control and controlling memory refresh operations
US7326950B2 (en) * 2004-07-19 2008-02-05 Micron Technology, Inc. Memory device with switching glass layer
US7190048B2 (en) * 2004-07-19 2007-03-13 Micron Technology, Inc. Resistance variable memory device and method of fabrication
US7354793B2 (en) * 2004-08-12 2008-04-08 Micron Technology, Inc. Method of forming a PCRAM device incorporating a resistance-variable chalocogenide element
US7365411B2 (en) * 2004-08-12 2008-04-29 Micron Technology, Inc. Resistance variable memory with temperature tolerant materials
US7151688B2 (en) * 2004-09-01 2006-12-19 Micron Technology, Inc. Sensing of resistance variable memory devices
US7374174B2 (en) * 2004-12-22 2008-05-20 Micron Technology, Inc. Small electrode for resistance variable devices
US20060131555A1 (en) * 2004-12-22 2006-06-22 Micron Technology, Inc. Resistance variable devices with controllable channels
US7317200B2 (en) 2005-02-23 2008-01-08 Micron Technology, Inc. SnSe-based limited reprogrammable cell
US7427770B2 (en) 2005-04-22 2008-09-23 Micron Technology, Inc. Memory array for increased bit density
US7709289B2 (en) 2005-04-22 2010-05-04 Micron Technology, Inc. Memory elements having patterned electrodes and method of forming the same
US7269044B2 (en) 2005-04-22 2007-09-11 Micron Technology, Inc. Method and apparatus for accessing a memory array
US7269079B2 (en) * 2005-05-16 2007-09-11 Micron Technology, Inc. Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory
US7233520B2 (en) * 2005-07-08 2007-06-19 Micron Technology, Inc. Process for erasing chalcogenide variable resistance memory bits
US7274034B2 (en) * 2005-08-01 2007-09-25 Micron Technology, Inc. Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
US7332735B2 (en) * 2005-08-02 2008-02-19 Micron Technology, Inc. Phase change memory cell and method of formation
US7317567B2 (en) * 2005-08-02 2008-01-08 Micron Technology, Inc. Method and apparatus for providing color changing thin film material
US20070037316A1 (en) * 2005-08-09 2007-02-15 Micron Technology, Inc. Memory cell contact using spacers
US7579615B2 (en) * 2005-08-09 2009-08-25 Micron Technology, Inc. Access transistor for memory device
US7304368B2 (en) * 2005-08-11 2007-12-04 Micron Technology, Inc. Chalcogenide-based electrokinetic memory element and method of forming the same
US7251154B2 (en) 2005-08-15 2007-07-31 Micron Technology, Inc. Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
US7277313B2 (en) * 2005-08-31 2007-10-02 Micron Technology, Inc. Resistance variable memory element with threshold device and method of forming the same
US7560723B2 (en) * 2006-08-29 2009-07-14 Micron Technology, Inc. Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication
US10134985B2 (en) 2006-10-20 2018-11-20 The Regents Of The University Of Michigan Non-volatile solid state resistive switching devices
US8467236B2 (en) * 2008-08-01 2013-06-18 Boise State University Continuously variable resistor
KR20110086089A (ko) 2008-10-20 2011-07-27 더 리젠츠 오브 더 유니버시티 오브 미시건 실리콘계 나노스케일 크로스바 메모리
US8547727B2 (en) * 2008-12-12 2013-10-01 Hewlett-Packard Development Company, L.P. Memristive device
US8384401B2 (en) * 2010-03-31 2013-02-26 Hewlett-Packard Development Company, L.P. Fast time-tagged event detection using resistive switching devices
US9601692B1 (en) 2010-07-13 2017-03-21 Crossbar, Inc. Hetero-switching layer in a RRAM device and method
US8946046B1 (en) 2012-05-02 2015-02-03 Crossbar, Inc. Guided path for forming a conductive filament in RRAM
US9570678B1 (en) 2010-06-08 2017-02-14 Crossbar, Inc. Resistive RAM with preferental filament formation region and methods
US9012307B2 (en) 2010-07-13 2015-04-21 Crossbar, Inc. Two terminal resistive switching device structure and method of fabricating
US8441835B2 (en) 2010-06-11 2013-05-14 Crossbar, Inc. Interface control for improved switching in RRAM
CN103081093B (zh) 2010-06-11 2015-06-03 科洛斯巴股份有限公司 存储器件的柱结构以及方法
US8374018B2 (en) 2010-07-09 2013-02-12 Crossbar, Inc. Resistive memory using SiGe material
US8168506B2 (en) 2010-07-13 2012-05-01 Crossbar, Inc. On/off ratio for non-volatile memory device and method
US8569172B1 (en) 2012-08-14 2013-10-29 Crossbar, Inc. Noble metal/non-noble metal electrode for RRAM applications
US8467227B1 (en) 2010-11-04 2013-06-18 Crossbar, Inc. Hetero resistive switching material layer in RRAM device and method
US8947908B2 (en) 2010-11-04 2015-02-03 Crossbar, Inc. Hetero-switching layer in a RRAM device and method
US8884261B2 (en) 2010-08-23 2014-11-11 Crossbar, Inc. Device switching using layered device structure
JP2012039042A (ja) * 2010-08-11 2012-02-23 Sony Corp メモリ素子
US8404553B2 (en) 2010-08-23 2013-03-26 Crossbar, Inc. Disturb-resistant non-volatile memory device and method
US9401475B1 (en) 2010-08-23 2016-07-26 Crossbar, Inc. Method for silver deposition for a non-volatile memory device
US8889521B1 (en) 2012-09-14 2014-11-18 Crossbar, Inc. Method for silver deposition for a non-volatile memory device
US8492195B2 (en) 2010-08-23 2013-07-23 Crossbar, Inc. Method for forming stackable non-volatile resistive switching memory devices
US8558212B2 (en) 2010-09-29 2013-10-15 Crossbar, Inc. Conductive path in switching material in a resistive random access memory device and control
US8391049B2 (en) 2010-09-29 2013-03-05 Crossbar, Inc. Resistor structure for a non-volatile memory device and method
US8502185B2 (en) 2011-05-31 2013-08-06 Crossbar, Inc. Switching device having a non-linear element
USRE46335E1 (en) 2010-11-04 2017-03-07 Crossbar, Inc. Switching device having a non-linear element
US8088688B1 (en) 2010-11-05 2012-01-03 Crossbar, Inc. p+ polysilicon material on aluminum for non-volatile memory device and method
US8930174B2 (en) 2010-12-28 2015-01-06 Crossbar, Inc. Modeling technique for resistive random access memory (RRAM) cells
US8791010B1 (en) 2010-12-31 2014-07-29 Crossbar, Inc. Silver interconnects for stacked non-volatile memory device and method
US8815696B1 (en) 2010-12-31 2014-08-26 Crossbar, Inc. Disturb-resistant non-volatile memory device using via-fill and etchback technique
US9153623B1 (en) 2010-12-31 2015-10-06 Crossbar, Inc. Thin film transistor steering element for a non-volatile memory device
US8450710B2 (en) 2011-05-27 2013-05-28 Crossbar, Inc. Low temperature p+ silicon junction material for a non-volatile memory device
US9620206B2 (en) 2011-05-31 2017-04-11 Crossbar, Inc. Memory array architecture with two-terminal memory cells
US8394670B2 (en) 2011-05-31 2013-03-12 Crossbar, Inc. Vertical diodes for non-volatile memory device
US8619459B1 (en) 2011-06-23 2013-12-31 Crossbar, Inc. High operating speed resistive random access memory
US9166163B2 (en) 2011-06-30 2015-10-20 Crossbar, Inc. Sub-oxide interface layer for two-terminal memory
US9564587B1 (en) 2011-06-30 2017-02-07 Crossbar, Inc. Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects
US8659929B2 (en) 2011-06-30 2014-02-25 Crossbar, Inc. Amorphous silicon RRAM with non-linear device and operation
US8946669B1 (en) 2012-04-05 2015-02-03 Crossbar, Inc. Resistive memory device and fabrication methods
US9627443B2 (en) 2011-06-30 2017-04-18 Crossbar, Inc. Three-dimensional oblique two-terminal memory with enhanced electric field
EP2735028A4 (de) 2011-07-22 2015-05-06 Crossbar Inc Saatschicht für a p+siliziumgermaniummaterial für einen nichtflüchtigen speicher und verfahren
US10056907B1 (en) 2011-07-29 2018-08-21 Crossbar, Inc. Field programmable gate array utilizing two-terminal non-volatile memory
US8674724B2 (en) 2011-07-29 2014-03-18 Crossbar, Inc. Field programmable gate array utilizing two-terminal non-volatile memory
US9729155B2 (en) 2011-07-29 2017-08-08 Crossbar, Inc. Field programmable gate array utilizing two-terminal non-volatile memory
US8716098B1 (en) 2012-03-09 2014-05-06 Crossbar, Inc. Selective removal method and structure of silver in resistive switching device for a non-volatile memory device
US9087576B1 (en) 2012-03-29 2015-07-21 Crossbar, Inc. Low temperature fabrication method for a three-dimensional memory device and structure
US9685608B2 (en) 2012-04-13 2017-06-20 Crossbar, Inc. Reduced diffusion in metal electrode for two-terminal memory
US8658476B1 (en) 2012-04-20 2014-02-25 Crossbar, Inc. Low temperature P+ polycrystalline silicon material for non-volatile memory device
US8796658B1 (en) 2012-05-07 2014-08-05 Crossbar, Inc. Filamentary based non-volatile resistive memory device and method
US8765566B2 (en) 2012-05-10 2014-07-01 Crossbar, Inc. Line and space architecture for a non-volatile memory device
US9583701B1 (en) 2012-08-14 2017-02-28 Crossbar, Inc. Methods for fabricating resistive memory device switching material using ion implantation
US10096653B2 (en) 2012-08-14 2018-10-09 Crossbar, Inc. Monolithically integrated resistive memory using integrated-circuit foundry compatible processes
US8946673B1 (en) 2012-08-24 2015-02-03 Crossbar, Inc. Resistive switching device structure with improved data retention for non-volatile memory device and method
US9312483B2 (en) 2012-09-24 2016-04-12 Crossbar, Inc. Electrode structure for a non-volatile memory device and method
US9576616B2 (en) 2012-10-10 2017-02-21 Crossbar, Inc. Non-volatile memory with overwrite capability and low write amplification
US11068620B2 (en) 2012-11-09 2021-07-20 Crossbar, Inc. Secure circuit integrated with memory layer
US8982647B2 (en) 2012-11-14 2015-03-17 Crossbar, Inc. Resistive random access memory equalization and sensing
US9412790B1 (en) 2012-12-04 2016-08-09 Crossbar, Inc. Scalable RRAM device architecture for a non-volatile memory device and method
US9406379B2 (en) 2013-01-03 2016-08-02 Crossbar, Inc. Resistive random access memory with non-linear current-voltage relationship
US9112145B1 (en) 2013-01-31 2015-08-18 Crossbar, Inc. Rectified switching of two-terminal memory via real time filament formation
US9324942B1 (en) 2013-01-31 2016-04-26 Crossbar, Inc. Resistive memory cell with solid state diode
US8934280B1 (en) 2013-02-06 2015-01-13 Crossbar, Inc. Capacitive discharge programming for two-terminal memory cells
CN105103291B (zh) * 2013-03-09 2018-01-16 国立研究开发法人科学技术振兴机构 电子元件
US10290801B2 (en) 2014-02-07 2019-05-14 Crossbar, Inc. Scalable silicon based resistive memory device
WO2019187032A1 (ja) * 2018-03-30 2019-10-03 富士通株式会社 抵抗変化素子及びその製造方法、記憶装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63200396A (ja) * 1987-02-16 1988-08-18 Sanyo Electric Co Ltd 導電性可変素子及び製造法
EP0291659A1 (de) * 1987-03-24 1988-11-23 Matsushita Electric Industrial Co., Ltd. Elektronisches Molekularelement
EP0419136A1 (de) * 1989-09-13 1991-03-27 Xerox Corporation Elektrische Halbleiteranordnung mit einem internen Fehlerkorrekturteil

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4839700A (en) * 1987-12-16 1989-06-13 California Institute Of Technology Solid-state non-volatile electronically programmable reversible variable resistance device
JPH0760907B2 (ja) * 1989-07-25 1995-06-28 松下電器産業株式会社 電気制御素子およびその応用装置
DE69018348T2 (de) * 1989-07-25 1995-08-03 Matsushita Electric Ind Co Ltd Speicherbauelement aus organischem Halbleiter mit einer MISFET-Struktur und sein Kontrollverfahren.
US5172204A (en) * 1991-03-27 1992-12-15 International Business Machines Corp. Artificial ionic synapse

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63200396A (ja) * 1987-02-16 1988-08-18 Sanyo Electric Co Ltd 導電性可変素子及び製造法
EP0291659A1 (de) * 1987-03-24 1988-11-23 Matsushita Electric Industrial Co., Ltd. Elektronisches Molekularelement
EP0419136A1 (de) * 1989-09-13 1991-03-27 Xerox Corporation Elektrische Halbleiteranordnung mit einem internen Fehlerkorrekturteil

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
JOURNAL OF APPLIED PHYSICS vol. 67, no. 6 , 15 March 1990 , NEW YORK US pages 3132 - 3135 S. THAKOOR ET AL 'Solid-state thin-film memistor for electronic neural networks' *
PATENT ABSTRACTS OF JAPAN vol. 12, no. 488 (P-803)20 December 1988 & JP-A-63 200 396 (SANYO ELECTRIC CO LTD) 18 August 1988 *
SOLID STATE COMMUNICATIONS vol. 73, no. 5 , 1990 , OXFORD GB pages 323 - 326 R. K\NENKAMP ET AL 'REVERSIBLE DOPING OF HYDROGANATED AMORPHOUS SILICON' *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6603143B2 (en) * 1999-03-18 2003-08-05 Hyundai Electronics Industries Co., Ltd. Semiconductor device and method for fabricating same

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EP0487101B1 (de) 2000-11-15
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