EP0476775A2 - Circuit pour compenser le courant de base d'un transistor - Google Patents

Circuit pour compenser le courant de base d'un transistor Download PDF

Info

Publication number
EP0476775A2
EP0476775A2 EP91202376A EP91202376A EP0476775A2 EP 0476775 A2 EP0476775 A2 EP 0476775A2 EP 91202376 A EP91202376 A EP 91202376A EP 91202376 A EP91202376 A EP 91202376A EP 0476775 A2 EP0476775 A2 EP 0476775A2
Authority
EP
European Patent Office
Prior art keywords
transistor
current
control
circuit arrangement
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP91202376A
Other languages
German (de)
English (en)
Other versions
EP0476775B1 (fr
EP0476775A3 (en
Inventor
Klaus Kröner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Intellectual Property and Standards GmbH
Koninklijke Philips NV
Original Assignee
Philips Patentverwaltung GmbH
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Patentverwaltung GmbH, Philips Gloeilampenfabrieken NV, Koninklijke Philips Electronics NV filed Critical Philips Patentverwaltung GmbH
Publication of EP0476775A2 publication Critical patent/EP0476775A2/fr
Publication of EP0476775A3 publication Critical patent/EP0476775A3/de
Application granted granted Critical
Publication of EP0476775B1 publication Critical patent/EP0476775B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26Current mirrors
    • G05F3/265Current mirrors using bipolar transistors only

Definitions

  • the invention relates to a circuit arrangement for compensating for the control current of a (first) transistor, the main current path of which is arranged in series with the main current path of a second transistor between the poles of a supply voltage source, with a current mirror arrangement formed from two transistors, the common connection of which to the pole of the Supply voltage source, which is coupled to the second transistor, is connected, the input terminal of which is connected to the control terminal of the second transistor and from whose output terminal a compensation current can be fed to the control terminal of the first transistor.
  • a transistor amplifier with a first transistor is known, the base of which is supplied with a signal to be amplified.
  • the emitter of the first transistor is connected via a resistor to a point of constant potential, preferably to ground.
  • the collector of the transistor is connected to the emitter of a measuring transistor.
  • the collector of the measuring transistor is connected to a supply voltage source via a second resistor.
  • the base of the measuring transistor is connected to a current input of a controlled current source, while the base of the first transistor is connected to a current output of the controlled current source.
  • a common connection point of the current source is connected to the collector of the measuring transistor.
  • the current source contains a transistor and a diode.
  • the emitter of the transistor of the current source and the anode of the diode are connected to the common connection point of the current source.
  • the collector of the transistor the current source is connected to its current output and the base of the transistor of the current source and the cathode of the diode are connected to the current input of the current source.
  • the current source in this circuit arrangement has the effect that the input current of the amplifier is reduced by a factor substantially corresponding to the base collector current amplification factor of the first transistor and of the measuring transistor.
  • a current source generally also referred to as a "Wilson current mirror”.
  • This "Wilson current mirror” contains a third and a fourth transistor and a diode.
  • the emitter of the third transistor and the anode of the diode are connected to the common connection point of the current source mentioned above.
  • the base of the third transistor and the cathode of the diode are connected to the emitter of the fourth transistor, the base of which is connected to the collector of the third transistor.
  • the collector of the fourth transistor is connected to the output of the "Wilson current mirror", while the collector of the third transistor is connected to the input of the "Wilson current mirror".
  • the use of the "Wilson current mirror” has the advantage over the current source described first that the currents occurring at the output and at the entrance of the "Wilson current mirror” coincide better with one another. An improved compensation of the base current of the first transistor can thereby be achieved.
  • the object of the invention is to create a circuit arrangement in which, on the one hand, the most complete possible compensation of the control current of the transistor amplifier is achieved and, on the other hand, which offers the highest possible modulation range of the transistor even at low supply voltages.
  • This object is achieved in a circuit arrangement of the generic type by a third transistor, via the main current path of the compensation current and the control connection of which is connected to the connection point of the main current paths of the first and second transistors.
  • the favorable properties of the circuit arrangements known from the prior art are connected to one another in a simple and advantageous manner.
  • the voltage level at the collector of the (first) transistor of the transistor amplifier is reduced by only two base-emitter forward voltages compared to the supply voltage, while at the same time one Compensation of the control current is achieved, as was previously only possible with the "Wilson current mirror".
  • the invention is preferably carried out with transistors of the bipolar type.
  • the first and second transistors are of a first and the remaining transistors are of a second conductivity type, as a result of which a structure which is particularly favorable for integration on a semiconductor body is also obtained.
  • the figure shows an embodiment of a circuit arrangement according to the invention with a first transistor 1 forming a transistor amplifier, the base connection of which is connected to an input 2 for a signal to be amplified.
  • a control current is supplied to the first transistor 1, which is of the NPN type in the present example, via the base connection.
  • This control current is to be compensated in such a way that the lowest possible signal current flows at input 2, preferably that input 2 is de-energized.
  • the circuit arrangement according to the invention for compensating for the control current of the first transistor 1 comprises a second transistor 3, which is also referred to as a measuring transistor.
  • This measuring transistor 3 is also of the NPN type and with its main current path between the collector and emitter connected in series with the corresponding main current path of the first transistor 1 such that the emitter of the measuring transistor 3 is coupled to the collector of the first transistor 1, while the collector of the Measuring transistor 3 is connected to a positive supply voltage terminal 4.
  • In series with the main current paths is between the emitter of the first transistor 1 and ground also switched a DC power source 5 for setting the operating point.
  • the positive supply voltage connection 4 and ground form the poles of the supply voltage source.
  • the circuit arrangement according to the present exemplary embodiment furthermore comprises a current mirror arrangement comprising a first current mirror transistor 6 and a second current mirror transistor 7, the emitters of which are connected to one another and to the base of the measuring transistor 3 together with the supply voltage connection 4 and the base connections thereof.
  • the collector of the first current mirror transistor 6 is connected to the base connections of the transistors 3, 6 and 7.
  • the connection between the base connections of the current mirror transistors 6, 7 and the collector of the first current mirror transistor 6 forms the input connection of the current mirror arrangement 6, 7.
  • Their output connection is formed by the collector of the second current mirror transistor 7 and is connected to the input 2 via the main current path of a third transistor 8 and thus connected to the base of the first transistor 1.
  • base-emitter forward voltages occurring on the transistors during operation of the circuit arrangement are entered with UBE, specifically on the base-emitter paths of the current mirror transistors 6, 7, the measuring transistor 3 and the third transistor 8.
  • At the collector of the second current mirror transistor 7 is at the same potential during operation as at the base of the measuring transistor 3 and thus on the collector of the first current mirror transistor 6.
  • the current mirror transistors 6, 7 thus have the same collector-emitter voltages, so that a particularly symmetrical operating mode of the current mirror 6, 7 is achieved.
  • the potential at the connection point 9 is only two base-emitter forward voltages UBE lower than the supply voltage at the supply voltage connection 4.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)
EP91202376A 1990-09-21 1991-09-17 Circuit pour compenser le courant de base d'un transistor Expired - Lifetime EP0476775B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4029889 1990-09-21
DE4029889A DE4029889A1 (de) 1990-09-21 1990-09-21 Schaltungsanordnung zum kompensieren des steuerstromes eines transistors

Publications (3)

Publication Number Publication Date
EP0476775A2 true EP0476775A2 (fr) 1992-03-25
EP0476775A3 EP0476775A3 (en) 1992-10-21
EP0476775B1 EP0476775B1 (fr) 1995-12-06

Family

ID=6414666

Family Applications (1)

Application Number Title Priority Date Filing Date
EP91202376A Expired - Lifetime EP0476775B1 (fr) 1990-09-21 1991-09-17 Circuit pour compenser le courant de base d'un transistor

Country Status (4)

Country Link
US (1) US5179356A (fr)
EP (1) EP0476775B1 (fr)
JP (1) JP3263410B2 (fr)
DE (2) DE4029889A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311147A (en) * 1992-10-26 1994-05-10 Motorola Inc. High impedance output driver stage and method therefor
US5864231A (en) * 1995-06-02 1999-01-26 Intel Corporation Self-compensating geometry-adjusted current mirroring circuitry
US7271645B2 (en) * 2005-09-30 2007-09-18 Ana Semiconductor Smart charge-pump circuit for phase-locked loops
KR100796974B1 (ko) * 2006-07-06 2008-01-22 한국과학기술원 전류공급회로 및 이를 포함하는 디지털 아날로그 변환기

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3714600A (en) * 1967-12-13 1973-01-30 Philips Corp Transistor amplifier
US3800239A (en) * 1972-11-24 1974-03-26 Texas Instruments Inc Current-canceling circuit
US4451800A (en) * 1980-09-27 1984-05-29 Pioneer Electronic Corporation Input bias adjustment circuit for amplifier
US4755770A (en) * 1986-08-13 1988-07-05 Harris Corporation Low noise current spectral density input bias current cancellation scheme

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7316556A (nl) * 1973-12-04 1975-06-06 Philips Nv Stroomstabilisatieschakeling.
JPS607845B2 (ja) * 1979-09-21 1985-02-27 パイオニア株式会社 増幅器
NL8301186A (nl) * 1983-04-05 1984-11-01 Philips Nv Stroomstabilisatieschakeling.
JPS6077506A (ja) * 1983-10-04 1985-05-02 Sharp Corp 電圧発生回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3714600A (en) * 1967-12-13 1973-01-30 Philips Corp Transistor amplifier
US3800239A (en) * 1972-11-24 1974-03-26 Texas Instruments Inc Current-canceling circuit
US4451800A (en) * 1980-09-27 1984-05-29 Pioneer Electronic Corporation Input bias adjustment circuit for amplifier
US4755770A (en) * 1986-08-13 1988-07-05 Harris Corporation Low noise current spectral density input bias current cancellation scheme

Also Published As

Publication number Publication date
DE4029889A1 (de) 1992-03-26
JP3263410B2 (ja) 2002-03-04
EP0476775B1 (fr) 1995-12-06
DE59107022D1 (de) 1996-01-18
JPH06326526A (ja) 1994-11-25
US5179356A (en) 1993-01-12
EP0476775A3 (en) 1992-10-21

Similar Documents

Publication Publication Date Title
DE2603164A1 (de) Differentialverstaerker
DE2358471A1 (de) Stromaufhebungsschaltung
DE3035272A1 (de) Operations-transkonduktanzverstaerker mit einer nichtlineare komponente aufweisenden stromverstaerkern
DE2653624A1 (de) Videosignalverstaerker
DE1487396A1 (de) Schaltungsanordnung zum Erzeugen einer Steuer- oder Kompensationsspannung
DE2905659B2 (de) Gegentakt-Verstärkerkreis
DE2438255A1 (de) Stromverstaerker
DE2529966C3 (de) Transistorverstärker
DE2506034C3 (de) Schaltungsanordnung zum elektronischen Durchschalten einer Wechselspannung
DE3545392C2 (fr)
DE2636156B2 (de) Spannungsfolger-Schaltung mit einer Eingangsklemme
DE2438883B2 (de) Durch rueckkopplung stabilisierte verstaerkeranordnung
EP0476775B1 (fr) Circuit pour compenser le courant de base d'un transistor
DE2924171C2 (fr)
DE69112104T2 (de) Verstärkerschaltung.
DE69018870T2 (de) Bipolare Transistorschaltung mit Verzerrungsausgleich.
DE2853581C2 (de) Emitterfolgerschaltung
EP0237086B1 (fr) Circuit de miroir de courant
DE3243706C1 (de) ECL-TTL-Signalpegelwandler
DE3687446T2 (de) Symmetrischer oszillator.
DE3607064A1 (de) Steuerschaltung mit kompensation der anodenspannungs-schwankungen fuer die vertikalablenkstufe eines fernsehgeraets
DE69303063T2 (de) Gegentaktausgangsstufe für integrierten Verstärker
DE3716577C2 (de) Stromspiegelschaltung großer Leistungsfähigkeit
DE2148880C2 (de) Stromquelle in integrierter Schaltungstechnik
DE69214189T2 (de) Transistorverstärker mit direkter Kopplung

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB IT NL

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB IT NL

17P Request for examination filed

Effective date: 19930405

17Q First examination report despatched

Effective date: 19940728

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT NL

REF Corresponds to:

Ref document number: 59107022

Country of ref document: DE

Date of ref document: 19960118

ITF It: translation for a ep patent filed
GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 19960226

ET Fr: translation filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 19960924

Year of fee payment: 6

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19980401

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee

Effective date: 19980401

REG Reference to a national code

Ref country code: FR

Ref legal event code: CD

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20010925

Year of fee payment: 11

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20011001

Year of fee payment: 11

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20011121

Year of fee payment: 11

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020917

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030401

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20020917

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030603

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20050917