EP0468027A1 - Decodeur pour television hd-mac - Google Patents

Decodeur pour television hd-mac

Info

Publication number
EP0468027A1
EP0468027A1 EP19910903857 EP91903857A EP0468027A1 EP 0468027 A1 EP0468027 A1 EP 0468027A1 EP 19910903857 EP19910903857 EP 19910903857 EP 91903857 A EP91903857 A EP 91903857A EP 0468027 A1 EP0468027 A1 EP 0468027A1
Authority
EP
European Patent Office
Prior art keywords
signals
input
output
samples
interpolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19910903857
Other languages
German (de)
English (en)
Inventor
Peter Hubertus Frencken
Willem Peter Gerardus Crooymans
Philippe Antoine Maurice Van Overmeire
Sandro Giovanni Colombo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB909002991A external-priority patent/GB9002991D0/en
Application filed by Philips Gloeilampenfabrieken NV, Koninklijke Philips Electronics NV filed Critical Philips Gloeilampenfabrieken NV
Publication of EP0468027A1 publication Critical patent/EP0468027A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems
    • H04N7/0152—High-definition television systems using spatial or temporal subsampling
    • H04N7/0155—High-definition television systems using spatial or temporal subsampling using pixel blocks

Definitions

  • HD-MAC television decoder
  • the invention relates to a decoder for a high definition television system, in particular the HD-MAC system adopted by the European cooperation program called Eureka.
  • EP-A-0,330,279 (PHF 88507) describes several aspects of this HD-MAC system which includes a bandwidth reduction encoder at the transmission end and a cor ⁇ responding decoder at the receiving end.
  • the -signal source (camera) 0 provides a 1250 lines, 50 Hz field rate, 2:1 interlaced signal and a 625 lines, 50 Hz, 2:1 signal is transmitted.
  • the transmit ⁇ ted video signal is accompanied by a digital signal giving t additional information for control,, and timing of the video signal processing system.
  • Such a system may be referred to as 5 digital assisted television (DATV) .
  • DATV digital assisted television
  • the invention provides thereto a ' decoder apparatus for decoding input signals divided into a plurality of adjacent blocks encoded in accordance with a selected one of a plurality of coding modes, each coding mode having an associated sampling pattern, which has input means coupled to receive said input signals for furnishing samples from a present field and from a plurality of preceding fields, first decoding means coupled to said input means for processing samples from blocks sampled in accordance with a first sampling pattern, second decoding means requiring samples from a plurality of temporally sequential blocks sampled in accordance with a second sampling pattern, and selector means for selectively coupling said input means or said first decoding means to said second decoding means to furnish said required samples to said second decoding means.
  • the decoder apparatus also has combined vertical contour correction and interpolation means, in the form of weighting constants accommodating both functions and applied to samples being processed.
  • a multipurpose integrated circuit has a plurality of data inputs, a plurality of data outputs a plurality of processing circuits, a plurality of interconnectable delay members, controllable selector means for connecting said delay members to each other to form selected delays and for connecting said selected delays to said proces ⁇ sing circuits at least in part in response to selector controls signals, externally loaded look-up table means for furnishing said selector control signals in response to externally applied chip control signals, and output means connected to said proces ⁇ sing circuits and said data outputs-for furnishing output sam- pies including processed samples in response to data applied at said data inputs.
  • a decoder apparatus has input means for receiving input signals, first memory means for receiving said input signals and furnishing once delayed signals at a first memory output, second memory means receiving said once delayed signals only during alternate ones of consecutive predetermined time intervals, third memory means receiving said once delayed signals' only during the remai ⁇ ning ones of said consecutive time intervals, and output means coupled to said first, second and third memory means, for fur ⁇ nishing output signals comprising, in parallel once, twice and three times delayed input signals.
  • Fig. la is a schematic diagram of the luminance interpola ⁇ tion part of an HD-MAC decoder in accordance with the present invention.
  • Fig. lb is a schematic diagram of the chrominance interpo- lation part of an HD-MAC decoder embodiment
  • Fig. lc shows sampling patterns corresponding to the three processing branches of the Eureka HD-MAC system
  • Fig. 2A-D schematically show how input samples for the 80 ms mode interpolator are obtained in an HD-MAC decoder according to the invention
  • Fig. 3 is a block diagram of a first embodiment of one branch of the 40 ms mode motion compensated interpolator;
  • Fig. 4 is a block diagram of a second embodiment of the 40 ms mode motion compensated interpolator branch having fewer line memories;
  • Fig. 5 shows the difference between the filter characteris- tics of a filter shown in Fig. 3 and a filter shown in Fig. 4;
  • Fig. 6 is a block diagram of a third embodiment of the 40 ms mode motion compensated interpolator branch
  • Fig. 7 is a block diagram of a fourth embodiment of the 40 ms mode motion compensated interpolator branch;
  • Fig. 8 is a block diagram of a fifth embodiment of the 40 ms mode motion compensated interpolator branch;
  • Fig. 9 shows the internal block diagram of a flexible filter block according to the invention.
  • Fig. 10a shows a block diagram of the data interfaces of a decoder according to the invention
  • Fig. 10b is a block diagram of the control interfaces
  • Fig. 11 shows the section of Fig. 10a concerning the 40 ms mode motion compensated interpolator in more detail
  • Fig. 12 shows the section of Fig. 10a concerning the multi- plexing of 40 ms mode interpolator output samples and 20 or 80 ms mode interpolator input samples in more detail;
  • Fig. 13 shows the section of Fig. 10a concerning the 20 and 80 ms mode interpolation in more detail
  • Fig. 14 shows the section of Fig. 10a concerning the hori- zontal chrominance interpolation in more detail
  • Fig. 15 schematically shows the interpolation of 80 ms mode chrominance samples
  • Fig. 16 shows the section of Fig. 10a concerning the verti ⁇ cal chrominance interpolation in more detail
  • Fig. 17 shows the frequency response of a horizontal lumi ⁇ nance upconversion filter according to the invention for upcon- version of a 4:3 aspect ratio input signal
  • Figs. 18, 19 and 20 show the sections of Figs. 11, 12 and 13, respectively, when configured to operate in a luminance upconversion mode
  • Figs. 21 shows a frequency response of a horizontal lumi ⁇ nance upconversion filter according to the invention for upcon- version of a 16:9 aspect ratio input signal
  • Figs. 22 shows a frequency response of a horizontal chromi ⁇ nance upconversion filter according to the invention for upcon ⁇ version of a 4:3 aspect ratio input signal
  • Fig. 23 shows the sections of Figs. 14 and 16, respective ⁇ ly, when configured to operate in a chrominance upconversion mode
  • Fig. 24 shows a frequency response of a horizontal chromi ⁇ nance upconversion filter according to the invention for upcon- version of a 16:9 aspect ratio input signal.
  • the overall block diagram of an HD-MAC decoder according to the present invention is shown in Figs, la and lb, for the luminance and chrominance signal components, respectively.
  • the signal received by the decoder was encoded at the transmitting end by bandwidth reduction processing of the scanned image (camera) signal in three processing paths, each having its own associated sampling pattern in accordance with the amount of motion in the picture.
  • a detailed description of such an enco ⁇ ding system can be found, for example, in European Patent Appli ⁇ cation EP-A 0,322,965 (PHN 12,440). Briefly, the three separate processing paths are associated, respectively, with temporal refresh rates of 20 ms, 40 ms and 80 ms.
  • the lowest temporal resolution, 80 ms, is accompanied by the highest spatial resolu ⁇ tion, and vice versa, so that the processed signal has a lower bandwidth than the scanned image (camera) signal and is suitable for recording, for transmission over a limited bandwidth chan ⁇ nel, and for reception and processing by presently used MAC receivers, as well as the new HDTV receivers.
  • the field rate is 12.5 Hz and the basic interval is 80 ms. Whe * there is more movement, the field rate is 25 Hz and the basic interval is 40 ms, while in the rapid movement mode the field rate is 50 Hz and the basic interval" is 20 ms.
  • These constants are appropriate for the HD-MAC system chosen by Eureka. Other time and spatial intervals may be appropriate for other systems.
  • the sampling patterns associated with these basic intervals are illustrated in Fig. lc. It should be noted that the image is divided into image blocks each having 16*16 pixels at the encoder. Part of a block at each of the refresh rates is illustrated.
  • x signifies samples to be transmitted
  • the dots indicate samples not to be transmitted
  • 1, 2, 3, 4 are the field numbers in which the particular sample is to be transmitted. It should be noted that for the 80 ms branch, illustrated in Fig. lc as A', B', subsampling takes place in units of 4 sequential fields. Samples to be transmitted in fields 1, 2, 3, or 4 are derived from the corresponding fields in the input sequence.
  • a 20 ms branch, E 1 and F' of Fig. lc, has the same subsam ⁇ pling pattern as the first two fields of the 80 ms pattern. This branch represents the highest temporal and lowest spatial reso ⁇ lution.
  • line shuffling takes place where required to decrease the transmitted number of lines per field and increase the line length to accommodate the transmis ⁇ sion standard and to allow processing by a conventional MAC receiver.
  • pattern B 1 the samples indi ⁇ cated by "1" from line 3 occupy the positions indicated by "3" on line 1 in the first field after line shuffling.
  • the "2" sample of line 4 is transmitted on line 2. It will be noted that line shuffling is not necessary in the 40 ms branch.
  • the luminance component of above described transmitted or recorded signal is applied to input 1 of the luminance deco ⁇ der illustrated in Fig. la.
  • the signal is applied to a temporal filter 8, which comprises one field memory FM1.
  • a temporal filter 8 which comprises one field memory FM1.
  • the 40 ms mode blocks output by the HD-MAC encoder are temporally filtered before transmission or recording.
  • the temporal filter 8 applies an inverse temporal filtering which compensates for the temporal filtering applied at the encoder side.
  • the field memory FM1 present in the temporal filter 8 is advantageously used as one of the field delays required for the HD-MAC decoding, thus saving one field memory. Therefore, temporal filter 8 outputs both a delayed and an undelayed signal at its outputs.
  • the signals output by temporal filter 8 undergo line des- huffling in a deshuffler stage 10.
  • the deshuffling operation takes place under control of a DATV signal applied to a control input 11 of the deshuffler stage 10. Since the control inputs do not contribute to the understanding of the present invention, they will be omitted or only sketchily indicated in the figures.
  • the deshuffled signals are applied to a field delay stage 12 which, in the embodiment shown, includes two field delays FM2 and FM3.
  • the particular interconnection of the field memories to accommodate high data rates will be discussed below with refe ⁇ rence to Fig. 10. There are thus available four signals mutually delayed by one field period.
  • the four signals derived from the field delay stage 12 are applied to a subsample pattern converter 14. Since the received sampling patterns are each associated with pixel blocks of small size (e.g. 16 x 16), the received signal will have many sampling blocks adjoining blocks of a different sampling pattern. Since the interpolators may need samples within the adjoining blocks for interpolating edge positions on a given block, subsample pattern converter 14 converts the sampling pattern of each incoming block to both the 80 ms and 40 ms sampling patterns. Specifically, a field A with the subsample pattern associated with the recombined first and second transmitted fields (i.e.
  • a field C with the subsample pattern associated with the recombi ⁇ ned third and fourth transmitted fields is furnished on a line ss40C, to respective 40 ms mode interpolator stages 16 and 18, where they are subjected to non ⁇ linear interpolation and vertical contour correction.
  • Even (E) and odd (0) samples are furnished at outputs 40A-O, 40A-E and 40C-0, 40C-E of the stages 16 and 18.
  • stages 20 and 22 delay the samples from stages 16 and 18, res ⁇ pectively, in accordance with the motion vectors (applied to inputs 20a) and branch decision signals (applied to inputs 20b) derived from the digital assisting DATV signal.
  • the outputs from stages 20 and 22 are applied, respectively, to gain selecting stages 24 and 26.
  • the gains of stages 24 and 26 are both adjusted to 0.5.
  • the gain of stage 24 is switched to unity, while that of stage 26 is adjusted to 0.
  • the gain is similarly adjusted, but, on a pixel basis, to imple ⁇ ment the improvement discussed below with reference to Fig. 2, which permits use of only three field memories.
  • the outputs from the "A" branch and the "C* branch are combined in an adder 27.
  • Selector stage 30 has a second pair of inputs, 40' connec- ted via a delay 32 to the ss80I and ss ⁇ OII outputs of subsample pattern converter 14. Either the first or the second input pair is connected to the output pair, (30b, 30c) , of selector 30 under control of a DATV branch decision signal at input 30a.
  • selector 30 selects the (40) input when the currently processed block is a 40 ms mode block, to furnish to the 20 and 80 ms mode interpolators the best available samples as supplied by the 40 ms mode interpolator.
  • EP-A 0,330,279 further teaches that in its decoder, selector 30 selects input 40 when the currently processed block is a 20 or 80 ms mode block, because in that case the best available samples for the 20 and 80 ms mode interpolator are supplied by subsample pattern converter 14.
  • selector 30 selects its (40) input also whenever a sample required for the 80 ms mode interpolation is not sup ⁇ plied by the subsample pattern converter 14. Further details about implementation of the above are described below with reference to Fig. 2.
  • Subsample patterns 80 I and 80 II, as present on lines 34a and 34b, respectively, are applied in parallel to a 20 ms inter ⁇ polation stage 36 and an 80 ms interpolation stage 38 for inter ⁇ polation of the remaining missing samples. Fully interpolated fields are then available at the outputs of stages 27, 36 and 38, respectively.
  • the output of adder 27 is applied to a first pair of inputs of a final selector stage 42 via a delay stage 41 which compensates for the delay of stages 30, 36 and 38.
  • the outputs of interpolators 36 and 38 are di- rectly applied to a second and third set of inputs of selector 42.
  • Selector 42 operates under control of DATV signal 42a.
  • the output of stage 42 is a 1250 line, 50 Hz, 2:1 HDTV signal.
  • each 80 ms input line in Fig. la symbolizes a pair of lines, four input values being required for the 80 ms interpolator.
  • Fig. lb is a schematic diagram of the chrominance interpo ⁇ lation part of an HD-MAC decoder embodiment.
  • the input chromi ⁇ nance component C-in is applied via a compensating delay stage 8C to chrominance deshuffler (DESHUF C) 10C, which is controlled by a control signal applied to its input 11C.
  • the deshuffled chrominance signal is applied to a field delay stage which includes 3 field memories.
  • a chrominance subsample pattern converter (SSPC C) 14C which furnishes, on the basis of these signals, the samples SS20, SS40 and SS80 required by the chrominance interpo ⁇ lators 36C for 20 ms mode blocks, 37C for 40 ms mode blocks and 38C for 80 ms mode blocks, respectively.
  • the V and U components 20V/U, 40V/U and 80V/U output by these interpolator stages 36C, 37C, 38C are multiplexed by selectors 42V and 42U which are controlled by a branch decision signal BD.
  • the U and V components are trans ⁇ mitted line alternatingly, branch decision signal BD is delayed by 64 ⁇ s in delay stage 43V before it is applied to the V compo ⁇ nent selector 42V.
  • the multiplexed V and ⁇ signals are processed by saturation improvement stages 44V and 44U which supply the V and U output signals V-out and ⁇ -out, respectively.
  • the, decoder of the present invention contains only three field memories in the luminance part. This was brought about by the realization that samples required at the input of the 80 ms mode interpolator 38 which were previous ⁇ ly derived from the outputs of additional field memories could be obtained from the output of the 40 ms mode interpolator. This requires control .of selector switch 30 to connect the output of 40 ms mode interpolator to the input of 80 ms mode interpolator 38 during the relevant time instants in the 20/80 ms mode intervals, as well as in the 40 ms mode intervals as was the case in the known decoder of EP-A 0,330,279 discussed above. Some adjustment of the 40 ms interpolation mode is also required.
  • circuits illustrated in Figs. 2A, 2B, 2C and 2D all consist of three field memories, 202, 204 and 206, connected in cascade.
  • SSPC 208 subsample pattern converter 14 (Fig. la) , hereinafter referred to as SSPC 208, and to corresponding inputs of 80 ms mode interpolator 38 as will be discussed below.
  • the output of SSPC 208 is connected to the input of 40A interpolator 210 (representing interpolator stages 16 and 20 of Fig. la) whose output(s) is/are connected to the remaining input(s) of interpo ⁇ lator 38.
  • Fig. 2A The case illustrated in Fig. 2A is a time instant in which the current input field at terminal 200 is the third field F3 in an 80 ms mode sequence.
  • the values available after the first and second field delays, 202 and 204, respectively, are the values from the second (F2) and first (Fl) 80"ms mode fields in the sequence. It is assumed that the field preceding the first field in the sequence was a 20 ms mode or a 40 ms mode field, indica ⁇ ted by 80.
  • Fig. lc, B' it will be noted that values from 80 ms mode field 4 are needed for the 80 ms mode interpolator. In Fig. 2A these are supplied by interpolator 210. Specifically, as also indicated in Fig.
  • samples f6 and e5 will be applied to the second and third input respectively.
  • 40 ms mode SSPC 208 and interpolator 210 will interpolate sample f8 from samples e7, f6 and e5.
  • the present field has a sample pattern (80) other than the 80 ms mode pattern, while the out ⁇ puts of field delays 202, 204 and 206 have samples from the fourth (F4) , third (F3) and second (F2) fields of the 80 ms mode sequence.
  • F4 fourth
  • F3 third
  • F2 second
  • the outputs of field delays 204 and 206 are, respectively, the fourth (F4) and third (F3) fields in an 80 ms mode sequence.
  • the sample at input 200 is a sample from the second field, 20-F2, of a 20 ms mode sequence, the sample at the output of field delay 202 therefore being from the first field, 20-F1, of that sequence.
  • the samples at input 200 and the output of field memory 202 are 40 ms mode samples from 40 ms mode fields 40-F2 and 40-F1, respectively.
  • samples f6 and e5 are not available in the incoming 80 ms mode patterns.
  • the relevant samples are available in the 20 ms mode fields. See Fig. lc. HoVever, the 20 ms mode branch is a high motion branch, while the 80 ms mode branch is associated with little or no movement. It is therefore preferable to sub ⁇ ject the available 20 ms mode samples to processing in the 40 ms mode SSPC 208 and interpolator 210. This ' creates low pass filte ⁇ red values more suitable for use in the 80 ms mode interpolator. On the other hand, in the time instant shown in Fig. 2D, 40 ms mode samples from fields 1 and 2 are available.
  • Fig 3. is a more detailed block diagram of one embodiment of the A branch 16,20 of the motion compensated 40 ms mode interpolator of Fig. la. It consists of a median interpolator (MI) 300 with associated line memories (L) 302a and 302b. Even samples (E) at the output of filter 300 are applied to a verti ⁇ cal contour correction circuit (VCC) f 303 with associated line memories 304a and 304b, while the odd samples (0) are applied to a VCC 305 with associated line memories 306a and 306b.
  • the coefficients of VCCs 303,305 are (-1 10 -1).
  • the outputs of VCCs 303 and 305 are applied to respective line memory banks 308a-i and 310a-i.
  • Switches 307 and 309 select the proper output sam ⁇ ples from the line memory banks to the inputs of, respectively, vertical interpolators 311 and 313 under control of a vertical motion vector component.
  • Selector switches 307,309 further include horizontal delay lines (HDEL) to perform the horizontal part of the motion compensated interpolation in known manner.
  • HDEL horizontal delay lines
  • the vertical motion vector component signifies from how many lines above or below the line presently being interpolated the interpolating pixels must be derived.
  • the line to which it points is a line for which the pixel value must be interpolated (here called an even line) .
  • Switch matrix 307 therefore connects four relevant line delay outputs corresponding to a pixel in each of four available lines surrounding the missing line, to vertical interpolator 311 for multiplication by respective constants (-1, 9 , 9, -1) .
  • the motion vector is an odd number, i.e. points to a line which is present, the connection is to multiplication factors (0, 16, 0) (not shown) of vertical interpolator 311, which means that the selected pixel value passes.
  • interpolator 311 furnishes the processed even samples E. Operation causing interpolator 313 to furnish the odd samples O is identical and will therefore not be descri ⁇ bed.
  • the number of line memories for branch A of the motion compensated interpolator is thus 24, so that the total number of line memories for the complete motion compensated interpolator (branches A and C) is 48. Further it should be remarked that in parallel to this motion compensated interpolator a compensation delay is required for the 80/20 ms mode blocks which requires 14 line memories.
  • vertical interpolators 311,3113 with coefficients (-1 9 9 -1) or (0 16 0) is replaced by respective vertical filters 410,412, having coefficients (-1 5 -1) or (-1 10 -1) .
  • the vertical contour correction is combined with the interpolation filter, which results in coefficients (-1 5 5 -1) shown in Fig. 4.
  • the relevant coefficients (-1 10 -1) are not shown in Fig. 4.
  • the saving in terms of line memories is four for the one branch illustrated in Fig. 4 and therefore eight for the entire 40 ms. mode interpolator.
  • the compensation delay for the 80/20 ms mode coded blocks requires 2 line memories less so that the total saving becomes ten line memories.
  • the difference in vertical frequency response between (-1 10 -1) * (-1 9 -1) and (-1 5 5 -1) is illustrated in Fig. 5.
  • the order of median interpolator 300 and line memories 308a-i,310a-i is exchanged, as illustrated in Fig. 6.
  • the median interpolator which may include a horizon- tal correction filter as described, e.g., in EP-A 0,344,854 (PHN 12,583), has to be duplicated 10 times as shown in stage 604, (so 9 extra) but the saving in terms of line memories, (602a-602k, vs. 308a-i and 310a-i, Fig.4) is 9 for one branch. Because the silicon area covered by one median interpolator is smaller than that for one line memory, this trade-off of line memories for median interpolators leads to a saving in the total silicon area. Also, switch matrix 606 repla ⁇ ces switch matrix 307 and switch matrix 309.
  • switch matrix 606 depends on the motion vector value of the 40 ms mode block to be processed, as illu ⁇ strated in Table 2 below in which a,c,e,.... refer to adjacent odd field lines, i.e. outputs of line delays 602a.... . Fig.6. It should be remarked that the selectors in branch A and branch C are in a 'mirror' positioff felative to each other.
  • Each median interpolator uses three input lines, e.g. interpolator M9 uses input lines a,c,e, interpolator M8 uses lines c,e,g, etc. If the vertical vector component is +6, i.e.
  • interpolator 704 and switch 706 cor ⁇ respond to interpolator 604 and switch 606 in Fig. 6.
  • the linear interpolators in both branches perform a three point interpolation.
  • the algorithm is illustrated below for L8 in branch A.
  • the interpolator calculates samples at vertical position f from information e and g as follows: input samples on line e : el x e3 x e5 x e7 output samples on line f: input samples on line g : x g2 x g4 x g6 x
  • the block diagram of the so-modified interpolator can be found in Fig. 8.
  • the number of line memories for branch A is 7, i.e. 14 for the entire motion compensated interpolator.
  • the number of line memories for the 80/20 ms -mode compensation delay is 8 in this case.
  • the visual output of the above-described embodiment can be further improved, particularly for picture parts having high horizontal frequency content, by substituting a "half" median algorithm M*l/M'8 for the linear interpolation L1/L8 at the high motion vector values.
  • This algorithm for vertical vector values ⁇ 6 is almost identical to the horizontally corrected median interpolation as applied to the other vertical vector values. The only difference is that the input pixels for the interpola ⁇ tion come from two lines instead of three. This is illustrated below.
  • this function has been mapped on 4 identical IC's containing 4 line memories each. Besides these line delays additional functions like interpolation, adjustable horizontal delay and multiplica ⁇ tion are required for the motion compensated interpolator func ⁇ tion. By making the control of these additional functions flexi- ble, the IC becomes also applicable for the remaining interpola ⁇ tion and (compensation) delay functions as required in the rest of the interpolation part of the decoder.
  • the internal structure of this general purpose processing IC which will be referred to as a Two Dimensional Filter Structure (TDFS) , will be described first. Further details on the applicability of this TDFS circuit in the rest of the decoder will be given later on.
  • TDFS Two Dimensional Filter Structure
  • the TDFS circuit shown in Fig. 9 has 3 data inputs IN1-IN3 and 3 data outputs 0UT1-0UT3 each 8 bit wide at a rate of 27 MHz which is also the internal clock frequency. For cascading purpo ⁇ ses two carry inputs and two carry outputs (not shown) are added. At the input side one can see 4 line memories LM1-LM4 which are organized as 720 pixels * 8 bit. With the aid of the multiplexers MUX1 and MUX2 between the line memories LM2-LM3 and LM3-LM4, respectively, it is possible to configure the line memories either as one chain of 4 line memories in series with input INI, or as 2 line memory chains in parallel.
  • paral ⁇ lel chains can be of equal length, both chains including 2 line memories, one chain (LM1-LM2) coupled to input INI, the other chain (LM3-LM4) coupled to input IN2.
  • one chain can incorporate three line memories (LM1-LM3) coupled to input INI whereas the other chain has only one 'line memory LM4 coupled to input IN3.
  • Behind the line memories 5 data paths (SEL1, INT1, HDEL1; SEL2, INT2, HDEL2; SEL3, INT3, HDEL3; SEL4, INT4, HDEL4; SEL5, COMP DEL) can be distinguished of which the first four can perform an interpolation.
  • the fifth branch is a by-pass path having the same delay (provided by compensating delay block COMP DEL) as the nominal delay of the other branches.
  • the selector blocks SEL1-SEL4 at the input side of the data paths 1-4, the three interpolator inputs of each interpolator INT1- INT4 can be connected to any one of the three data inputs IN1- IN3 or one of the outputs of the four line memories LM1-LM4.
  • the interpolators INT1-INT4 in branches 1 to 4 can be set into different interpolation modes as required for the interpolation of differently subsampled signals. Both linear and non-linear interpolations are possible.
  • Preferred non-linear interpolation modes include the straightforward median interpolation known from EP-A 0,192,292 (PHN 11,613), and the median interpolation which is supplemented by a horizontal filtering as known from EP-A 0,344,854 (PHN 12,583).
  • the interpolators can also be set to perform minimum and maximum functions; this does not call for any additional hardware as in order to determine the median of three input values, minimum and maximum determining logic should be provided anyway, see EP-A 0,192,292. All interpolators INT1-INT4 have two outputs to support the 54 Mbyte/s data rate 21
  • Each interpolator INT1-INT4 can also be set into a transparent mode in which case data at both interpolator outputs are copies of the data at the first two interpolator inputs.
  • the three interpolator inputs can be connected to either one of the three data inputs or one of the four line memory outputs.
  • the adjustable horizontal delays HDEL1-HDEL4 at the outputs of the interpolators INT1-INT4 have a range from 1 to 7 clock periods and are primarily intended for the horizontal displace ⁇ ment required for the motion po pensated interpolator.
  • Each interpolator output can be multiplied by a coefficient ranging from -1 up to +10 in a multiplier block MUL.
  • the coeffi ⁇ cient is identical for both interpolator outputs.
  • the data from the by-pass path may be multiplied by N*4 in which N may range from 0 to A. However, the maximum value of N depends on the multiplier coefficients in the four interpolator paths and may increase by one for each interpolator coefficient smaller than 3.
  • the outputs of the multipliers (12bits) are added, scaled and limited to 8 or 9 bits before supplying to two cross switches. These cross switches facilitate an exchange of both data streams on output 1&2 of the IC.
  • the signal at output 3 is an un-processed but delayed version of one of the input signals.
  • the TDFS circuit as described above can be applied at various places in the decoder, provided that it can be set into the correct mode. To achieve this, the multiplexers, delays, interpolators and multiplier coefficients of the TDFS circuit can be controlled independently of each other by a control block CONT.
  • Control bits required to satisfy this requirement are not supplied in parallel to the TDFS circuit because this would cost a large number of control pins.
  • Most of the internal control bits are static and need only be refreshed during the vertical blanking interval. Only horizontal delays and multiplier coeffi ⁇ cients need to be switched dynamically at block borders, at a rate of 27/8 Mhz. However, these need not to be switched inde ⁇ pendently of each other.
  • the horizontal delays HDEL1-HDEL4 are controlled in two banks viz. one for the delay of odd samples and one for the delay of the even samples, or, formulated otherwise, one for each inter ⁇ polator output.
  • the horizontal delay ranges from 1 to 7 pixels, and depends on the value of the horizontal vector.
  • the number of possible multiplier coefficient combinations is restricted to about 10 per TDFS IC.
  • These internally required multiplier control signals are derived from an internal look-up table as well. Also in this case only 4 bits (to select 1 out of 10 coefficient combinations) need to be supplied to the TDFS.
  • Both look-up tables can be loaded externally so each TDFS has its specific translation table.
  • the multipliers in the by-pass path and in the interpolator paths can also be disabled on pixel time basis by some internal counters.
  • the input control signal at serial control data input SCD-IN should be in phase with the incoming data.
  • This control signal is delayed in the control block CONT and looped through to the serial control data output SCD-OUT with the same delay as the video data.
  • the static control bits are supplied to the TDFS circuit during the vertical blanking interval. During that interval all flip-flops and LUTS to be loaded are configured as a one bit wide shift register under control of an externally supplied ConFiguration Enable command (CFE) .
  • CFE ConFiguration Enable command
  • the input for this configuration information is the same as the input for dynamic control (SCDin) .
  • the output of this configuration chain is then connected to the SCD-output SCD-OUT.
  • a horizontal reference signal indicating the position of the active samples is supplied to input HREF-IN of the TDFS circuit. This signal too is looped through the control block CONT in such a way that, the horizontal reference signal at output HREF-OUT is in phase with the output video data.
  • the block diagram of the decoder is given in Fig. 10a and 10b for the data and control interfaces, respectively. It can be seen that the part of the decoder follo ⁇ wing the outputs of the subsample pattern converter (SSPC Y) 1014 is completely built up with TDFS circuits. Rear- rangement of the input part of the decoder allows upconversion of standard input signals (MAC/PAL/SECAM) to be performed with the same hardware.
  • MAC/PAL/SECAM subsample pattern converter
  • FIG. 10a shows that the input luminance signal Y-in is applied to a temporal filter 1008 which includes a first field memory FM1.
  • the memory output signal and the input signal are applied on lines II and III to a double deshuffling circuit (DESHUF Y) 1010.
  • the first field memory FM1 operates on a 64 ⁇ s line time basis.
  • By means of the double deshuffling circuit 1010 both the input and the output of the first field memory FM1 are converted to a 32 ⁇ s line time basis.
  • the double deshuffle circuit 1010 has four outputs. Output line IV supplies the information from input line III, while information from input line II is supplied at the remaining three outputs. For HD-MAC decoding up to four consecutive fields are required for interpo ⁇ lation.
  • field memories FM2,FM3 are controlled such that after each write cycle they output the information received on line III during two successive field periods.
  • subsample pattern converter (SSPC Y) 1014 via 4 data lines of 4 bits each at 27 Mhz. Nibbles are multiplexed in time, with the least significant nibbles first.
  • the incoming subsample patterns are converted to two 40 ms mode subsample patterns (A & C) lying 40 ms apart in time. These two signals, having a data rate of 27 Mbyte/s, are supplied via 8 bit wide busses to two separate branches of the 40 ms mode motion compensated interpolator. Further the SSPC circuit 1014 passes the four incoming data streams via some compensation line delay to the 80 and 20 ms mode interpolators as will be descri ⁇ bed below.
  • SSPC circuit 1014 The outputs of SSPC circuit 1014 are coupled to TDFS cir ⁇ cuits b-i for interpolation and further processing of the lumi ⁇ nance 20/40/80 ms mode signals.
  • Figs. 11-13 to be described now show these TDFS circuits in more detail.
  • each branch of the 40 ms mode motion compensated interpolator is realized by cascading two TDFS circuits, viz. TDFS b,d for branch C and TDFS c,e for branch A.
  • FIG. 11 shows four TDFS circuits of the type described with reference to Fig. 9.
  • Fig. 11 shows four TDFS circuits of the type described with reference to Fig. 9.
  • Fig. 11 shows four TDFS circuits of the type described with reference to Fig. 9.
  • sho ⁇ wing TDFS circuits only- one output line represents the two interpolators outputs.
  • the multiplier block MUL of Fig. 9 is represented by separate multipliers at the outputs of the interpolator branches INT1-INT4 and the compensating delay branch COMP DEL of Fig. 9.
  • the AD+SCAL block of Fig. 9 is symbolized by an adder followed by a multiplier with coefficient 1/8.
  • Both TDFS circuit pairs c,e and b,d are cascaded by connec ⁇ ting outputs OUT1 and OUT2 (with intermediate results) of the first TDFS circuits b,c respectively to inputs IN2 and IN3 of the second TDFS circuits d,e which lead these through their bypass branches with compensating delay COMP DEL through multip ⁇ liers c- jp with coefficient 8 to the final adder in the respective second TDFS circuits d,e.
  • the line memories LM1-LM3 of the first TDFS circuits b,c are connected via outputs OUT3 to inputs INI of TDFS circuits d,e and their line memories I_M4b-LM7.
  • TDFS combinations c,e and b,d function as two circuits in parallel, giving a chain total of 7 line memories (as line memory LM4a in TDFS b,c overlaps line memory LM4b in TDFS d,e) or 8 possible vertical taps as required by the motion compensa- ted interpolator branch shown in Fig. 8.
  • a non-linear interpolator M2-M7 provides in parallel an interpola ⁇ ted pixel and a copy of the central input. Nominal vertical displacement is 4 taps, giving a 4 line processing delay of the motion compensated interpolator.
  • a pixel is selected conform the vertical vector component with the proper vertical contour correction (-1 10 -1) or combined vertical contour correction and vertical interpolation (-1 5 -l) by switching the multiplier coefficients cl-c ⁇ as follows, in which a dot (.) represents a zero coefficients branch vertical vector value branch
  • Horizontal displacement is accomplished by means of the 1 to 7 pixel delay chains (HDEL1-HDEL4 in Fig. 9) which, in accor ⁇ dance with the horizontal vector component, are changed from their nominal setting (a 4 pixel delay) as follows: a further cross switch takes care that the odd samples remain at outl.
  • X-sw "0" means no change
  • X-sw "1” means a cross- switching of 0UT1 and 0UT2.
  • TDFS c,e and TDFS b,d apply the same operation for 40 ms mode blocks except that they interpret the vectors with opposite signs.
  • the coefficients are set for a simple vertical (4) interpolation.
  • the multiplier c ⁇ in the bypass branch of TDFS b,c is set to 0, which results in a copy of the 40 ms mode odd field samples, although with half their luminance value due to the scaling by 8; for even pixels the vertically interpolated (even field) 40 ms mode samples are output.
  • TDFS cascades c,e and b,d do not distinguish between modes, but each TDFS cascade functions differently: TDFS c,e perform the non-linear interpolation with linear vertical contour-correction (-1 10 -1) required for a -1 motion vector; TDFS b,d do a vertical interpolation (-1 5 -1) as required for a 0 motion vector. Again both 40 ms mode odd and even field pixels are available for use later on by the 80-SSPC in TDFS f,g.
  • Both TDFS cascades output the 54 Mhz interpolated data via 2 outputs of 27 Mhz each: outputs 0UT1 of TDFS d,e supply the odd samples (40-A od / 40-C od) and outputs OUT2 of TDFS d,e supply the even samples (40-A ev / 40-C ev) .
  • TDFS f,g shown in Fig. 12 are used to perform a DATV con ⁇ trolled multiplexing and addition of 80 and 20 ms blocks having subsampling patterns SSPC-I od and SSPC-II ev coming from SSPC circuit 1014 of Fig. 10 and the 40 ms blocks from both branches 40-A,40-C of the motion compensated interpolator.
  • Each TDFS handles one of the 27 Mhz video data streams:
  • TDFS g handles the odd samples and TDFS f the even samples.
  • the incoming 80 and 20 ms mode blocks are delayed by 4 line periods by leading them through the 4 line memory chain LM1-LM4, to compensate for the processing delay of the motion compensated interpolator, before leading them through the bypass branch.
  • TDFS f,g also serve to average both 40 ms mode signals from motion compensated interpolator branches' A and C. Additionally to this averaging function a compensation for intensity errors is performed in TDFS f,g.
  • the 40 ms motion compensated interpo ⁇ lator output amplitude is too small (especially when high spati ⁇ al frequencies occur) if the vector controlled displacement is not completely correct. Be ⁇ ause motion compensation is only performed during even fields, this error gives rise to a 25 Hz flicker effect in highly detailed 40 ms mode areas. The larger the difference between the outputs of the motion compensator branches, the more the flicker can be perceived.
  • the DATV controlled multiplexing between 20/40/80 ms mode blocks is achieved by appropriate switching of the multiplier coefficients cl, c2 and c5 of these max and min 40 ms branches and the 80 ms bypass branch, respectively.
  • the multiplier coefficients cl, c2 and c5 of these max and min 40 ms branches and the 80 ms bypass branch respectively.
  • EP-A 0,322,956 to perform a complete 80 ms mode interpolation, in principle information from four consecutive 80 ms mode blocks is required. As the decoder according to the present invention has only 3 field memories, this information may be not available in case of certain temporal mode transitions.
  • TDFS f,g also perform the conversion to a full 80 ms mode subsample pattern of 80 ms mode blocks, by insertion of missing samples from the 40 ms mode interpolation path as set out in the following table. These cases are illustrated in Fig. 2.
  • Multipliers c3,c4 of two bran ⁇ ches are switched on a pixel-by-pixel basis to select the 40 interpolator output with their interpolators INT3 and INT4 set into transparent mode (symbolically indicated by vertical arrows in Fig. 12).
  • the video data stream prepared in TDFS b..e con- tains all 40 ms mode odd and even field samples needed to com ⁇ plete the 80 ms mode subsample pattern: when odd fields are processed, TDFS c,e output the 40 ms mode odd field and TDFS b,d output the vertically interpolated 40 ms mode even field.
  • TDFS c,e output 1 contains 40 ms mode odd field samples (with half intensity) while output 2 furnishes vertically interpolated even field samples intensity is correc ⁇ ted by setting c3 and c4 to 8.
  • n ⁇ O indicates a non- ⁇ O ms mode block
  • ⁇ O indicates a ⁇ O ms mode block
  • n20 indicates a non-20 ms mode block
  • 20 indicates a 20 ms mode block.
  • Both TDFS f and TDFS g output a 27 Mhz stream of multi- plexed 80/40/20 ms mode odd (od) or even (ev) samples, respecti ⁇ vely.
  • the data streams from TDFS f,g are supplied to TDFS h (shown in Fig. 13) , in which the line memories LM1-LM4 are configured into two chains of two line memories in parallel. This splits in fact TDFS h up into two equivalent parts, one handling the odd samples and one the even samples.
  • the median interpolators Y80, Y20-1 and Y20-1 With the aid of the median interpolators Y80, Y20-1 and Y20-1, the incoming 80 and 20 ms mode blocks are spatially interpolated in parallel whereas the already interpolated 40 ms mode information is fed via the by-pass branch with compensating delay COMP DEL.
  • the fourth interpolator INT4 is not used and its multiplier coeffi ⁇ cient c4 is 0. As also shown in Fig.
  • two 20 ms mode interpo ⁇ lator cells Y20-1 and Y20-1 are used for the 20 ms mode blocks, since also a horizontal (1 1) interpolation is to be done. This is achieved by using 2 different 20-mo.de interpolations: both give the same 20 ms mode interpolated results but the second (Y20-2) is 1 clock period shifted (by HDEL2 shown in Fig. 9) compared to the first (Y20-1) . Averaging both outputs by means of multiplier coefficients (4) results, in the desired horizontal interpolation.
  • the multipliers cl-c ⁇ _ are controlled as indicated in Fig. 13 using the top, middle and lower multiple value sets for the 80, 40, 20 modes respectively, controlled by the DATV data. Outputs OUT1 and OUT2 supply odd and even 27 Mhz signals.
  • the HD-MAC encoder performs a vertical low pass filtering which has to be undone by the HD-MAC decoder. Therefore, as a last step in the luminance channel, an inverse vertical compatibility improvement filtering is perfor- med by TDFS i shown in Fig. 13.
  • TDFS i is configured as two 3 tap linear vertical filters in parallel in order to cope with the 54 Mbyte/s data stream out of TDFS h.
  • the interpolators INT1-INT4 in TDFS i are switched to transparent, i.e.
  • both outputs of each interpolator INT1-INT4 supplies copies of input samples applied to both inputs (symbolized by vertical arrows) and the transfer of the vertical filter formed by TDFS i is determined by the multiplier coefficients cl-c5.
  • the filter may be switched between 6 dB enhancement (-2 12 -2) or 3 Db enhancement (-1 10 -1) .
  • the values of the multiplier coeffi ⁇ cients cl-c5 shown in Fig. 13 correspond to the 6 Db enhance ⁇ ment.
  • the input chrominance signal C-in is applied to a compensation delay block lOO ⁇ C, which compensates for any processing delay difference between luminance and chrominance processing.
  • the delayed chro ⁇ minance signal is deshuffled to the 32 ⁇ s line time domain by deshuffler chrominance (DESHUF C) lOlOC.
  • the deshuffler output signals are supplied to field memories FM4-FM6 which are confi- gured in parallel. The relevant timing diagram on field basis is shown below.
  • field memories FM4-FM6 are controlled such that after each write cycle they output the information received during three successive field periods.
  • This write and read control of field memories FM4-FM6 allows a parallel arrangement to operate like a series arrange ⁇ ment, while maintaining the advantage that a parallel arrange ⁇ ment can cope with a higher data rate. From field period 60, the four sucessive fields required for HD-MAC decoding are available at the same time during each field period.
  • SSPC C chrominance subsample pattern converter
  • chrominance SSPC circuit 1014C also performs a delay of 64 ⁇ s in the U. signal. By doing this the block borders for U and V are in phase in the cascaded interpolation part formed by TDFS circuits j—1.;
  • the data format at the SSPC and interpolation input on line time basis is as follows:
  • the SSPC circuit 1014C delivers 360 samples per chrominance compo- nent (U and V) per 32 ⁇ s.
  • this signal is upconverted horizontally to 720 samples per component per line.
  • 40 ms mode coded blocks only one out of two lines contains 360 valid samples per component. Both horizontal and vertical interpolations should be done on this data stream.
  • the valid informa ⁇ tion is also transferred every other line but only 180 samples per component per line are relevant.
  • a horizontal upconversion by a factor 4 and vertically by a factor 2 are carried out on this data stream.
  • Figs. 14-16 to be described below show the TDFS circuits j-1 in more detail.
  • the outputs of TDFS j are coupled to a saturation improvement circuit 1044C which supplies the output U and V components U-out and V-out.
  • the output signal of the chrominance SSPC circuit 1014C is fed to TDFS j which performs the horizontal interpolation as illustrated in Fig. 14.
  • the four line memories LM1-LM4 are used to supply the necessary vertical aperture.
  • the first interpola ⁇ tor TJV20 performs the 20 ms mode median interpolation over 5 vertical taps; the second interpolator UV80-1 performs the normal 60 ms mode median interpolation over 3 taps; the third interpolator UV40 is set to do the 40 ms mode linear interpola ⁇ tion on the central tap. Multiplexing between modes is done by means of DATV controlled switching of the multiplier coeffi ⁇ cients cl-c4.
  • the fourth interpolator UV80-2 operates in accordance with an 80 ms exception interpola ⁇ tion mode (which simply takes a vertical copy of the border pixels instead of the median) and is used instead of the normal 80 ms mode interpolation UV80-1 by switching the multiplier coefficients cl-c4 properly.
  • a schematic representation of this modified border interpolation is givpn ⁇ in Fig. 15.
  • the samples indicated by 'x' are incoming samples.
  • the samples m are derived by the spatial median interpolation known from EP-A 0,344,654 (PHN 12,563).
  • the samples indicated by 'o' are border samples which are copied from spatially adjacent samples.
  • the different vertical interpolations are performed by DATV controlled switching of the multiplier coeffi ⁇ cients cl-c4 in TDFS k,l with all interpolators INT1-INT4 set to transparent (indicated by vertical arrows) .
  • the vertical interpolation is modified under DATV control.
  • the compensating delay branches COMP DEL are not used; their multiplier coefficients c5 are 0.
  • a receiver containing the hardware for decoding HD-MAC signals can also receive standard MAC, PAL or SECAM signals.
  • the display of the HD-MAC receiver has an aspect ratio of 16:9 whereas the scanning is at 32 kHz because HD-MAC has
  • the first step in the conversion process is the horizontal conversion from 64 ⁇ s lines with 52 ⁇ s of active video to 32 ⁇ s line time with its video information compressed into 19.5 ⁇ s.
  • the video information should be eompressed by a factor 2 * (16/9)/(4/3) - 8/3.
  • This compression is performed in the luminance deshuffling circuit 1010 of Fig. 10 which implies an extra operation mode for this circuit. With respect to data rates, this implies an effective data rate of 8/3 * 13.5 - 36 Mbyte/s at the output of the deshuffler 1010. Because the system clock frequency of the decoder is 27 Mhz, two outputs should be used simultaneously thus together capable of transferring 54 Mbyte/s.
  • the effective data rate is only 36 Mbyte/s which means that only 2/3th of the samples contain valid data.
  • the data stream out of the deshuffler 1010 contains 2 duplicated samples per group of 6.
  • the output format of the luminance deshuffling circuit 1010 in which the symbols refer to 36 Mhz samples, is as follows: ,
  • output 1 signifies the lines directly connected to SSPC 1014
  • output 2 signifies data lines connected to the inputs of the field memories.
  • the information of two successive fields is available at inputs II and III of the deshuffling circuit (Fig. 10) . Both fields are supplied to the rest of the decoder in a line sequen ⁇ tial way (after compression) as indicated (on line time basis) below: 36
  • the delay of the field memories FM2,FM3 is set to the simplest minimum value, e.g. one line.
  • the SSPC circuit 1014 does not perform any interpolation but compensates for the delay of the field memories by delaying the signals at input IV and V by one line as well.
  • the interpolation part of the decoder receives this 36 Mbyte/s data stream and converts it to a sample rate of 54 Mhz by interpolating the missing samples. This inter ⁇ polation process is illustrated schematically below:
  • the impulse response of the interpolating filter on lO ⁇ Mhz basis is:
  • H(t) (-1 -2 0 6 13 16 13 6 0 -2 -1) .
  • the corresponding norma- lized frequency response is given in Fig. 17.
  • the arithmetic operation to be performed in the interpolation part is: sample 1: 16*a sample 2: -l*z + 6*a + 13*b -2*c sample 3: -2*a + 13*b + 6*c -l*d sample 4: 16*c sample 5: -l*b + 6*c + 13*d -2*e sample 6: -2*c + 13*d + 6*e -l*f After three periods of 27 Mhz this process repeats. In order to have unity gain, all coefficients should be divided by 16.
  • an output sample is calculated from maximally four input samples.
  • This purely hori- zontal operation is performed by the TDFS circuits b to g confi ⁇ gured as shown in Figs. 16, 19.
  • the input selectors all select the same vertical tap viz. directly to input; therefore, the line memories LM1-LM4 are unconnected.
  • the interpolator INT1- INT4 are switched to transparent and the adjustable (horizontal) delays in the TDFS branches are set to appropriate values to select the pixels needed for the interpolation. Because two TDFS circuits are cascaded (c,e and b,d in Fig. 18) up to 10 adjacent samples may by combined to one output sample and this is suffi ⁇ cient to cope with the impulse response and the irregular input sequence as indicated above.
  • both cascades operate in parallel and are combined in TDFS f and g with a gain factor of 1 (i.e. multiplier coefficient c5 of TDFS f,g is 8 for branch A, and a gain factor of 0.5 (i.e. multiplier coefficient c4 of TDFS f,g is 4) for branch C (Fig. 19) .
  • H(t) (+2 0 -5 0 19 32 19 O -5 0 +2).
  • the corresponding norma ⁇ lized frequency response is shown in Fig. 21.
  • a horizontal sample rate conversior to the 54 Mhz display clock frequency is performed in the luminance deshuf ⁇ fling circuit 1014 and TDFS b to g.
  • the lines from two adjacent fields are combined into one 625/1:l/50Hz signal without motion adaptation.
  • the adaptation to movement is performed by applying line alternately a straightforward three point vertical median interpolation, see EP-rA 0,192,292 (PHN 11.613).
  • This median filter is allocated to TDFS h which is configured as shown in Fig. 20.
  • Two identical sections (each having two line memories LM1,2/LM3,4 and one median filter od/ev) are put in parallel in order to cope with the 54 Mhz data rate.
  • the unused interpolators INT2,INT4 and the unused bypass branch COMP DEL are connected to multipliers c2,c4,c5 with zero coefficients.
  • the last step in the vertical interpolation process is performed by TDFS i which converts the 54 Mhz 625/1:1 signal to the 1250/2:1 display format by linear vertical interpolation.
  • Line memories LM1-LM4 furnish the information of three adjacent lines which is used for this interpolation and the coefficients are (-1 15 2) for odd fields and (2 15 -1) for even fields.
  • two branches are used with coefficients 7 and ⁇ . All interpolators INT1-INT4 are set to transparent and the unused bypass branch COMP DEL is connected to a multiplier c5 with a zero coefficient.
  • the chrominance input signal is in accordance with the CCIR 4:2:2 format.
  • the two chrominance components U and V are sup ⁇ plied in a pixel multiplexed data stream of 13.5 Mbyte/s.
  • the chrominance deshuffling circuit 1010C of Fig. 10 acts primarily as a compression memory but it also separates U and V.
  • the compression factor is ⁇ /3 which results in an output data rate of 36 Mbyte/s.
  • the output format of this deshuffler 1010C is as follows:
  • the s ⁇ unple rate of the U and V signals should be up-converted from 18 Mbyte/s to the display clock frequency of 27 Mbyte/s. This is schematically indicated below:
  • This horizontal interpolation is performed by TDFS j,k shown in Fig. 23. Because only a horizontal interpolation is required, the line memories LM1-LM4 in TDFS j,k are unconnected. All interpolators INT1-INT4 are set to transparent, indicated by vertical arrows. Horizontal delay circuits HDEL1-HDEL4 provide appropriate horizontal delays as required for the horizontal interpolation.
  • the corresponding normalized frequency response is shown in Fig. 22.
  • the interpolation action can be summarized as follows: Samples 1,4,7,... are copied from the input. Samples 2,5,8,... are interpolated in TDFS k. Samples 3,6,9,... are interpolated in TDFS j.
  • the required time compression by a factor two takes place in the chrominance deshuffler 1010C of Fig. 10.
  • the output format of the deshuffler 1010C in this case is as follows:
  • the interpolating filter operates on an imaginary clock frequency of 27 Mhz.
  • the corresponding normalized frequency response is shown in Fig. 24.
  • the calculation of the output samples is as follows:
  • TDFS 1 For the vertical interpolation of chroma in the upconversi ⁇ on mode, only lines from one field are used.
  • TDFS 1 (see Fig. 23) a simple (1) vertical interpolation is performed using 3 branches.
  • the fourth interpolator INT4 and the bypass path COMP DEL are unused; their multipliers c4,c5 have zero coefficients.
  • the (1) vertical interpolation can be effected by appropriate coefficient switching of multipliers cl-c3; the interpolators INT1-INT3 are set to transparent. It should be remarked that the output is not interlaced which asks for different control of the multiplier coefficients cl-c3 during odd (0 4) and even (4 0) fields.
  • U and V are processed in parallel.

Abstract

Décodeur pour télévision HD-MAC comportant une dérivation de décodage à 40 ms (16-27) ainsi qu'une dérivation de décodage à 80 ms (38). En principe, le décodage des blocs de mode 80 ms exige des échantillons provenant de quatre blocs de mode 80 ms reçus en succession. Un décodeur pour télévision HD-MAC peut fonctionner avec seulement trois mémoires de champ (FM1-FM3) si, lors des changements de temps de modes dans lesquels une séquence de blocs de mode 80 ms est suivie ou précédée de blocs de mode non 80 ms, les échantillons manquants exigés par le décodeur à 80 ms (38) s'obtiennent à la sortie du décodeur à 40 ms (16-27) à l'aide d'une commutation appropriée d'un commutateur (30).
EP19910903857 1990-02-09 1991-02-08 Decodeur pour television hd-mac Withdrawn EP0468027A1 (fr)

Applications Claiming Priority (4)

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GB9002991 1990-02-09
GB909002991A GB9002991D0 (en) 1990-02-09 1990-02-09 High definition television decoder
GB909007670A GB9007670D0 (en) 1990-02-09 1990-04-04 High definition television decoder
GB9007670 1990-04-04

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EP0468027A1 true EP0468027A1 (fr) 1992-01-29

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JP (1) JPH05500442A (fr)
AU (1) AU7239691A (fr)
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FR2691600B1 (fr) * 1992-05-19 1994-08-19 Philips Electronique Lab Dispositif de correction de l'effet de scintillement de signaux dits compatibles.
JP3981651B2 (ja) * 1993-03-25 2007-09-26 セイコーエプソン株式会社 画像処理装置
DE69329332T2 (de) * 1993-05-26 2001-02-22 St Microelectronics Srl Fernsehbilderdekodierarchitektur zur Ausführung eines 40 ms-Prozessalgorithmus in HDTV
WO1994028677A1 (fr) * 1993-06-01 1994-12-08 Thomson Multimedia S.A. Methode et dispositif d'interpolation par compensation cinetique

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US4012628A (en) * 1975-08-15 1977-03-15 Bell Telephone Laboratories, Incorporated Filter with a reduced number of shift register taps
US4694416A (en) * 1985-02-25 1987-09-15 General Electric Company VLSI programmable digital signal processor
DE3850952T2 (de) * 1987-12-22 1995-02-23 Philips Nv Videosignalkodierung und -dekodierung mit einem adaptiven Filter.
GB8814822D0 (en) * 1988-06-22 1988-07-27 British Broadcasting Corp Bandwidth reduction system for television
GB2219458A (en) * 1988-06-01 1989-12-06 Philips Electronic Associated Processing sub-sampled signals
FR2633135B1 (fr) * 1988-06-17 1990-11-09 France Etat Armement Decodeur pour recepteur de programmes de television haute definition diffuses sur canal etroit

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