EP0468027A1 - Hd-mac television decoder - Google Patents

Abstract

Decoder for HD-MAC television comprising a 40 ms decoding bypass (16-27) as well as an 80 ms decoding bypass (38). In principle, the decoding of the 80 ms mode blocks requires samples from four 80 ms mode blocks received in succession. A decoder for HD-MAC television can operate with only three field memories (FM1-FM3) if, during time changes of modes in which a sequence of mode blocks 80 ms is followed or preceded by mode blocks not 80 ms , the missing samples required by the 80 ms decoder (38) are obtained at the output of the 40 ms decoder (16-27) using appropriate switching of a switch (30).

Description

HD-MAC television decoder.

The invention relates to a decoder for a high definition television system, in particular the HD-MAC system adopted by the European cooperation program called Eureka.

* European patent application EP-A-0,330,279 (PHF 88507) describes several aspects of this HD-MAC system which includes a bandwidth reduction encoder at the transmission end and a cor¬ responding decoder at the receiving end.

In the Eureka HD-MAC system, the -signal source (camera) 0 provides a 1250 lines, 50 Hz field rate, 2:1 interlaced signal and a 625 lines, 50 Hz, 2:1 signal is transmitted. The transmit¬ ted video signal is accompanied by a digital signal giving t additional information for control,, and timing of the video signal processing system. Such a system may be referred to as 5 digital assisted television (DATV) .

As described with reference to Figs. 9 and 11 of EP-A-0,330,279, in the HD-MAC decoder samples from several received fields are combined to interpolate display fields. While EP-A-0,330,279 does not mention the number of field memo- 0 ries required in its HD-MAC decoder to furnish these samples, the non-prepublished French patent application 89.13.091 filed 06.10.89 (PHF 89,595) describes an HD-MAC decoder which requires not less than six field memories, which results in a rather expensive HD-MAC decoder implementation. 5 The present embodiment of a Eureka HD-MAC decoder also requires complex blocks with an excessive number of interconnec¬ tions. It is thus not suitable for integrated circuit implemen¬ tation.

0

It is an object of the invention to provide a less expensi¬ ve HD-MAC decoder. .

It is another object of the present invention to furnish a decoder for an HD-MAC system in which a minimum number of diffe¬ rent blocks with limited complexity and practical interfaces is used.

It is a further object of the present invention to decrease the number of field memories and line memories without, however, decreasing viewer satisfaction with the resulting image.

It is also an object of the present invention to provide a decoder in which the format of standard received television signals can be changed to attain an increased aspect ratio.

The invention provides thereto a ^' decoder apparatus for decoding input signals divided into a plurality of adjacent blocks encoded in accordance with a selected one of a plurality of coding modes, each coding mode having an associated sampling pattern, which has input means coupled to receive said input signals for furnishing samples from a present field and from a plurality of preceding fields, first decoding means coupled to said input means for processing samples from blocks sampled in accordance with a first sampling pattern, second decoding means requiring samples from a plurality of temporally sequential blocks sampled in accordance with a second sampling pattern, and selector means for selectively coupling said input means or said first decoding means to said second decoding means to furnish said required samples to said second decoding means.

The decoder apparatus also has combined vertical contour correction and interpolation means, in the form of weighting constants accommodating both functions and applied to samples being processed.

Also according to the invention, a multipurpose integrated circuit has a plurality of data inputs, a plurality of data outputs a plurality of processing circuits, a plurality of interconnectable delay members, controllable selector means for connecting said delay members to each other to form selected delays and for connecting said selected delays to said proces¬ sing circuits at least in part in response to selector controls signals, externally loaded look-up table means for furnishing said selector control signals in response to externally applied chip control signals, and output means connected to said proces¬ sing circuits and said data outputs-for furnishing output sam- pies including processed samples in response to data applied at said data inputs.

According to another feature of the invention, a decoder apparatus has input means for receiving input signals, first memory means for receiving said input signals and furnishing once delayed signals at a first memory output, second memory means receiving said once delayed signals only during alternate ones of consecutive predetermined time intervals, third memory means receiving said once delayed signals' only during the remai¬ ning ones of said consecutive time intervals, and output means coupled to said first, second and third memory means, for fur¬ nishing output signals comprising, in parallel once, twice and three times delayed input signals.

These and other (more detailed) aspects of the invention will be described and elucidated by the following description in conjunction with the drawings.

In the drawings:

Fig. la is a schematic diagram of the luminance interpola¬ tion part of an HD-MAC decoder in accordance with the present invention;

Fig. lb is a schematic diagram of the chrominance interpo- lation part of an HD-MAC decoder embodiment;

Fig. lc shows sampling patterns corresponding to the three processing branches of the Eureka HD-MAC system;

Fig. 2A-D schematically show how input samples for the 80 ms mode interpolator are obtained in an HD-MAC decoder according to the invention;

Fig. 3 is a block diagram of a first embodiment of one branch of the 40 ms mode motion compensated interpolator; Fig. 4 is a block diagram of a second embodiment of the 40 ms mode motion compensated interpolator branch having fewer line memories;

Fig. 5 shows the difference between the filter characteris- tics of a filter shown in Fig. 3 and a filter shown in Fig. 4;

Fig. 6 is a block diagram of a third embodiment of the 40 ms mode motion compensated interpolator branch;

Fig. 7 is a block diagram of a fourth embodiment of the 40 ms mode motion compensated interpolator branch; Fig. 8 is a block diagram of a fifth embodiment of the 40 ms mode motion compensated interpolator branch;

Fig. 9 shows the internal block diagram of a flexible filter block according to the invention; ^*

Fig. 10a shows a block diagram of the data interfaces of a decoder according to the invention;

Fig. 10b is a block diagram of the control interfaces;

Fig. 11 shows the section of Fig. 10a concerning the 40 ms mode motion compensated interpolator in more detail;

Fig. 12 shows the section of Fig. 10a concerning the multi- plexing of 40 ms mode interpolator output samples and 20 or 80 ms mode interpolator input samples in more detail;

Fig. 13 shows the section of Fig. 10a concerning the 20 and 80 ms mode interpolation in more detail;

Fig. 14 shows the section of Fig. 10a concerning the hori- zontal chrominance interpolation in more detail;

Fig. 15 schematically shows the interpolation of 80 ms mode chrominance samples;

Fig. 16 shows the section of Fig. 10a concerning the verti¬ cal chrominance interpolation in more detail; Fig. 17 shows the frequency response of a horizontal lumi¬ nance upconversion filter according to the invention for upcon- version of a 4:3 aspect ratio input signal;

Figs. 18, 19 and 20 show the sections of Figs. 11, 12 and 13, respectively, when configured to operate in a luminance upconversion mode;

Figs. 21 shows a frequency response of a horizontal lumi¬ nance upconversion filter according to the invention for upcon- version of a 16:9 aspect ratio input signal;

Figs. 22 shows a frequency response of a horizontal chromi¬ nance upconversion filter according to the invention for upcon¬ version of a 4:3 aspect ratio input signal; Fig. 23 shows the sections of Figs. 14 and 16, respective¬ ly, when configured to operate in a chrominance upconversion mode; and

Fig. 24 shows a frequency response of a horizontal chromi¬ nance upconversion filter according to the invention for upcon- version of a 16:9 aspect ratio input signal.

The overall block diagram of an HD-MAC decoder according to the present invention is shown in Figs, la and lb, for the luminance and chrominance signal components, respectively. The signal received by the decoder was encoded at the transmitting end by bandwidth reduction processing of the scanned image (camera) signal in three processing paths, each having its own associated sampling pattern in accordance with the amount of motion in the picture. A detailed description of such an enco¬ ding system can be found, for example, in European Patent Appli¬ cation EP-A 0,322,965 (PHN 12,440). Briefly, the three separate processing paths are associated, respectively, with temporal refresh rates of 20 ms, 40 ms and 80 ms. The lowest temporal resolution, 80 ms, is accompanied by the highest spatial resolu¬ tion, and vice versa, so that the processed signal has a lower bandwidth than the scanned image (camera) signal and is suitable for recording, for transmission over a limited bandwidth chan¬ nel, and for reception and processing by presently used MAC receivers, as well as the new HDTV receivers.

Specifically, in a stationary or very slow movement mode, the field rate is 12.5 Hz and the basic interval is 80 ms. Whe^* there is more movement, the field rate is 25 Hz and the basic interval is 40 ms, while in the rapid movement mode the field rate is 50 Hz and the basic interval" is 20 ms. These constants are appropriate for the HD-MAC system chosen by Eureka. Other time and spatial intervals may be appropriate for other systems. For convenience, the sampling patterns associated with these basic intervals are illustrated in Fig. lc. It should be noted that the image is divided into image blocks each having 16*16 pixels at the encoder. Part of a block at each of the refresh rates is illustrated. Here x signifies samples to be transmitted, the dots indicate samples not to be transmitted, and 1, 2, 3, 4 are the field numbers in which the particular sample is to be transmitted. It should be noted that for the 80 ms branch, illustrated in Fig. lc as A', B', subsampling takes place in units of 4 sequential fields. Samples to be transmitted in fields 1, 2, 3, or 4 are derived from the corresponding fields in the input sequence.

A 20 ms branch, E¹ and F' of Fig. lc, has the same subsam¬ pling pattern as the first two fields of the 80 ms pattern. This branch represents the highest temporal and lowest spatial reso¬ lution.

The operation of the 40 ms branch, C^» and D' of Fig. lc, is somewhat more complicated. Samples are derived from alternate camera fields only. Samples from the first camera input field, as indicated in D' in Fig. lc, are transmitted during the first and second transmitted fields. At the HDTV decoder the received samples are recombined into one field. The second input field is suppressed by the encoder. The third input field is subsampled as indicated in C and transmitted during the third and fourth transmitted fields (D' but with "1" and "2" changed to "3" and ⁿ4ⁿj _Tne latter two fields are also recombined at the decoder. These two reconstituted fields are then used to interpolate the suppressed second field with motion compensation, in accordance with known techniques. In every branch described above, samples which are not transmitted are interpolated at the receiver.

As mentioned above, this encoding system is known and further details can be derived from published literature as, for example, European Patent Application EP-A 0,322,956. Further, as discussed in EP-A 0,322,956, the sequence of sampling patterns received at the decoder in sequential compati¬ ble fields is limited to the different "routes" described in Table 1 below:

TABLE 1

It should also be noted that line shuffling takes place where required to decrease the transmitted number of lines per field and increase the line length to accommodate the transmis¬ sion standard and to allow processing by a conventional MAC receiver. For example in Fig. lc, pattern B¹, the samples indi¬ cated by "1" from line 3 occupy the positions indicated by "3" on line 1 in the first field after line shuffling. Similarly, for the even fields, the "2" sample of line 4 is transmitted on line 2. It will be noted that line shuffling is not necessary in the 40 ms branch.

The luminance component of above described transmitted or recorded signal, after reception and suitable processing at the receiver head end, is applied to input 1 of the luminance deco¬ der illustrated in Fig. la. The signal is applied to a temporal filter 8, which comprises one field memory FM1. As set out with reference to Figs. 18a to 23 of European patent application EP-A 0,330,279 (PHF 88,507), to improve the display quality of the HD-MAC signal on normal definition MAC receivers, the 40 ms mode blocks output by the HD-MAC encoder are temporally filtered before transmission or recording. The temporal filter 8 applies an inverse temporal filtering which compensates for the temporal filtering applied at the encoder side. As EP-A 0,330,279 descri- bes this inverse filtering in detail, no further description will be given here. However, in accordance with an aspect of the present invention, the field memory FM1 present in the temporal filter 8 is advantageously used as one of the field delays required for the HD-MAC decoding, thus saving one field memory. Therefore, temporal filter 8 outputs both a delayed and an undelayed signal at its outputs.

The signals output by temporal filter 8 undergo line des- huffling in a deshuffler stage 10. The deshuffling operation takes place under control of a DATV signal applied to a control input 11 of the deshuffler stage 10. Since the control inputs do not contribute to the understanding of the present invention, they will be omitted or only sketchily indicated in the figures. The deshuffled signals are applied to a field delay stage 12 which, in the embodiment shown, includes two field delays FM2 and FM3. The particular interconnection of the field memories to accommodate high data rates will be discussed below with refe¬ rence to Fig. 10. There are thus available four signals mutually delayed by one field period.

The four signals derived from the field delay stage 12 are applied to a subsample pattern converter 14. Since the received sampling patterns are each associated with pixel blocks of small size (e.g. 16 x 16), the received signal will have many sampling blocks adjoining blocks of a different sampling pattern. Since the interpolators may need samples within the adjoining blocks for interpolating edge positions on a given block, subsample pattern converter 14 converts the sampling pattern of each incoming block to both the 80 ms and 40 ms sampling patterns. Specifically, a field A with the subsample pattern associated with the recombined first and second transmitted fields (i.e. the first camera field) is furnished on a line ss40A, while a field C with the subsample pattern associated with the recombi¬ ned third and fourth transmitted fields (i.e. the third camera field) is furnished on a line ss40C, to respective 40 ms mode interpolator stages 16 and 18, where they are subjected to non¬ linear interpolation and vertical contour correction. Even (E) and odd (0) samples are furnished at outputs 40A-O, 40A-E and 40C-0, 40C-E of the stages 16 and 18.

Field interpolation with motion compensation takes place utilizing data from both the A and C branches. For this purpose, stages 20 and 22 delay the samples from stages 16 and 18, res¬ pectively, in accordance with the motion vectors (applied to inputs 20a) and branch decision signals (applied to inputs 20b) derived from the digital assisting DATV signal. The outputs from stages 20 and 22 are applied, respectively, to gain selecting stages 24 and 26. During the time that the even field values are available at the output of stages 20 and 22, the gains of stages 24 and 26 are both adjusted to 0.5. During the odd fields, in which no motion compensation is performed, the gain of stage 24 is switched to unity, while that of stage 26 is adjusted to 0. The gain is similarly adjusted, but, on a pixel basis, to imple¬ ment the improvement discussed below with reference to Fig. 2, which permits use of only three field memories. The outputs from the "A" branch and the "C* branch are combined in an adder 27.

The output of adder 27, which contains the reconstructed HDTV luminance signal from a 40 ms mode subsampling pattern, is connected to a first pair of inputs (40) of a selector stage 30.

Selector stage 30 has a second pair of inputs, 40' connec- ted via a delay 32 to the ss80I and ssδOII outputs of subsample pattern converter 14. Either the first or the second input pair is connected to the output pair, (30b, 30c) , of selector 30 under control of a DATV branch decision signal at input 30a. In a similar way as has been described with reference to Fig. 11 of EP-A 0,330,279, selector 30 selects the (40) input when the currently processed block is a 40 ms mode block, to furnish to the 20 and 80 ms mode interpolators the best available samples as supplied by the 40 ms mode interpolator. EP-A 0,330,279 further teaches that in its decoder, selector 30 selects input 40 when the currently processed block is a 20 or 80 ms mode block, because in that case the best available samples for the 20 and 80 ms mode interpolator are supplied by subsample pattern converter 14.

However, as known from EP-A 0,322,956, to perform a co ple- te 80 ms mode interpolation, information from four consecutive 80 ms mode blocks is required. As the decoder according to the present invention has only 3 field memories, this information may be not available in case of certain temporal mode transiti¬ ons in which an 80 ms mode route is followed or preceded by a non-80 ms mode route. In accordance with the principles of the present invention, to enable the decoder to have only three field memories, selector 30 selects its (40) input also whenever a sample required for the 80 ms mode interpolation is not sup¬ plied by the subsample pattern converter 14. Further details about implementation of the above are described below with reference to Fig. 2.

Subsample patterns 80 I and 80 II, as present on lines 34a and 34b, respectively, are applied in parallel to a 20 ms inter¬ polation stage 36 and an 80 ms interpolation stage 38 for inter¬ polation of the remaining missing samples. Fully interpolated fields are then available at the outputs of stages 27, 36 and 38, respectively. The output of adder 27 is applied to a first pair of inputs of a final selector stage 42 via a delay stage 41 which compensates for the delay of stages 30, 36 and 38. The outputs of interpolators 36 and 38 are di- rectly applied to a second and third set of inputs of selector 42. Selector 42 operates under control of DATV signal 42a. The output of stage 42 is a 1250 line, 50 Hz, 2:1 HDTV signal.

It should further be noted that each 80 ms input line in Fig. la symbolizes a pair of lines, four input values being required for the 80 ms interpolator.

Fig. lb is a schematic diagram of the chrominance interpo¬ lation part of an HD-MAC decoder embodiment. The input chromi¬ nance component C-in is applied via a compensating delay stage 8C to chrominance deshuffler (DESHUF C) 10C, which is controlled by a control signal applied to its input 11C. The deshuffled chrominance signal is applied to a field delay stage which includes 3 field memories. Its input signal and three delayed signals are applied to a chrominance subsample pattern converter (SSPC C) 14C which furnishes, on the basis of these signals, the samples SS20, SS40 and SS80 required by the chrominance interpo¬ lators 36C for 20 ms mode blocks, 37C for 40 ms mode blocks and 38C for 80 ms mode blocks, respectively. The V and U components 20V/U, 40V/U and 80V/U output by these interpolator stages 36C, 37C, 38C are multiplexed by selectors 42V and 42U which are controlled by a branch decision signal BD. As in accordance with the MAC transmission standard the U and V components are trans¬ mitted line alternatingly, branch decision signal BD is delayed by 64μs in delay stage 43V before it is applied to the V compo¬ nent selector 42V. Finally, the multiplexed V and ϋ signals are processed by saturation improvement stages 44V and 44U which supply the V and U output signals V-out and ϋ-out, respectively.

As mentioned above, the, decoder of the present invention contains only three field memories in the luminance part. This was brought about by the realization that samples required at the input of the 80 ms mode interpolator 38 which were previous¬ ly derived from the outputs of additional field memories could be obtained from the output of the 40 ms mode interpolator. This requires control .of selector switch 30 to connect the output of 40 ms mode interpolator to the input of 80 ms mode interpolator 38 during the relevant time instants in the 20/80 ms mode intervals, as well as in the 40 ms mode intervals as was the case in the known decoder of EP-A 0,330,279 discussed above. Some adjustment of the 40 ms interpolation mode is also required.

The above-described action is schematically illustrated in Fig. 2 for all relevant temporal instances, i.e. all instances in which an output froa the field memories to be omitted was required for 80 ms mode interpolator 38. It should be noted that the series arrangement of the memories is also a functional representation. A preferred interconnection of the three field memories will be discussed below with reference to Fig. 10.

The circuits illustrated in Figs. 2A, 2B, 2C and 2D all consist of three field memories, 202, 204 and 206, connected in cascade. An input terminal 200 and the outputs of memories 202,

204 and 206 are applied to respective inputs of 40 ms mode part 208 of subsample pattern converter 14 (Fig. la) , hereinafter referred to as SSPC 208, and to corresponding inputs of 80 ms mode interpolator 38 as will be discussed below. The output of SSPC 208 is connected to the input of 40A interpolator 210 (representing interpolator stages 16 and 20 of Fig. la) whose output(s) is/are connected to the remaining input(s) of interpo¬ lator 38.

The case illustrated in Fig. 2A is a time instant in which the current input field at terminal 200 is the third field F3 in an 80 ms mode sequence. The values available after the first and second field delays, 202 and 204, respectively, are the values from the second (F2) and first (Fl) 80"ms mode fields in the sequence. It is assumed that the field preceding the first field in the sequence was a 20 ms mode or a 40 ms mode field, indica¬ ted by 80. Referring to Fig. lc, B', it will be noted that values from 80 ms mode field 4 are needed for the 80 ms mode interpolator. In Fig. 2A these are supplied by interpolator 210. Specifically, as also indicated in Fig. 2A, if sample e7 (Fig. lc) is applied to the first input of interpolator 38, samples f6 and e5 will be applied to the second and third input respectively. 40 ms mode SSPC 208 and interpolator 210 will interpolate sample f8 from samples e7, f6 and e5.

At the time instant of Fig. 2B, the mirror-image of the conditions in Fig. 2A prevails. The present field has a sample pattern (80) other than the 80 ms mode pattern, while the out¬ puts of field delays 202, 204 and 206 have samples from the fourth (F4) , third (F3) and second (F2) fields of the 80 ms mode sequence. Thus at the time that samples f6, e7 and fδ are avai¬ lable at three of the inputs to 80 ms mode interpolator 38, the fourth input sample e5 must be supplied by 40 A interpolator 210.

In both Fig. 2C and Fig. 2D, the outputs of field delays 204 and 206 are, respectively, the fourth (F4) and third (F3) fields in an 80 ms mode sequence. In Fig. 2C the sample at input 200 is a sample from the second field, 20-F2, of a 20 ms mode sequence, the sample at the output of field delay 202 therefore being from the first field, 20-F1, of that sequence. In Fig. 2D the same is true, but the samples at input 200 and the output of field memory 202 are 40 ms mode samples from 40 ms mode fields 40-F2 and 40-F1, respectively. In both cases samples f6 and e5 are not available in the incoming 80 ms mode patterns. In the case of Fig. 2C, the relevant samples are available in the 20 ms mode fields. See Fig. lc. HoVever, the 20 ms mode branch is a high motion branch, while the 80 ms mode branch is associated with little or no movement. It is therefore preferable to sub¬ ject the available 20 ms mode samples to processing in the 40 ms mode SSPC 208 and interpolator 210. This ^'creates low pass filte¬ red values more suitable for use in the 80 ms mode interpolator. On the other hand, in the time instant shown in Fig. 2D, 40 ms mode samples from fields 1 and 2 are available. These are ap¬ plied directly to the 40 ms mode interpolator 210 which passes the e5 sample and calculates the f6 sample. Both of these sam¬ ples are then applied to 80 ms mode interpolator 38. The above clearly indicates that a total of three field memories is adequate for generating the samples needed for the 80 ms mode interpolator in the luminance branch. No correspon¬ ding changes are required for the chrominance branch (Fig. lb) .

Further, according to the present invention, modifications are carried out in the 40 ms mode motion compensated interpola¬ tor. These will now be discussed.

Fig 3. is a more detailed block diagram of one embodiment of the A branch 16,20 of the motion compensated 40 ms mode interpolator of Fig. la. It consists of a median interpolator (MI) 300 with associated line memories (L) 302a and 302b. Even samples (E) at the output of filter 300 are applied to a verti¬ cal contour correction circuit (VCC)^f 303 with associated line memories 304a and 304b, while the odd samples (0) are applied to a VCC 305 with associated line memories 306a and 306b. The coefficients of VCCs 303,305 are (-1 10 -1). The outputs of VCCs 303 and 305 are applied to respective line memory banks 308a-i and 310a-i. Switches 307 and 309 select the proper output sam¬ ples from the line memory banks to the inputs of, respectively, vertical interpolators 311 and 313 under control of a vertical motion vector component. Selector switches 307,309 further include horizontal delay lines (HDEL) to perform the horizontal part of the motion compensated interpolation in known manner.

As is well known, the vertical motion vector component signifies from how many lines above or below the line presently being interpolated the interpolating pixels must be derived. When the motion vector is an even number, the line to which it points is a line for which the pixel value must be interpolated (here called an even line) . Switch matrix 307 therefore connects four relevant line delay outputs corresponding to a pixel in each of four available lines surrounding the missing line, to vertical interpolator 311 for multiplication by respective constants (-1, 9 , 9, -1) . When the motion vector is an odd number, i.e. points to a line which is present, the connection is to multiplication factors (0, 16, 0) (not shown) of vertical interpolator 311, which means that the selected pixel value passes. In this way interpolator 311 furnishes the processed even samples E. Operation causing interpolator 313 to furnish the odd samples O is identical and will therefore not be descri¬ bed.

The number of line memories for branch A of the motion compensated interpolator is thus 24, so that the total number of line memories for the complete motion compensated interpolator (branches A and C) is 48. Further it should be remarked that in parallel to this motion compensated interpolator a compensation delay is required for the 80/20 ms mode blocks which requires 14 line memories.

In the embodiment illustrated in Fig. 4, in which elements corresponding to elements in Fig. 3 have the same reference numerals, the cascaded action of respective vertical contour correctors 303,305 with coefficients (-1 10 -1) and respective 15

vertical interpolators 311,3113 with coefficients (-1 9 9 -1) or (0 16 0) is replaced by respective vertical filters 410,412, having coefficients (-1 5 -1) or (-1 10 -1) . For pixels of even lines, the vertical contour correction is combined with the interpolation filter, which results in coefficients (-1 5 5 -1) shown in Fig. 4. For the pixels of odd lines, only contour correction is carried out; the relevant coefficients (-1 10 -1) are not shown in Fig. 4. The saving in terms of line memories is four for the one branch illustrated in Fig. 4 and therefore eight for the entire 40 ms. mode interpolator. Moreover, the compensation delay for the 80/20 ms mode coded blocks requires 2 line memories less so that the total saving becomes ten line memories. The difference in vertical frequency response between (-1 10 -1) * (-1 9 -1) and (-1 5 5 -1) is illustrated in Fig. 5.

In a further embodiment of this invention, the order of median interpolator 300 and line memories 308a-i,310a-i is exchanged, as illustrated in Fig. 6. To keep the same functional behavior, the median interpolator, which may include a horizon- tal correction filter as described, e.g., in EP-A 0,344,854 (PHN 12,583), has to be duplicated 10 times as shown in stage 604, (so 9 extra) but the saving in terms of line memories, (602a-602k, vs. 308a-i and 310a-i, Fig.4) is 9 for one branch. Because the silicon area covered by one median interpolator is smaller than that for one line memory, this trade-off of line memories for median interpolators leads to a saving in the total silicon area. Also, switch matrix 606 repla¬ ces switch matrix 307 and switch matrix 309.

The function of switch matrix 606 depends on the motion vector value of the 40 ms mode block to be processed, as illu¬ strated in Table 2 below in which a,c,e,.... refer to adjacent odd field lines, i.e. outputs of line delays 602a.... . Fig.6. It should be remarked that the selectors in branch A and branch C are in a 'mirror' positioff felative to each other. Each median interpolator uses three input lines, e.g. interpolator M9 uses input lines a,c,e, interpolator M8 uses lines c,e,g, etc. If the vertical vector component is +6, i.e. even, the outputs of median interpolators M9,M8,M7,M6 are multiplied by coefficients -1,5,5,-1, respectively. If the vertical vector component is +5, i.e. odd, the outputs of median interpolators M8,M7,M6 are multiplied by coefficients -1,10,-1 respectively, etc. Dots (.) indicate median filter outputs not used for the vertical vector value.

Branch Vertical Vector Value Branch

+6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6

TABLE 2

Additional savings of line memories can be achieved by modification of the vertical interpolation algorithm for the case in which the vertical vector equals +6. See Fig. 7. For these high vertical vector values the interpolation coefficients are changed from (-1 5 -1) to (0 4 0) . The hardware consequences of this adaptation are a saving of 4 median filters (MO and M9 in both branches) , 4 line memories (602a and 602k in both branches) and 2 line memories in the 80/20 ms mode compen- sation delay. In view of performance this modification can be justified by the knowledge that motion estimation becomes less accurate with larger displacement. It might thus be very dange- 17

rous to accentuate fine vertical detail when it may be placed in an incorrect position by the motion compensated interpolator. Apart from these changes, interpolator 704 and switch 706 cor¬ respond to interpolator 604 and switch 606 in Fig. 6.

One step further, which again leads to a saving of 4 + 2 (compensation delay) line memories is also to leave out the next border line memories and median interpolators (M1,M8) of the MC interpolator, see Fig. 8. This implies that the vertical inter¬ polation algorithm also changes for vertical vector values +4 from (-1 5 -1) to (0 4 0) and for vertical vector values +5 from (-1 10 -1) to (0 8 0). For vertical vectors +6 the interpolation algorithm is completely changed from non-linear median interpo¬ lation to linear interpolation (linear interpolators L1,L8 in interpolator 804 instead of median interpolators M1,M8 in inter¬ polator 704) because of the smaller vertical aperture of the linear interpolation method. The position of the switch matrix 806 and the value of the associated interpolation coefficients of stages 410,412 are illustrated below.

Branch Vertical Vector Value Branch

+6 +5 +4 +3 +2 +1 O <-l -2 -3 -4 -5 -6

e L8 g M7 4 -1 -1 i M6 4 10 5 -1 -1 . . . k M5 -1 5 10 5 -1 -1 . m M4 . -1 -1 5 10 5 -1

O M3 . . . -1 -1 5 10 4 q M2 -1 -1 4 8

S LI

ΪABLE 3

The linear interpolators in both branches perform a three point interpolation. The algorithm is illustrated below for L8 in branch A. The interpolator calculates samples at vertical position f from information e and g as follows: input samples on line e : el x e3 x e5 x e7 output samples on line f: input samples on line g : x g2 x g4 x g6 x

output f(n) = [e(n-l) + e(n+l)] /2 + g(n)/2 for n = even, output f(n) = [g(n-l) + g(n+l)] /2 + e(n)/2 for n = odd.

The block diagram of the so-modified interpolator can be found in Fig. 8. The number of line memories for branch A is 7, i.e. 14 for the entire motion compensated interpolator. The number of line memories for the 80/20 ms -mode compensation delay is 8 in this case.

The visual output of the above-described embodiment can be further improved, particularly for picture parts having high horizontal frequency content, by substituting a "half" median algorithm M*l/M'8 for the linear interpolation L1/L8 at the high motion vector values. This algorithm for vertical vector values ±6 is almost identical to the horizontally corrected median interpolation as applied to the other vertical vector values. The only difference is that the input pixels for the interpola¬ tion come from two lines instead of three. This is illustrated below.

in A (line g) : x g2 x in B (line e) : el x e3 in C (line g) : x g2 x

For purely horizontal frequency components the output of the 'half median will be the same as for the 'full' median. Once this 'half median output is available, it can also be used for vertical vectors +4 and +5 as indicated in Table 4 below. Branch Vertical Vector Value Branch

+6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6

TABLE 4

IC partitioning of the decoder.

As current IC technology does not allow an implementation of the motion compensated interpolator on a single IC, this function has been mapped on 4 identical IC's containing 4 line memories each. Besides these line delays additional functions like interpolation, adjustable horizontal delay and multiplica¬ tion are required for the motion compensated interpolator func¬ tion. By making the control of these additional functions flexi- ble, the IC becomes also applicable for the remaining interpola¬ tion and (compensation) delay functions as required in the rest of the interpolation part of the decoder. The internal structure of this general purpose processing IC, which will be referred to as a Two Dimensional Filter Structure (TDFS) , will be described first. Further details on the applicability of this TDFS circuit in the rest of the decoder will be given later on.

Description of the TDFS circuit.

The TDFS circuit shown in Fig. 9 has 3 data inputs IN1-IN3 and 3 data outputs 0UT1-0UT3 each 8 bit wide at a rate of 27 MHz which is also the internal clock frequency. For cascading purpo¬ ses two carry inputs and two carry outputs (not shown) are added. At the input side one can see 4 line memories LM1-LM4 which are organized as 720 pixels * 8 bit. With the aid of the multiplexers MUX1 and MUX2 between the line memories LM2-LM3 and LM3-LM4, respectively, it is possible to configure the line memories either as one chain of 4 line memories in series with input INI, or as 2 line memory chains in parallel. These paral¬ lel chains can be of equal length, both chains including 2 line memories, one chain (LM1-LM2) coupled to input INI, the other chain (LM3-LM4) coupled to input IN2. Alternatively, one chain can incorporate three line memories (LM1-LM3) coupled to input INI whereas the other chain has only one 'line memory LM4 coupled to input IN3. Behind the line memories 5 data paths (SEL1, INT1, HDEL1; SEL2, INT2, HDEL2; SEL3, INT3, HDEL3; SEL4, INT4, HDEL4; SEL5, COMP DEL) can be distinguished of which the first four can perform an interpolation. The fifth branch is a by-pass path having the same delay (provided by compensating delay block COMP DEL) as the nominal delay of the other branches. By means of the selector blocks SEL1-SEL4 at the input side of the data paths 1-4, the three interpolator inputs of each interpolator INT1- INT4 can be connected to any one of the three data inputs IN1- IN3 or one of the outputs of the four line memories LM1-LM4. The interpolators INT1-INT4 in branches 1 to 4 can be set into different interpolation modes as required for the interpolation of differently subsampled signals. Both linear and non-linear interpolations are possible. Preferred non-linear interpolation modes include the straightforward median interpolation known from EP-A 0,192,292 (PHN 11,613), and the median interpolation which is supplemented by a horizontal filtering as known from EP-A 0,344,854 (PHN 12,583). The interpolators can also be set to perform minimum and maximum functions; this does not call for any additional hardware as in order to determine the median of three input values, minimum and maximum determining logic should be provided anyway, see EP-A 0,192,292. All interpolators INT1-INT4 have two outputs to support the 54 Mbyte/s data rate 21

after interpolation. Each interpolator INT1-INT4 can also be set into a transparent mode in which case data at both interpolator outputs are copies of the data at the first two interpolator inputs. By means of the selector function at the input, the three interpolator inputs can be connected to either one of the three data inputs or one of the four line memory outputs.

The adjustable horizontal delays HDEL1-HDEL4 at the outputs of the interpolators INT1-INT4 have a range from 1 to 7 clock periods and are primarily intended for the horizontal displace¬ ment required for the motion po pensated interpolator.

Each interpolator output can be multiplied by a coefficient ranging from -1 up to +10 in a multiplier block MUL. The coeffi¬ cient is identical for both interpolator outputs. The data from the by-pass path may be multiplied by N*4 in which N may range from 0 to A. However, the maximum value of N depends on the multiplier coefficients in the four interpolator paths and may increase by one for each interpolator coefficient smaller than 3. The outputs of the multipliers (12bits) are added, scaled and limited to 8 or 9 bits before supplying to two cross switches. These cross switches facilitate an exchange of both data streams on output 1&2 of the IC. The signal at output 3 is an un-processed but delayed version of one of the input signals.

Control of the TDFS circuit.

The TDFS circuit as described above can be applied at various places in the decoder, provided that it can be set into the correct mode. To achieve this, the multiplexers, delays, interpolators and multiplier coefficients of the TDFS circuit can be controlled independently of each other by a control block CONT.

Control bits required to satisfy this requirement are not supplied in parallel to the TDFS circuit because this would cost a large number of control pins. Most of the internal control bits are static and need only be refreshed during the vertical blanking interval. Only horizontal delays and multiplier coeffi¬ cients need to be switched dynamically at block borders, at a rate of 27/8 Mhz. However, these need not to be switched inde¬ pendently of each other. For motion compensated interpolation the horizontal delays HDEL1-HDEL4 are controlled in two banks viz. one for the delay of odd samples and one for the delay of the even samples, or, formulated otherwise, one for each inter¬ polator output. The horizontal delay ranges from 1 to 7 pixels, and depends on the value of the horizontal vector. Because there are only 13 different values (-6 to +6) of the horizontal motion vector component, only 13 different delay adjustments are requi¬ red. Thus horizontal delays can be controlled by 4 bits. Only one look-up table (not shown) incorporated in the control block CONT will suffice to translate the externally supplied 4 control bits into the internally required horizontal delay parameters. The multiplier coefficients must be controlled by vertical vector information or by the branch decision signal on a block basis.

The number of possible multiplier coefficient combinations is restricted to about 10 per TDFS IC. These internally required multiplier control signals are derived from an internal look-up table as well. Also in this case only 4 bits (to select 1 out of 10 coefficient combinations) need to be supplied to the TDFS. Both look-up tables can be loaded externally so each TDFS has its specific translation table. The multipliers in the by-pass path and in the interpolator paths can also be disabled on pixel time basis by some internal counters.

Together only 8 bits per datv block (7 Mhz/8) are required for each TDFS. Thus only one 27 Mhz input for control is requi- red.

The input control signal at serial control data input SCD-IN should be in phase with the incoming data. This control signal is delayed in the control block CONT and looped through to the serial control data output SCD-OUT with the same delay as the video data. The static control bits are supplied to the TDFS circuit during the vertical blanking interval. During that interval all flip-flops and LUTS to be loaded are configured as a one bit wide shift register under control of an externally supplied ConFiguration Enable command (CFE) . The input for this configuration information is the same as the input for dynamic control (SCDin) . The output of this configuration chain is then connected to the SCD-output SCD-OUT.

Because line memory capacity allows only storage of active video samples, i.e. without samples corresponding to the hori¬ zontal blanking period, a horizontal reference signal indicating the position of the active samples is supplied to input HREF-IN of the TDFS circuit. This signal too is looped through the control block CONT in such a way that, the horizontal reference signal at output HREF-OUT is in phase with the output video data.

HD-MAC decoder implementation.

Once such a flexible TDFS circuit is available, most of the functions required for decoding bandwidth reduced HD-MAC signals can be realized thereby. The block diagram of the decoder is given in Fig. 10a and 10b for the data and control interfaces, respectively. It can be seen that the part of the decoder follo¬ wing the outputs of the subsample pattern converter (SSPC Y) 1014 is completely built up with TDFS circuits. Rear- rangement of the input part of the decoder allows upconversion of standard input signals (MAC/PAL/SECAM) to be performed with the same hardware. In the next paragraphs a more detailed de¬ scription will be given of the different decoder operation modes. As shown in Fig. 10, luminance and chrominance are pro- cessed in parallel. The only mutual interaction is that the overall delay in both channels should be identical. Each part will be described separately.

Luminance HD-MAC decoding.

Reference to Fig. 10a shows that the input luminance signal Y-in is applied to a temporal filter 1008 which includes a first field memory FM1. The memory output signal and the input signal are applied on lines II and III to a double deshuffling circuit (DESHUF Y) 1010. The first field memory FM1 operates on a 64 μs line time basis. By means of the double deshuffling circuit 1010 both the input and the output of the first field memory FM1 are converted to a 32 μs line time basis. The double deshuffle circuit 1010 has four outputs. Output line IV supplies the information from input line III, while information from input line II is supplied at the remaining three outputs. For HD-MAC decoding up to four consecutive fields are required for interpo¬ lation. Therefore two additional field memories FM2,FM3 are required which operate on the 32 μs line^* time basis. Because of the data rates to be handled in the case of upconversion of standard MAC/PAL/SECAM signals, field memories FM2 and FM3 are put in parallel, each being coupled to an output line of deshuf¬ fle circuit 1010. How this field memory configuration copes with HD-MAC signals is indicated in the timing diagram (Table 5) below, in which Tn indicates the video information of different field periods and in which IV, V, VI and VII are inputs to luminance subsample pattern converter 1014.

t (ms) : O 20 40 60 80 100 120

II = IV: Tl T2 T3 T4 T5 T6 T7

III = V: Tl T2 T3 T4 T5 T6

VI FM2: Tl Tl T3 T3 T5

VII FM3: T2 T2 T4 T4

TABLE 5

From the above diagram it can be easily seen that field memories FM2,FM3 are controlled such that after each write cycle they output the information received on line III during two successive field periods. Field memory FM2 is written into during field period t=20, the information is output during field periods t=40 and t*=60. The next write cycle is during field period t=60, the information is output during field periods t=80 and t=100. This write and read control of field memories FM2,FM3 allows a parallel arrangement to operate like a series arrange¬ ment, while maintaining the advantage that a parallel arrange¬ ment can cope with a higher data rate. Starting with field period t=60, four successive fields required for HD-MAC decoding are simultaneously available during each field period.

From the deshuffle circuit 1010 and field memories FM2,FM3 four data streams IV,V,VI,VII of 13.5 Mbyte/s are supplied to subsample pattern converter (SSPC Y) 1014 via 4 data lines of 4 bits each at 27 Mhz. Nibbles are multiplexed in time, with the least significant nibbles first. In the SSPC circuit 1014 the incoming subsample patterns are converted to two 40 ms mode subsample patterns (A & C) lying 40 ms apart in time. These two signals, having a data rate of 27 Mbyte/s, are supplied via 8 bit wide busses to two separate branches of the 40 ms mode motion compensated interpolator. Further the SSPC circuit 1014 passes the four incoming data streams via some compensation line delay to the 80 and 20 ms mode interpolators as will be descri¬ bed below.

The outputs of SSPC circuit 1014 are coupled to TDFS cir¬ cuits b-i for interpolation and further processing of the lumi¬ nance 20/40/80 ms mode signals. Figs. 11-13 to be described now show these TDFS circuits in more detail.

40 ms mode motion compensated luminance interpolation.

As shown in Fig. 10a, each branch of the 40 ms mode motion compensated interpolator is realized by cascading two TDFS circuits, viz. TDFS b,d for branch C and TDFS c,e for branch A.

A more detailed schematic representation of this implementation is given in Fig. 11 which shows four TDFS circuits of the type described with reference to Fig. 9. However, in the simplified schematic representation of Fig. 11 and following figures sho¬ wing TDFS circuits, only- one output line represents the two interpolators outputs. To simplify the drawings, the horizontal delays HDEL1-HDEL4 are no longer shown. The multiplier block MUL of Fig. 9 is represented by separate multipliers at the outputs of the interpolator branches INT1-INT4 and the compensating delay branch COMP DEL of Fig. 9. The AD+SCAL block of Fig. 9 is symbolized by an adder followed by a multiplier with coefficient 1/8.

Both TDFS circuit pairs c,e and b,d are cascaded by connec¬ ting outputs OUT1 and OUT2 (with intermediate results) of the first TDFS circuits b,c respectively to inputs IN2 and IN3 of the second TDFS circuits d,e which lead these through their bypass branches with compensating delay COMP DEL through multip¬ liers c-_jp with coefficient 8 to the final adder in the respective second TDFS circuits d,e. The line memories LM1-LM3 of the first TDFS circuits b,c are connected via outputs OUT3 to inputs INI of TDFS circuits d,e and their line memories I_M4b-LM7. So in fact TDFS combinations c,e and b,d function as two circuits in parallel, giving a chain total of 7 line memories (as line memory LM4a in TDFS b,c overlaps line memory LM4b in TDFS d,e) or 8 possible vertical taps as required by the motion compensa- ted interpolator branch shown in Fig. 8. On each vertical tap a non-linear interpolator M2-M7 provides in parallel an interpola¬ ted pixel and a copy of the central input. Nominal vertical displacement is 4 taps, giving a 4 line processing delay of the motion compensated interpolator.

Even field processing

For 40 ms mode blocks a pixel is selected conform the vertical vector component with the proper vertical contour correction (-1 10 -1) or combined vertical contour correction and vertical interpolation (-1 5 -l) by switching the multiplier coefficients cl-cδ as follows, in which a dot (.) represents a zero coefficients branch vertical vector value branch

+6 +5 +4 +3 +2 +1 -1 -2 -3 -4 -5 -6

As can be seen in Fig. 11, at the extreme taps there is no normal median interpolation possible because only 7 line memo¬ ries are used. Consequently, the filters Ml' and M8• are shown to have only two inputs. The interpolator performs either linear or half median interpolation as explained with respect to Table 4 above. Because for even vertical vectors an even field pixel is required, a vertical interpolation must still be carried out: simply (4) instead of (-1 5 -1). Ml' and M8• can be used for vectors -4 and -5 by using coefficients (-1 5 -1) and (-1 10 -1) .

Horizontal displacement is accomplished by means of the 1 to 7 pixel delay chains (HDEL1-HDEL4 in Fig. 9) which, in accor¬ dance with the horizontal vector component, are changed from their nominal setting (a 4 pixel delay) as follows: a further cross switch takes care that the odd samples remain at outl.

Here, X-sw "0" means no change, while X-sw "1" means a cross- switching of 0UT1 and 0UT2.

TDFS c,e and TDFS b,d apply the same operation for 40 ms mode blocks except that they interpret the vectors with opposite signs. For non-40 ms mode blocks, the coefficients are set for a simple vertical (4) interpolation. For odd pixels however, the multiplier c^ in the bypass branch of TDFS b,c is set to 0, which results in a copy of the 40 ms mode odd field samples, although with half their luminance value due to the scaling by 8; for even pixels the vertically interpolated (even field) 40 ms mode samples are output. These are the pixels from the 40 ms mode odd and even fields to be used later on by the second step 80-SSPC in TDFS f,g as will be described below.

Odd field processing

Here both TDFS cascades c,e and b,d do not distinguish between modes, but each TDFS cascade functions differently: TDFS c,e perform the non-linear interpolation with linear vertical contour-correction (-1 10 -1) required for a -1 motion vector; TDFS b,d do a vertical interpolation (-1 5 -1) as required for a 0 motion vector. Again both 40 ms mode odd and even field pixels are available for use later on by the 80-SSPC in TDFS f,g.

Both TDFS cascades output the 54 Mhz interpolated data via 2 outputs of 27 Mhz each: outputs 0UT1 of TDFS d,e supply the odd samples (40-A od / 40-C od) and outputs OUT2 of TDFS d,e supply the even samples (40-A ev / 40-C ev) .

Multiplexing of 20/40/80 ms mode luminance blocks. TDFS f,g shown in Fig. 12 are used to perform a DATV con¬ trolled multiplexing and addition of 80 and 20 ms blocks having subsampling patterns SSPC-I od and SSPC-II ev coming from SSPC circuit 1014 of Fig. 10 and the 40 ms blocks from both branches 40-A,40-C of the motion compensated interpolator. Each TDFS handles one of the 27 Mhz video data streams: TDFS g handles the odd samples and TDFS f the even samples. The incoming 80 and 20 ms mode blocks are delayed by 4 line periods by leading them through the 4 line memory chain LM1-LM4, to compensate for the processing delay of the motion compensated interpolator, before leading them through the bypass branch.

TDFS f,g also serve to average both 40 ms mode signals from motion compensated interpolator branches' A and C. Additionally to this averaging function a compensation for intensity errors is performed in TDFS f,g. The 40 ms motion compensated interpo¬ lator output amplitude is too small (especially when high spati¬ al frequencies occur) if the vector controlled displacement is not completely correct. Beάause motion compensation is only performed during even fields, this error gives rise to a 25 Hz flicker effect in highly detailed 40 ms mode areas. The larger the difference between the outputs of the motion compensator branches, the more the flicker can be perceived. Therefore a correction signal equal to l/4*abs(A-C) is added to the nominal motion compensator output signal l/2*(A+€). The resulting output signal can be rewritten by: 6/8*max(A,C) + 2/8*min(A,C) . Inter¬ polators INTl of TDFS f,g are set to their max(Sl,S2) and inter¬ polators INT2 are set to the min(Sl,S2) operation mode, and multiplication factors cl=6/8 and c2=2/8 are applied to their output signals. It should be remarked that this operation is optional and is only applicable to 40 ms blocks. Further details about this correction can be bbtained from the non-prepublished European patent application EP-A 0,392,576 (PHN 12,902).

The DATV controlled multiplexing between 20/40/80 ms mode blocks is achieved by appropriate switching of the multiplier coefficients cl, c2 and c5 of these max and min 40 ms branches and the 80 ms bypass branch, respectively. As known from EP-A 0,322,956, to perform a complete 80 ms mode interpolation, in principle information from four consecutive 80 ms mode blocks is required. As the decoder according to the present invention has only 3 field memories, this information may be not available in case of certain temporal mode transitions. For those transiti¬ ons, according to the present invention, TDFS f,g also perform the conversion to a full 80 ms mode subsample pattern of 80 ms mode blocks, by insertion of missing samples from the 40 ms mode interpolation path as set out in the following table. These cases are illustrated in Fig. 2. Multipliers c3,c4 of two bran¬ ches are switched on a pixel-by-pixel basis to select the 40 interpolator output with their interpolators INT3 and INT4 set into transparent mode (symbolically indicated by vertical arrows in Fig. 12). The video data stream prepared in TDFS b..e con- tains all 40 ms mode odd and even field samples needed to com¬ plete the 80 ms mode subsample pattern: when odd fields are processed, TDFS c,e output the 40 ms mode odd field and TDFS b,d output the vertically interpolated 40 ms mode even field. When even fields are processed, TDFS c,e output 1 contains 40 ms mode odd field samples (with half intensity) while output 2 furnishes vertically interpolated even field samples intensity is correc¬ ted by setting c3 and c4 to 8.

missing available samples in TDFS at

even (field 4) F (IN3) odd (field 1) G (IN2) odd/even (field 1,2) G/F (IN2) odd/even (field 3,4) G/F (IN2/3) odd/even (field 3,4) G/F (IN2)

Herein, nδO indicates a non-δO ms mode block, δO indicates a δO ms mode block, n20 indicates a non-20 ms mode block, and 20 indicates a 20 ms mode block.

Both TDFS f and TDFS g output a 27 Mhz stream of multi- plexed 80/40/20 ms mode odd (od) or even (ev) samples, respecti¬ vely.

80 and 20 ms mode non-linear luminance interpolation.

The data streams from TDFS f,g are supplied to TDFS h (shown in Fig. 13) , in which the line memories LM1-LM4 are configured into two chains of two line memories in parallel. This splits in fact TDFS h up into two equivalent parts, one handling the odd samples and one the even samples. With the aid of the median interpolators Y80, Y20-1 and Y20-1, the incoming 80 and 20 ms mode blocks are spatially interpolated in parallel whereas the already interpolated 40 ms mode information is fed via the by-pass branch with compensating delay COMP DEL. The fourth interpolator INT4 is not used and its multiplier coeffi¬ cient c4 is 0. As also shown in Fig. 13, two 20 ms mode interpo¬ lator cells Y20-1 and Y20-1 are used for the 20 ms mode blocks, since also a horizontal (1 1) interpolation is to be done. This is achieved by using 2 different 20-mo.de interpolations: both give the same 20 ms mode interpolated results but the second (Y20-2) is 1 clock period shifted (by HDEL2 shown in Fig. 9) compared to the first (Y20-1) . Averaging both outputs by means of multiplier coefficients (4) results, in the desired horizontal interpolation. The multipliers cl-c^_ are controlled as indicated in Fig. 13 using the top, middle and lower multiple value sets for the 80, 40, 20 modes respectively, controlled by the DATV data. Outputs OUT1 and OUT2 supply odd and even 27 Mhz signals.

Vertical Linear Filter.

To improve the compatibility of the HD-MAC signal with normal definition MAC receivers, the HD-MAC encoder performs a vertical low pass filtering which has to be undone by the HD-MAC decoder. Therefore, as a last step in the luminance channel, an inverse vertical compatibility improvement filtering is perfor- med by TDFS i shown in Fig. 13. TDFS i is configured as two 3 tap linear vertical filters in parallel in order to cope with the 54 Mbyte/s data stream out of TDFS h. The interpolators INT1-INT4 in TDFS i are switched to transparent, i.e. both outputs of each interpolator INT1-INT4 supplies copies of input samples applied to both inputs (symbolized by vertical arrows) and the transfer of the vertical filter formed by TDFS i is determined by the multiplier coefficients cl-c5. Optionally the filter may be switched between 6 dB enhancement (-2 12 -2) or 3 Db enhancement (-1 10 -1) . The values of the multiplier coeffi¬ cients cl-c5 shown in Fig. 13 correspond to the 6 Db enhance¬ ment.

Chrominance HD-MAC decoding.

Turning back now to Fig. 10 for the block diagram of the chrominance HD-MAC decoder according to the invention, the input chrominance signal C-in is applied to a compensation delay block lOOδC, which compensates for any processing delay difference between luminance and chrominance processing. The delayed chro¬ minance signal is deshuffled to the 32 μs line time domain by deshuffler chrominance (DESHUF C) lOlOC. The deshuffler output signals are supplied to field memories FM4-FM6 which are confi- gured in parallel. The relevant timing diagram on field basis is shown below.

t (ms) : O 20 40 60 80 100 120

From the above diagram it can be easily seen that field memories FM4-FM6 are controlled such that after each write cycle they output the information received during three successive field periods. Field memory FM4 is written into during field period t=0, the information is output during field periods t=20, t=40 and t«60. The next write cycle is during field period t=60, the information is output during field periods t=80, t=100 and t=120. This write and read control of field memories FM4-FM6 allows a parallel arrangement to operate like a series arrange¬ ment, while maintaining the advantage that a parallel arrange¬ ment can cope with a higher data rate. From field period 60, the four sucessive fields required for HD-MAC decoding are available at the same time during each field period.

The four data streams of 6.75 Mbyte/s output by deshuffle circuit 1010C and field memories FM4-FM6 are fed to chrominance subsample pattern converter (SSPC C) 1014C via 4 bit wide inter¬ faces on 13.5 Mhz. SSPC circuit 1014C generates one 27 Mhz data stream, containing a 20/40/80 multiplex of relevant samples of both U and V. SSPC circuit does not perform a real interpolation but it just places neighboring input samples at missing positi- ons.

Because in the MAC transmission standard the chrominance components U and V are transmitted line alternately, the verti¬ cal block borders for ϋ and V are 64 μs out of phase at the input. Therefore, chrominance SSPC circuit 1014C also performs a delay of 64 μs in the U. signal. By doing this the block borders for U and V are in phase in the cascaded interpolation part formed by TDFS circuits j—1.; The data format at the SSPC and interpolation input on line time basis is as follows:

SSPC in : <

U & V : a c m

SSPC out U V Herein, the symbols a-q indicate chrominance line signals.

When the incoming signal is coded in the 80 ms mode, the SSPC circuit 1014C delivers 360 samples per chrominance compo- nent (U and V) per 32μs. In the chrominance interpolator blocks TDFS j-1 this signal is upconverted horizontally to 720 samples per component per line. In case of 40 ms mode coded blocks only one out of two lines contains 360 valid samples per component. Both horizontal and vertical interpolations should be done on this data stream. For 20 ms mode coded blocks the valid informa¬ tion is also transferred every other line but only 180 samples per component per line are relevant. A horizontal upconversion by a factor 4 and vertically by a factor 2 are carried out on this data stream.

Figs. 14-16 to be described below show the TDFS circuits j-1 in more detail. The outputs of TDFS j are coupled to a saturation improvement circuit 1044C which supplies the output U and V components U-out and V-out.

Horizontal chrominance interpolation.

The output signal of the chrominance SSPC circuit 1014C is fed to TDFS j which performs the horizontal interpolation as illustrated in Fig. 14. The four line memories LM1-LM4 are used to supply the necessary vertical aperture. The first interpola¬ tor TJV20 performs the 20 ms mode median interpolation over 5 vertical taps; the second interpolator UV80-1 performs the normal 60 ms mode median interpolation over 3 taps; the third interpolator UV40 is set to do the 40 ms mode linear interpola¬ tion on the central tap. Multiplexing between modes is done by means of DATV controlled switching of the multiplier coeffi¬ cients cl-c4. At vertical spatial block borders (first and last block lines) the apertures of the chrominance interpolation filters may not cross the borders. Therefore the fourth interpolator UV80-2 operates in accordance with an 80 ms exception interpola¬ tion mode (which simply takes a vertical copy of the border pixels instead of the median) and is used instead of the normal 80 ms mode interpolation UV80-1 by switching the multiplier coefficients cl-c4 properly. A schematic representation of this modified border interpolation is givpn^in Fig. 15. The samples indicated by 'x' are incoming samples. The samples m are derived by the spatial median interpolation known from EP-A 0,344,654 (PHN 12,563). The samples indicated by 'o' are border samples which are copied from spatially adjacent samples.

The bypass branch with the compensating delay COMP DEL is not used and its multiplier coefficient c5 is set to 0. Finally, the U and V samples are separated; ϋ via output 0UT1, V via output OUT2.

Vertical chrominance interpolation.

Because of the vertical delay difference of two lines between the color difference components TJ and V, these compo¬ nents are interpolated vertically in different TDFS circuits. The required vertical interpolation of the U component is per¬ formed in TDFS k while TDFS 1 copes with the vertical interpola¬ tion of the V component. A functional block diagram of both TDFS circuits is given in Fig. 16. Besides this vertical interpolati¬ on, TDFS k and 1 also provide the vertical timing matching between U and V. In each of TDFS k and 1, the V samples are delayed by one line period relative to the U samples.

As described above, vertical interpolation by a factor 2 should be applied to 40 ms mode and 20 ms mode blocks. In conformance with the HD-MAC decoding algorithm, these blocks must be interpolated differently in the vertical direction. In the case of 40 ms mode blocks, two interlaced fields should be generated. In case of 20 ms mode blocks, only the odd field lines have to be interpolated. It should be remarked that δO ms mode blocks need not to be interpolated vertically and are passed through to the output having the same delay as 20 ms mode and 40 ms mode blocks. The different vertical interpolations are performed by DATV controlled switching of the multiplier coeffi¬ cients cl-c4 in TDFS k,l with all interpolators INT1-INT4 set to transparent (indicated by vertical arrows) . At vertical 40 ms block transitions the vertical interpolation is modified under DATV control. The compensating delay branches COMP DEL are not used; their multiplier coefficients c5 are 0.

HD-MAC decoding operation in the film-mode.

In the so-called film-mode neither the 20 ms mode nor motion compensation for the 40 ms mode are used. In case of 40 ms mode blocks, the TDFS circuits get zero vectors via their SCD control. Only TDFS f,g are affected by this extra HD-MAC deco¬ ding mode. During even field processing, no motion compensation is carried out. Instead, the 40 ms mode interpolated data is taken directly from input IN2 by selecting the third interpola¬ tion branch in TDFS fig. 12.

Upconversion of normal definition signals.

A receiver containing the hardware for decoding HD-MAC signals, can also receive standard MAC, PAL or SECAM signals.

However, the display of the HD-MAC receiver has an aspect ratio of 16:9 whereas the scanning is at 32 kHz because HD-MAC has

1250 lines / frame while PAL/MAC/SECAM have only 625 lines / frame. Therefore normal definition standard input signals should be upconverted to the HDTV display standard. Because of the built in flexibility and the amount of TDFS circuits available in the interpolation part of the HD-MAC decoder, it is possible to perform this conversion from 625 lines with an aspect ratio of either 4:3 or 16:9 to the HD-MAC display format of 1250 lines with a 16:9 aspect ratio. A more detailed explanation of this conversion and the additional demands for the decoder circuits are elucidated below. Horizontal upconversion of input luminance signals with a 4:3 aspect ratio.

The first step in the conversion process is the horizontal conversion from 64 μs lines with 52 μs of active video to 32 μs line time with its video information compressed into 19.5 μs. Thus the video information should be eompressed by a factor 2 * (16/9)/(4/3) - 8/3. This compression is performed in the luminance deshuffling circuit 1010 of Fig. 10 which implies an extra operation mode for this circuit. With respect to data rates, this implies an effective data rate of 8/3 * 13.5 - 36 Mbyte/s at the output of the deshuffler 1010. Because the system clock frequency of the decoder is 27 Mhz, two outputs should be used simultaneously thus together capable of transferring 54 Mbyte/s. The effective data rate is only 36 Mbyte/s which means that only 2/3th of the samples contain valid data. For simplici¬ ty in the internal control of the TDFS circuits the data stream out of the deshuffler 1010 contains 2 duplicated samples per group of 6. The output format of the luminance deshuffling circuit 1010 in which the symbols refer to 36 Mhz samples, is as follows: ,

outl: Sa j Sb j Sc j J Se j Sf I Sg i I Si J Sj j Sk out2: Sb j Sc j Sd j j Sf [ Sg j Sh j j Sj j Sk | SI

where output 1 signifies the lines directly connected to SSPC 1014, while output 2 signifies data lines connected to the inputs of the field memories. The information of two successive fields is available at inputs II and III of the deshuffling circuit (Fig. 10) . Both fields are supplied to the rest of the decoder in a line sequen¬ tial way (after compression) as indicated (on line time basis) below: 36

< 64 μs > input II of deshuffler: a —j— e —j— l —j— input III of deshuffler: c —j— g —j— k —j— output 1: a j c e ! g i | k output 2: a j c e ! g i ! k

These signals are fed via field memories FM2,FM3 and lumi¬ nance SSPC circuit 1014 to the interpolation part of the deco¬ der. The delay of the field memories FM2,FM3 is set to the simplest minimum value, e.g. one line. The SSPC circuit 1014 does not perform any interpolation but compensates for the delay of the field memories by delaying the signals at input IV and V by one line as well. The interpolation part of the decoder receives this 36 Mbyte/s data stream and converts it to a sample rate of 54 Mhz by interpolating the missing samples. This inter¬ polation process is illustrated schematically below:

input (36 Mbyte/s) t . . t . . t . . t . . t . . t sample index a b c d e f

output (odd samples) t . . . t . . . t . . . t . . . output (even samples) t . . . t . . . t . . . t . sample index 1 2 3 4 5 6 7 8

The interpolating filter operates on an imaginary frequency of 3*36 = 108 Mhz, but in practice only the required output samples (54 Mhz) will be calculated. The impulse response of the interpolating filter on lOδ Mhz basis is:

H(t) = (-1 -2 0 6 13 16 13 6 0 -2 -1) . The corresponding norma- lized frequency response is given in Fig. 17. The arithmetic operation to be performed in the interpolation part is: sample 1: 16*a sample 2: -l*z + 6*a + 13*b -2*c sample 3: -2*a + 13*b + 6*c -l*d sample 4: 16*c sample 5: -l*b + 6*c + 13*d -2*e sample 6: -2*c + 13*d + 6*e -l*f After three periods of 27 Mhz this process repeats. In order to have unity gain, all coefficients should be divided by 16. As can be seen from the formulas above, an output sample is calculated from maximally four input samples. This purely hori- zontal operation is performed by the TDFS circuits b to g confi¬ gured as shown in Figs. 16, 19. The input selectors all select the same vertical tap viz. directly to input; therefore, the line memories LM1-LM4 are unconnected. The interpolator INT1- INT4 are switched to transparent and the adjustable (horizontal) delays in the TDFS branches are set to appropriate values to select the pixels needed for the interpolation. Because two TDFS circuits are cascaded (c,e and b,d in Fig. 18) up to 10 adjacent samples may by combined to one output sample and this is suffi¬ cient to cope with the impulse response and the irregular input sequence as indicated above.

In order to achieve the coefficient accuracy of 1/16, both cascades operate in parallel and are combined in TDFS f and g with a gain factor of 1 (i.e. multiplier coefficient c5 of TDFS f,g is 8 for branch A, and a gain factor of 0.5 (i.e. multiplier coefficient c4 of TDFS f,g is 4) for branch C (Fig. 19) . This means the required impulse response is subdivided over both branches as:

H(t)c,e = (-1 -1 O 3 6 8 6 3 0 -1 -1) / δ H(t)b,d = (+1 0 0 0 +1 0 +1 0 0 0 1) / 16

This gives as coefficients for TDFS c,e: 6, 3, -1, -1, δ and for TDFS b,d : 1, 0, 0, 1, δ. The coefficients should be altered with a repetition rate equal to 1/3 of the incoming signal instead of 1/δ as was the " case in the HD-MAC decoding mode. However, because only 4 multipliers should be activated at a time, this dynamic switching can be restricted to enabling/dis¬ abling fixed multiplier coefficients on a pixel time basis. The interpolation action can be summarized as follows:

51 is copied from the input.

52 is interpolated in TDFS d,e

53 is interpolated in TDFS d,e. S4 is copied from the input.

55 is interpolated in TDFS b,c.

56 is interpolated in TDFS b,c.

Other implementations are of course possible, though this is the preferred embodiment for the particular filter structures.

In Fig. 19, line memories LM1-LM4 are unconnected, interpo¬ lators INT1-INT3 are unused and their multiplier coefficients cl-c3 are 0.

Horizontal upconversion of input luminance signals with a 16:9 aspect ratio.

If the input MAC signal already has the correct aspect ratio, then only a compression to 32μs lines and sample rate conversion to 54 Mhz must be performed. In this case also the compression will take place in the deshuffler 1010 of Fig. 10, whereas the horizontal interpolation is done in TDFS b to g. The output format (27MHz) of deshuffler 1010 is as follows:

outl: Sa } Sb ! j Sc j Sd j j Se j Sf j j Sg I Sh out2: Sa j Sb j j Sc ! Sd j j Se j Sf j j Sg j Sh

The horizontal interpolation is indicated schematically below:

input (27 Mbyte/s) t . t . t . t . t . t . t . t sample index a b c d e f g h

output (odd samples) t . t . t . t . t . t output (even samples) t . t . t . t . t . t sample index 1 2 3 4 5 6 7 8 9 10 11 12 The interpolating filter operates on an imaginary frequency of 2*27 = 54 Mhz, and the impulse response of the interpolating filter on the 54 Mhz basis is:

H(t) = (+2 0 -5 0 19 32 19 O -5 0 +2). The corresponding norma¬ lized frequency response is shown in Fig. 21. The arithmetic operation to be performed by the interpolation part of the decoder is: sample 1 = 32c; sample 2 = 2a -5b + 19c + 19d - 5e + 2f.

It is implemented in the same way as the 4:3 upconversion: use the two cascades of TDFS c,e and b,d to get the necessary accurate coefficients and add both results in TDFS g,f, now with respective gains 1 and 0.25. Thus the impulse response is again subdivided over 2 branches:

H(t)c,e = (0 0 -1 0 4 8 0 -1 0 0) / 8 H(t)b,d = (2 0 -1 0 3 0 3 0 -1 0 2) / 32 determining the needed coefficients in TDFS c,e : 0, 4 , -1 , 0, 8 and in TDFS b,d : 2, 3, -1, 0, 8.

In the 16:9 case the multiplier coefficients are operated in a 2 phase cycle.

Vertical interpolation for luminance upconversion.

Thus a horizontal sample rate conversior to the 54 Mhz display clock frequency is performed in the luminance deshuf¬ fling circuit 1014 and TDFS b to g. In the vertical direction the lines from two adjacent fields are combined into one 625/1:l/50Hz signal without motion adaptation. The adaptation to movement is performed by applying line alternately a straightforward three point vertical median interpolation, see EP-rA 0,192,292 (PHN 11.613). This median filter is allocated to TDFS h which is configured as shown in Fig. 20. Two identical sections (each having two line memories LM1,2/LM3,4 and one median filter od/ev) are put in parallel in order to cope with the 54 Mhz data rate. The unused interpolators INT2,INT4 and the unused bypass branch COMP DEL are connected to multipliers c2,c4,c5 with zero coefficients.

The last step in the vertical interpolation process is performed by TDFS i which converts the 54 Mhz 625/1:1 signal to the 1250/2:1 display format by linear vertical interpolation. Line memories LM1-LM4 furnish the information of three adjacent lines which is used for this interpolation and the coefficients are (-1 15 2) for odd fields and (2 15 -1) for even fields. To get the coefficient 15, two branches are used with coefficients 7 and δ. All interpolators INT1-INT4 are set to transparent and the unused bypass branch COMP DEL is connected to a multiplier c5 with a zero coefficient.

Horizontal interpolation for upconversion of chrominance signals with a 4:3 aspect ratio.

The chrominance input signal is in accordance with the CCIR 4:2:2 format. The two chrominance components U and V are sup¬ plied in a pixel multiplexed data stream of 13.5 Mbyte/s. The chrominance deshuffling circuit 1010C of Fig. 10 acts primarily as a compression memory but it also separates U and V. The compression factor is δ/3 which results in an output data rate of 36 Mbyte/s. The output format of this deshuffler 1010C is as follows:

outl on X,XI: Ua j Ub j Ub J 1 jI Uc j Ud j Ud^' j I JI Ue { Uf ' out2 on XII,XIII: Va j Vb j Vb ! jj VVcc jj VVdd !J VVdd I Ij jI I VVee !J VVff j'

In the chrominance path no vertical inter field interpola¬ tion is performed in the upconversion mode but the incoming lines of one field are repeated twice. The timing diagram on line time basis is given below. 43

deshuffler input : - UVa - - UVe - - UVi - output X,XI (U samples): Ua Ua ! Ue Ue I Ui Ui output XII,XIII (V samples): Va Va ! Ve Ve j Vi Vi

After compression the sεunple rate of the U and V signals should be up-converted from 18 Mbyte/s to the display clock frequency of 27 Mbyte/s. This is schematically indicated below:

input (16 Mbyte/s) sample index

output (U or V) sample index

This horizontal interpolation is performed by TDFS j,k shown in Fig. 23. Because only a horizontal interpolation is required, the line memories LM1-LM4 in TDFS j,k are unconnected. All interpolators INT1-INT4 are set to transparent, indicated by vertical arrows. Horizontal delay circuits HDEL1-HDEL4 provide appropriate horizontal delays as required for the horizontal interpolation.

The impulse response (on 27 Mhz) of the transversal filter is H(t) = (-1 0 3 6 8 6 3 0 -1) . The corresponding normalized frequency response is shown in Fig. 22. The calculation of the output samples is as follows: sample 1 = 8*a; sample 2 = 3*a + 6*b -l*c; sample 3 = -l*a + 6*b +3*c.

After three output samples this process repeats. The calculation is effected by appropriate coefficient settings of multipliers cl-c5 as shown in Fig. 23.

As shown in Fig. 23, U and V are processed in parallel. Since the coefficients are simple, only two TDFS circuits (j and k) are needed for the chrominance upconversion (instead of four as needed for the luminance upconversion) . A functional illust¬ ration of the interpolation algorithm is given below. All indi¬ cated sample values should be divided by δ. input TDFS j 8a 8b 8b 8c 8d 8d 8e 8f 8f 8g

output TDFS j -la -lc -le

=input TDFS k 8a 8b 6b 8c 8d 6d 8e 8f 6f 3c 3e 3g

3a -la 3c -lc 3e -le output TDFS k 8a 6b 6b 8c 6d 6d 8e 6f 6f

-lc 3c -le 3e -lg 3g

The interpolation action can be summarized as follows: Samples 1,4,7,... are copied from the input. Samples 2,5,8,... are interpolated in TDFS k. Samples 3,6,9,... are interpolated in TDFS j.

Horizontal interpolation for upconversion of input chrominance signals with a 16:9 aspect ratio.

The required time compression by a factor two takes place in the chrominance deshuffler 1010C of Fig. 10. The output format of the deshuffler 1010C in this case is as follows:

outl on X,XI: Ua Ua I I I 1 Ub ! Ub I I I I I Uc Uc I I I Ud I Ud out2 on XII,XIII: Va ! Va I I I I I I I I Vb ! Vb I I Vc ! Vc I I Vd ! Vd

The interpolating filter operates on an imaginary clock frequency of 27 Mhz. The impulse response of the interpolating filter is H(t) = (-1 0 5 8 5 0 -1) . The corresponding normalized frequency response is shown in Fig. 24. The calculation of the output samples is as follows:

input (13.5 Mbyte/s) sample index output (U or V) sample index Herein, sample 1 = 8b and sample 2 = -la + 5b + 5c - Id. After two clock pulses the interpolation process repeats which implies that the multiplier coefficients should be switched in two phases. The interpolation algorithm as described above can completely be handled by TDFS j. TDFS k is set to transparent in this case.

Vertical linear interpolation for chrominance upconversion.

For the vertical interpolation of chroma in the upconversi¬ on mode, only lines from one field are used. In TDFS 1 (see Fig. 23) a simple (1) vertical interpolation is performed using 3 branches. The fourth interpolator INT4 and the bypass path COMP DEL are unused; their multipliers c4,c5 have zero coefficients. The (1) vertical interpolation can be effected by appropriate coefficient switching of multipliers cl-c3; the interpolators INT1-INT3 are set to transparent. It should be remarked that the output is not interlaced which asks for different control of the multiplier coefficients cl-c3 during odd (0 4) and even (4 0) fields. As can be seen from Fig. 23, U and V are processed in parallel.

The above description shows preferred embodiments of the invention, but should not be limited thereto, as the skilled worker will be able to conceive many modifications thereof which are encompassed in the scope of the following Claims.

Claims

Claims:

1. A decoder apparatus for decoding input signals divided into a plurality of adjacent blocks, each encoded in accordance with a selected one of a plurality of coding modes, each coding mode having an associated sampling pattern, comprising: input means coupled to receive said input signals for furnishing samples from a present field and from a plurality of preceding fields, first decoding means coupled to said input means for processing samples from blocks sampled in accordance with a first sampling pattern, second decoding means requiring samples from a plurality of temporally successive blocks sampled in accordance with a second sampling pattern, and selector means for selectively coupling said input means or said first decoding means to said second decoding means to furnish said required samples to said second decoding means.

2. HDMAC decoder having means operative under control of a motion vector for interpolating a first field from first and second data respectively associated with a second field and a third field, and first and second means for respectively furnis¬ hing said first and second data in response to said received encoded data, characterized in that said first means comprises median interpolation means furnishing median output samples in response to said received encoded data, a plurality of line delay members connected to said median interpolation means for furnishing a plurality of delayed output samples, vertical interpolation and contour correction means having a plurality of inputs, selection means operative under control of said motion vector for connecting the outputs of selected ones of said line delays to respective ones of said inputs, and wherein said vertical contour correction and interpolation means comprises means for multiplying signals at respective ones of said inputs by respective weighting constants selected for simultaneous contour correction and interpolation, and combining means for combining the so-weighted input signals to generate at least part of said first data.

3. HDMAC decoder having a first processing branch receving encoded subsamples for processing said subsamples by median interpolation, vertical contour correction, delayed subsample selection under control of a motion vector, and weighting and combining of selected delayed subsamples to create first field interpolation samples, characterized in that combined means are provided for simultaneously effecting said vertical contour correction and said weighting of said delayed subsamples.

4. HDMAC decoder as claim in Claim 3, characterized in that said combined means has a plurality of inputs for receiving respective delayed subsamples selected under control of said motion vector, and multiplier means for multiplying the samples at each of said inputs by respective multiplication factors, said multiplication factors incorporating both said vertical contour correction and said vertical interpolation.

5. HDMAC decoder as claimed in Claim 3, characterized in a plurality of cascaded line delay numbers connected to receive said input subsamples, a plurality of median interpolator means corresponding in number to said plurality of line delay members and connected thereto, each furnishing a median output sample, and selector switch means operative under control of said motion vector for supplying selected ones of said median interpolator output samples to said combined means.

6. HDMAC decoder as claimed in Claim 5, wherein said deco¬ der also has a second processing branch receiving encoded sub¬ samples for processing as in said first processing branch and furnishing second field interpolation samples, characterized in that second combined means are also provided, and wherein said selector switch means further furnishes other selected ones of said median output samples to said second combined means, so that said second combined means furnishes said second field interpolation samples.

7. HDMAC decoder as claimed in Claim 6, wherein said first processing branch processes even received encoded subsamples and said second processing branch processes odd received encoded subsamples.

8. HDMAC decoder for processing received encoded subsam¬ ples of a video image signal under control of a motion vector varying in magnitude in accordance with motion in said image. comprising

- first filter means for filtering said encoded subsamples in accordance with a first filter mode;

- second filter means for filtering said encoded subsamples in accordance with a second filter mode; and

- means for selecting said first or said second filter means to process said encoded subsamples under control of said motion vector.

9. HDMAC decoder as claimed in Claim 8, wherein said selec- ting means selects said first or said second filter means when said magnitude of said motion vector is, respectively, less than or greater than a predetermined magnitude.

10. HDMAC decoder as claimed in Claim 9, wherein said first filter means comprises a median filter and said second filter means comprises a linear filter.

11. HDMAC decoder as claimed in Claim 9, wherein said first filter means comprises a median filter and said second filter means comprises a half median filter.

12. Multipurpose integrated circuit, comprising: - a control input;

- a plurality of data inputs;

- a plurality of data outputs;

- a plurality of processing circuit;

- a plurality of interconnectable delay members; - controllable selector means for connecting said delay members to each other to form selected delays and for connecting said selected delays to said processing circuits at least in part in response to selector controls signals;

- externally loaded look-up table means connected to said con- trol input for furnishing said selector control signals in response to chirj control signεtls applied to said control input;

- output means connected to said processing means and said data outputs for furnishing output samples including processed sam¬ ples in response to data applied at said data inputs.

13. An integrated circuit as claimed in Claim 12, wherein said output means comprises multiplier means having controllable coefficients, and addition and scaling means, and wherein said look-up table means further controls said multiplier coeffi¬ cients.

14. An integrated circuit as claimed in Claim 12, further comprising compensatory delay means connected in parallel to said processing means.

15. An integrated circuit as claimed in Claim 12, wherein said delay members are line delays.

16. An integrated circuit as claimed in Claim 15, wherein said processing circuits comprise interpolator circuits.

17. An integrated circuit as claimed in Claim 16,

- wherein said data inputs receive encoded samples of a video signal; and

- wherein said look-up table means receives at least part of said chip control signals during the vertical blanking intervals of said video signal.

18. An integrated circuit as claimed in Claims 12 or 17 wherein said interconnectable delay members have a first delay member connected to a cascading output and a second delay member connected to a cascading input; and further comprising means for connecting said cascading output of one of said integrated circuits to said cascading input of another, thereby connecting said delay members in cascade.

19. Decoder having a plurality of interpolation circuits, characterized in that said interpolation circuits comprise at least one of the multipurpose integrated circuits claimed in Claim 12.

20. Decoder as claimed in Claim 19, characterized in that said interpolation circuits comprise a motion compensated inter¬ polation circuit, and further characterized in that said motion compensatod interpolation circuit comprises a plurality of said multipurpose integrated circuits, at least a first and second one of said circuits being connected in cascade.

21. A filter arrangement for filtering several types of input data signals in accordance with a plurality of filtering modes, comprising control means coupled to receive input control signals and having a selection control output for furnishing selection control signals and a filter control output for fur- nishing filtering mode control signals, data input means for receiving said input data signals, memory means coupled to said data input means for furnishing delayed data signals, selection means coupled to receive said selection control signals, said input data signals and said delayed data signals for furnishing a plurality of bundles of selected data signals, a plurality of filter means each coupled to receive,- one of said filtering mode control signals and one of said bundles of selected data signals for furnishing signals filtered in accordance with said one filtering mode control signal, and combining means coupled to said plurality of ilter means for combining said filtered signals to supply output signals.

22. A filter arrangement as claimed in Claim 21, wherein said memory means comprise a plurality of memory units and wherein said data input means comprise a plurality of data input connections, and means for selectively coupling said data input connections and said memory units.

23. A filter arrangement as claimed in Claim 21, wherein said control means have a combination control output for furnis- hing combination control signals, and wherein said combining means are coupled to receive said combination control signals for combining said filtered signals in response to said combina¬ tion control signals.

24. A filter arrangement as claimed in Claim 21, wherein said control means have a delay control output for furnishing delay control signals, and wherein said filter means comprise delay means for supplying said filtered signals delayed in response to said delay control signal.

25. A filter arrangement as claimed in Claim 21, wherein said control means has an output for supplying control signals delayed by a delay corresponding to filter processing delay imposed by said filter means.

26. A decoder apparatus comprising input means for recei¬ ving input signals, temporal filter means coupled to said input means and including a field memory having an input coupled to said input means, an output ^*ttf said temporal filter means being coupled to an output of said field memory for furnishing delayed signals, deshuffle means having a first input coupled to said input means, a second input coupled to said output of said temporal filter means, a first output for furnishing deshuffled input signals, and second outputs for furnishing first deshuf- fled delayed signals, second and third field memories coupled to said second outputs for furnishing second and third deshuffled delayed signals, and decoder means for decoding said deshuffled input signals and said first, second and third deshuffled delay¬ ed signals to furnish decoded signals.

27. Decoder apparatus, comprising input means for receiving input signals, first memory means for receiving said input signals and furnishing once delayed signals at a first memory output, second memory means receiving said once delayed sigals only during alternate ones of consecutive predetermined time intervals, third memory means receiving said once delayed sig¬ nals only during the remaining ones of said consecutive time intervals, and output means coupled to said first, second and third memory means, for furnishing output signals comprising, in parallel once, twice and three times delayed input signals.

28. Decoder apparatus as claimed in Claim 16, wherein said output means is further coupled to said input means and said output signals further comprise undelayed input signals.

29. HDTV decoder apparatus, comprising

- means for receiving standard television signals having a standard line time substantially equal to a multiple of an HDTV line time, and a sampling rate substantially equal to a submul- tiple of an HDTV sampling rate,

- compression means connected to said receiving means for com¬ pressing said standard television signals to said HDTV line time, and furnishing compressed line samples at a compressed line sampling rate, and

- interpolating means connected to said compression means for interpolating samples between said compressed line samples a nd furnishing and output signal having said HDTV line time and sampling rate.

30. HDTV decoding apparatus as claimed in Claim 29, wherein said standard television signal has a standard aspect ratio less than the HDTV aspect ratio, and wherein said compression means compresses said standard television signals by a compression factor equal to the ratio of said HDTV aspect ratio to said standard aspect ratio, multiplied by said multiple of said TV line time.

31. HDTV decoding apparatus as claimed in Claim 29, wherein said interpolating means comprises a multipurpose integrated circuit as claimed in 12.