EP0464778B1 - Frankiermaschine mit einer als Schnittstelle dienenden gedruckten Schaltung - Google Patents

Frankiermaschine mit einer als Schnittstelle dienenden gedruckten Schaltung Download PDF

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Publication number
EP0464778B1
EP0464778B1 EP91110957A EP91110957A EP0464778B1 EP 0464778 B1 EP0464778 B1 EP 0464778B1 EP 91110957 A EP91110957 A EP 91110957A EP 91110957 A EP91110957 A EP 91110957A EP 0464778 B1 EP0464778 B1 EP 0464778B1
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EP
European Patent Office
Prior art keywords
microprocessor
switches
encoders
integrated circuit
motor
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EP91110957A
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English (en)
French (fr)
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EP0464778A1 (de
Inventor
Bernard Vermesse
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Quadient Technologies France SA
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Neopost Technologies SA
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    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
    • G07B17/00193—Constructional details of apparatus in a franking system
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
    • G07B17/00193—Constructional details of apparatus in a franking system
    • G07B2017/00258—Electronic hardware aspects, e.g. type of circuits used

Definitions

  • the invention relates to a machine for franking mail, printing stamps by counting the values of these stamps.
  • a so-called main card notably includes the microprocessor and a first part of the second interface.
  • a so-called interface card comprises: the first interface, the position encoders, the switches, and a second part of the second interface.
  • the two cards are connected by connectors with five contacts corresponding respectively to: a conductor for the reference potential, a conductor for the supply voltage of the electronic circuits, a specialized conductor for a motor control signal, and two conductors constituting a serial transmission bus, according to the I2C protocol for example.
  • the microprocessor is the master of transactions between the two cards.
  • One bus conductor transmits clock pulses clocking the transmission, while the other conductor transmits binary data, in either direction.
  • This bus transmits the commands controlling the scanning and the transmission of the values translated by the encoders, and of the states of the switches; and transmits data in response to these orders.
  • the first interface has two general purpose integrated circuits available commercially: a serial input-output circuit, and a decoder. These circuits make it possible to scan a matrix of conductors in which the encoders and the switches establish variable links between rows and columns. The lack of available outputs on these circuits leads to the use in addition of twelve diodes, to connect six outputs of the decoder to the twelve columns of the matrix without harming the independence of these columns.
  • the second interface which switches the power supply to the motor, comprises: an address decoder and a locking register, located on the main card; and comprises: a power transistor and a preamplifier transistor, located on the interface card.
  • the specialized conductor for controlling the motor carries a direct voltage, supplied by an output of the latching register and directly controlling the preamplifier transistor.
  • the interface card of a machine according to the prior art has the advantage of comprising only integrated circuits for general use, commercially available. Their number is small (two) but it is desirable to reduce it to reduce the cost of manufacturing the machine (cost of the printed circuit, assembly, control). It is not possible to reduce the number of integrated circuits by using a single integrated circuit which is commercially available, since there is no general purpose integrated circuit which can fulfill all the functions of the first interface and, a fortiori, fulfill part or all of the functions of the second interface. We must therefore consider the realization of an integrated circuit specific to this application (ASIC). It is possible to integrate into a single integrated circuit: the twelve diodes, the serial input-output circuit, and a decoder. The new machine would then have the same performance and the same disadvantages as the machine according to the prior art, except that the bulk and the cost would be reduced.
  • ASIC integrated circuit specific to this application
  • the machine according to the prior art has the following drawbacks. To scan the value translated by each encoder, it is necessary to send, from the microprocessor to the input-output circuit, a write order consisting essentially of two bytes; then send, from the microprocessor to the input-output circuit, a read order consisting essentially of a byte; and finally, to send, from the input-output circuit to the microprocessor, a byte of data. There is therefore transmission, in one direction or the other, of four bytes to examine the state of a single encoder.
  • each order sent by the microprocessor is preceded by a signal characteristic of the start of a transaction, and it is followed by a signal characteristic of an end of transaction.
  • the scanning of four encoders requires four scans triggered by four orders from the microprocessor.
  • the manual control switches constitute two groups, separated from the encoders, and which are the subject of a fifth and a sixth scan, and of the transmission of a fifth and a sixth byte of data. Finally, the scanning of all the encoders and switches is followed by putting all the columns of the matrix to rest, consisting in configuring the input-output circuit by a write order such that none of the columns of the matrix is only scanned by the decoder. In total, to scan four encoders and four switches, twenty six bytes are transmitted on the data conductor.
  • a scan is commanded every 10 milliseconds.
  • the minimum admissible period for the bus clock clocking the transmission is 10 microseconds
  • the minimum duration necessary to scan four switches and four encoders is 2.5 milliseconds.
  • the microprocessor therefore devotes a quarter of its operating time to carrying out this scan.
  • a non-negligible current flows in the columns of the matrix corresponding to an encoder, during the scrutiny of it. Consequently, the duration of all the scans has a direct effect on the quantity of energy taken from the power supply device of the electronic circuits of the machine. Incidentally, this scanning mode requires storing a relatively complex program in the microprocessor program memory.
  • the machine according to the prior art also has a drawback arising from the lack of outputs on the decoder.
  • the use of diodes to connect the columns of the matrix to the outputs of the decoder has the effect of reducing by 0.7 volt approximately the noise immunity of the ports of the input-output circuit, when they are configured as inputs .
  • the fact of transmitting by two different procedures the commands controlling the motor and the commands controlling the scanning leads to adding a specialized conductor to connect the two cards of the machine, which increases by one the number of contacts of the connectors connecting the two cards.
  • the main card has a size and a cost increased by the presence of the address decoder and the locking register forming part of the second interface.
  • the machine according to the prior art has a drawback arising from the lack of inputs on the input-output circuit.
  • This lack of entries leads to limiting the number of rows in the matrix to five.
  • each coder constitutes a sub-matrix comprising five lines, all the lines of the matrix are occupied when a coder is scanned. Consequently, the switches are grouped into two groups, independent of the encoders. The states of the switches are transmitted in two bytes distinct from the four bytes transmitting the values translated by the four coders. There is therefore a transmission of six data bytes which each contain a maximum of four useful bits and stuffing bits. This poor filling of the data bytes contributes to increasing the transactions between the interface card and the main card, by increasing the number of data bytes.
  • the object of the invention is to provide a franking whose input-output interface card includes a single integrated circuit, specific to this application; and which does not have the disadvantages of the machine according to the prior art.
  • the machine thus characterized no longer comprises, on the main card, an address decoder and a lock register for the switching commands of the motor supply, thanks to the fact that these commands are routed by the same bus and the same specific integrated circuit that the scanning and transmission orders.
  • the creation of a specific integrated circuit is an opportunity to integrate at least part of the switching amplifier. This characteristic therefore makes it possible to reduce the size of the connector and the number of components beyond what a simple integration of the interfaces according to the prior art would allow in a specific integrated circuit.
  • the second interface is connected to the first interface, inside said specific integrated circuit, for transmitting to the microprocessor, at the same time as bits representing the values translated by the encoders, and representing the states of the switches, a bit indicating the engine condition: running or stopped.
  • the machine thus characterized, allows the microprocessor to verify the correct execution of the switching commands of the motor supply, without the slightest additional component having to be added, thanks to an internal connection to the specific circuit and thanks to the use of means already present, in the specific integrated circuit, to transmit the values translated by the encoders and transmit the states of the switches.
  • This sequencer gives the interface card a certain autonomy, by making it possible to carry out a long phase of scanning and transmission or to carry out a command of the motor, following a single order sent by the microprocessor.
  • the specific integrated circuit for a franking machine comprising coders and switches making variable connections between rows and columns of a matrix of conductors, has outputs in number at least equal to the number of columns of the matrix, and which are respectively connected to said columns.
  • the machine thus characterized does not require diodes mounted respectively in series with the conductors constituting the columns of the matrix, thanks to the fact that each column is connected to an output of the specific integrated circuit, independent of the others.
  • this characteristic increases by 0.7 volt the noise immunity of the inputs of the specific circuit which are connected to the conductors constituting the lines of the matrix.
  • the specific integrated circuit comprises a number of inputs connected to matrix lines, which is greater than the number of matrix lines to which the encoders are connected; at least one matrix line being connected only to manual control switches, the encoders and switches being connected in groups, each group having a number of outputs at most equal to the number of lines of the matrix, the outputs of each group being connected respectively to the rows of the matrix.
  • This specific integrated circuit structure allows the scanning phase and the transmission phase to be carried out more optimally, by increasing the number of useful bits in each byte of data sent to the microprocessor.
  • the motor 10 is connected to the interface card by two terminals 11 and 12.
  • a transformer, not shown, which is not mounted on the interface card, supplies the circuit 9 by two terminals 13 and 14.
  • the rest of the interface card is supplied by a DC voltage supplied by the main card, which is not represented.
  • the interface card is connected to the main card by a connector 30 with five contacts.
  • a contact noted CDM specialized for the control of the motor, provides a binary signal which directly controls the transistors 7 and 8 through the resistor R6.
  • a contact marked SDA transmits data in serial form, from the microprocessor to an input of circuit 6, and vice versa.
  • a contact noted SCL transmits a clock signal from the microprocessor to circuit 6, to clock the data transmission in both directions.
  • a contact marked VDD provides a supply voltage of + 5V.
  • a contact rated VSS brings a reference potential.
  • Encoders 1 to 4 and switches SW1 to SW4 make variable connections between five rows and twelve columns of a matrix of conductors, each encoder constituting a sub-matrix comprising five rows and two columns. Each encoder has five terminals connected respectively to the five rows of the matrix and has two terminals connected to two columns of the matrix. Each encoder has two movable contacts which establish a connection between the first of the two columns corresponding to the encoder, and one of the five lines; and a link between the second of the two columns and another line among the five lines.
  • Each switch SW1 to SW4 possibly establishes a connection between a row of the matrix and a column.
  • the five lines of the matrix are connected to the VDD contact providing a voltage of + 5V, respectively by five resistors R1 to R5 each having a value of 2.7 kilo-ohms.
  • the scrutiny of one of the coders consists in connecting the two columns corresponding to this coder, to a potential close to the reference potential and to determining the potential on the five lines of the matrix.
  • Each coder codes a digit, from 0 to 9, by providing on the five lines of the matrix a binary word comprising two low levels and three high levels, when it is scanned.
  • Each switch SW1 to SW4 is scanned by connecting the corresponding column to a potential close to the reference potential. If the switch is closed, the row to which the column is connected is at the low level. Otherwise, this line is at the high level.
  • the serial input-output circuit 6 has eight ports, denoted P0 to P7, which can be individually configured either as input or as output, by a write order sent by the microprocessor. It also has three inputs: A0, A1, A2, used to define the address of circuit 6 as a slave of the microprocessor. In this example, these three inputs are linked to the reference potential.
  • the ports P0 to P4 are connected to the five lines of the matrix, while the ports P5, P6, P7 are connected to three inputs: A, B, C of the decoder 5.
  • the decoder 5 has eight complemented outputs, denoted Y0 to Y7. Each of these outputs is constituted by a CMOS door. Only one of the eight outputs is low at all times. It is a function of the value of the binary word applied to inputs A, B, C.
  • the outputs Y0 to Y5 are used to scan the twelve columns of the matrix, while the outputs Y6 and Y7 are not connected. One of these two outputs Y6, Y7 is selected when the microprocessor commands an absence of scanning on all the encoders and all the switches, at the end of a scanning sequence.
  • Each of the outputs Y0 to Y5 simultaneously scans two columns of the matrix by means of two diodes making it possible to maintain the independence of these two columns regardless of the state of the contacts possibly connecting these two columns to the rows of the matrix.
  • the switches SW1 to SW4 are scanned two by two.
  • the interface card has twelve diodes D1 to D12 to fulfill this function. It appears that each of these diodes increases by 0.7V the potential corresponding to the low level of the lines of the matrix, by adding their voltage drop of 0.7 V to a voltage drop of the order of 0.4V existing between the drain and the source of the transistor constituting each of the outputs Y0 to Y5 of the decoder 5.
  • the diodes D1 to D12 increase the number of components of the interface card; as well as the presence of the two transistors 7 and 8.
  • the separation of the motor control interface into a part located on the interface card and a part located on the main card, requires a connection between the two cards, by the contact noted CDM, which increases the number of connector 11 contacts by 25%.
  • a transaction begins when the microprocessor sends a start of transaction signal, consisting of a descent to the low level on the data conductor, SDA, while the clock conductor, SCL, is stable at the high level.
  • a transaction is completed when the microprocessor emits an end of transition signal, consisting of a rise to the high level of the data conductor, SDA, while the clock conductor, SCL, has a stable high level.
  • the microprocessor begins by configuring circuit 6, with a write operation. For example, to scan the encoder 4 translating the value of the digit of the units, the ports P0 to P4 are configured as inputs while the ports P5, P6, P7 are configured as outputs providing a binary word 000 so that the decoder 5 provides a low level on its output Y0 and high levels on its outputs Y1 to Y7, the output Y0 exciting the two columns of the encoder 4.
  • the microprocessor emits: a start signal, then a byte made up of the seven bits of the specific address of circuit 6, and of a read or write command bit; followed by a data byte which controls the configuration of ports P0 to P7.
  • the microprocessor checks that it receives an acknowledgment signal sent by the circuit 6, in the form of a low level, during the 9th clock period. Likewise, the microprocessor verifies that it receives an acknowledgment signal after having transmitted the data byte. Then he sends the end of transaction signal.
  • the microprocessor To read the logic levels on the five ports P0 to P4, the microprocessor then orders a read. To do this, it sends a transaction start signal, followed by a byte made up of the seven bits of the address specific to circuit 6, followed by the read-write bit indicating a read. Then it verifies that it receives an acknowledgment of receipt sent by the circuit 6, and consisting of a low level during the ninth clock period. It then receives a byte indicating the logical levels read on the ports P0 to P7, among which only the ports P0 to P4 are of interest. The microprocessor then emits an acknowledgment of receipt, then an end of transaction signal.
  • the assembly has the drawback of consuming a certain current during the whole duration of the scan, that is to say 2.6 milliseconds at least, every 10 milliseconds. In this exemplary embodiment, this current has an intensity of 3 milliamps during the scanning. The average power consumed is relatively high because it is directly proportional to the duration of the scan.
  • the interface card is connected to the motor 27 by two terminals 17 and 18, and to a supply transformer, not shown, by two terminals 19 and 20 which are connected to two inputs of the supply circuit of the circuit 26.
  • the terminal 17 is connected to the collector of transistor 28 while terminal 18 is connected to an output of the supply circuit 26.
  • the interface card is also connected to a main card, carrying a microprocessor 16, by a connector 29.
  • the main card is represented briefly by its microprocessor 16 and by a connector 15 which fits into the connector 29.
  • This card notably includes a supply circuit, not shown, supplying a voltage of + 5V.
  • the connector 29 has only four contacts.
  • a contact marked SDA is connected to a conductor transmitting data in serial form, in both directions.
  • a contact denoted SCL is connected to a conductor transmitting a clock signal sent by the microprocessor 16 during the transactions.
  • a contact marked VDD receives a continuous supply voltage of + 5V.
  • a contact noted VSS is connected to a conductor bringing the reference potential.
  • the specific integrated circuit 25 has two connected inputs respectively to the two contacts SDA and SCL of the connector 29, to communicate with the microprocessor 16. It further comprises: six inputs denoted E2 to E7 which are respectively connected to six lines of a matrix of conductors; an output marked MOT which is connected to the base of transistor 28 by a resistor R13; and outputs: UNI0, UNI1, UNI2, DIZ0, DIZ1, DIZ2, CENT0, CENT1, CENT2, MI0, MI1, MI2, which are respectively connected to the twelve columns of the matrix.
  • Each of the coders 21 to 24 has two terminals connected respectively to two columns of the matrix; and comprises five second terminals connected respectively to five lines of the matrix, the sixth line being independent of the encoders but being common to the four switches SW′1 to SW′4.
  • Each of these switches is connected to a separate column, and establishes a connection between this column and the sixth row of the matrix.
  • the six lines of the matrix are connected to the supply voltage, respectively by six resistors R7 to R12 each having a value of 1.2 kilo-ohms.
  • the diagram does not include any diodes since each column of the matrix is scanned by an independent output, UNI0, ..., MI2, of the specific integrated circuit 25. This eliminates the drawbacks of cost, size, and reduction immunity to noise, which were due to diodes D1 to D12 of the interface card described above.
  • the outputs UNI0 to MI2 are constituted respectively by transistors of the MOS type with open drain, while the output MOT is made up of a complementary pair of transistors of the MOS type.
  • the specific integrated circuit 25 has essentially three functions, triggered respectively by three unique orders sent by the microprocessor 16 according to the I2C protocol: a single order to control the starting of the engine; a single command to order engine shutdown; and a single command to control a scan of all encoders and all switches.
  • FIG. 3 represents a timing diagram of the transaction between the microprocessor 16 and the circuit 25, constituting an order to control the motor, which replaces the connection by the conductor noted CDM in the interface card according to the prior art, described previously.
  • the transaction begins with a start signal, consisting of a passage at the low level of the SDA conductor, while the SCL conductor is stable at the high level.
  • the microprocessor 16 then sends an address of seven bits, specific to the integrated circuit 25, then a read-write bit, noted R / W, during in the eighth clock period. In this case, the R / W bit is a write bit, consisting of a low level.
  • the circuit 25 responds with an acknowledgment of receipt, denoted ACK, constituted by a low level on the conductor SDA during the ninth period of the clock sent on the conductor SCL.
  • ACK acknowledgment of receipt
  • the microprocessor 16 When the microprocessor 16 has detected this acknowledgment of receipt, it sends an eight-bit control word which has the hexadecimal value 6A or EA to command a starting of the motor; or which has a hexadecimal value other than 6A and EA to stop the engine.
  • the circuit 25 sends an acknowledgment, denoted ACK, constituted by a low level on the conductor SDA for the duration of the ninth clock period, counted from the first bit of the word ordered.
  • the microprocessor 16 sends an end of transaction signal, constituted by a high level transition on the conductor SDA while the conductor SCL has a stable high level.
  • the circuit 25 imposes a voltage close to + 5V or 0V on its MOT output, depending on whether the order is to start or stop the supply to the motor 27.
  • FIG. 4 represents a timing diagram of the transaction between the circuit 25 and the microprocessor 16, constituting the order of scanning and transmission, then the actual transmission of the values translated by the encoders 21 to 24, and of the state of the switches SW '1 to SW'4.
  • the microprocessor 16 sends a single order which consists first of all of a transaction start signal, then of the address specific to the integrated circuit 25, then of an R / W read-write bit. In this case, it is a read bit consisting of a high level on the SDA conductor for the duration of the eighth clock period on the SCL conductor.
  • the response of circuit 25 is: an acknowledgment, ACK, consisting of a level low on the SDA conductor during the ninth period of the clock; then a first data byte consisting of bits B7, B6, B5, B4, B3, B2, M, and a stuffing bit.
  • bits B7 to B2 represent respectively: the states of the inputs E7 to E2 when the encoder 21 and the switch SW′1 are scanned by setting the outputs MI0, MI1, and MI2 to the low level.
  • Bit M represents the switching state of the motor supply.
  • the microprocessor 16 responds briefly by sending an acknowledgment, ACK ′, constituted by a bit at the low level on the conductor SDA during the ninth clock period on the conductor SCL, counted from the first data bit.
  • ACK ′ acknowledgment
  • circuit 25 When circuit 25 has received this acknowledgment ACK ′, it sends a second data byte representing the state of the inputs E7 to E2 when the encoder 22 and the switch SW'2 are scanned by setting the outputs CENT0 to low , CENT1, CENT2; and representing the state of the switching of the motor supply.
  • the microprocessor 16 responds briefly by sending an acknowledgment ACK ′. After receiving this acknowledgment ACK ′, circuit 25 sends a third data byte representing the state of the inputs E7 to E2 when the encoder 23 and the switch SW′3 are scanned by setting the outputs DIZ0 to low, DIZ1, DIZ2; and representing the state of the switching of the motor supply.
  • the microprocessor 16 responds with an acknowledgment of receipt ACK ′. After receiving this acknowledgment ACK ′, circuit 25 sends a fourth data byte representing the state of the inputs E7 to E2 when the encoder 24 and the switch SW′4 are scanned by setting the outputs UNI0 to low. , UNI1, UNI2; and representing the state of the switching of the motor supply.
  • the microprocessor 16 responds by sending an acknowledgment of receipt ACK ′. Then, as there is no more data to transmit, it sends an end of transaction signal. The transaction has five bytes instead of twenty six.
  • the number of inputs E2, ..., E7 connected to the lines of the matrix has been increased compared to the number of ports P0, ..., P4 configured as inputs, in the interface card according to the prior art.
  • the number of rows in the matrix has been increased from five to six.
  • the encoders and switches are scanned by group, each group comprising an encoder and a switch, in this example. This makes it possible to minimize the number of bytes of data to be transmitted to the microprocessor, since each byte of data contains six useful bits, instead of five. In this example, four bytes are enough to transmit the data resulting from the scan.
  • the transaction therefore comprises five bytes, instead of seven if the switches constituted two separate groups of coders, as was the case in the prior art.
  • the scanning lasts less than 0.5 milliseconds, which is approximately 5 times less than in the example of machine according to the prior art, described above.
  • the scanning of the state of an encoder and of a switch does not last during the duration of transmission of a byte, but in fact only lasts during the duration of a clock period preceding this transmission, that is to say lasts only 10 microseconds.
  • the encoders therefore consume current only for 4 times 10 microseconds, ie 0.04 milliseconds instead of 2.6 milliseconds in the example of machine according to the prior art. The energy consumption in the interface card is therefore significantly reduced.
  • resistors R7 to R12 have a value of 1.2 kilo-ohms instead of 2.7 kilo-ohms. This reduction in resistance makes it possible to approximately double the intensity of the current passing through each contact, while nevertheless benefiting from a significant reduction in the energy consumption in the interface card.
  • the scan time is reduced by a factor of five: 0.5 milliseconds instead of 2.6 milliseconds, which frees up time of microprocessor calculation.
  • the program controlling the microprocessor is very light since a single command is sufficient to scan all the encoders and switches. Consequently, the program requires less memory capacity, which frees up space for other applications, or makes it possible to reduce the size of this memory.
  • the clock signal supplied by the conductor SCL constitutes a clock signal denoted H1, after filtering by the filter 63. It is applied to: a clock input of register 60; a clock input of the detector 67; and a clock input of the counter 68.
  • the oscillator 62 supplies a clock signal H2 to the two filters 61 and 63, and to a clock input of the sequencer 69.
  • the data signal supplied by the conductor SDA is filtered by the filter 61 then is supplied, on the one hand, to a data input of the detector 67 and, on the other hand, to a first input of the AND gate 64.
  • An output of the detector 67 is connected to an input of the sequencer 69 to supply it with a logic signal throughout the duration of a transaction.
  • An output of the sequencer 69 is connected to a second input of the AND gate 64, and an output of the latter is connected to a serial input of the circuit 60.
  • the register 60 is loaded in series, by validating the AND gate 64, to load an address received or load a motor control word, at the rate set by the clock H1.
  • the register 60 has seven stages having seven parallel outputs connected respectively to seven inputs of the decoder 65 and to seven inputs of the decoder 66.
  • the output of the first stage of register 60 is connected to an input of sequencer 69. This output provides the R / W bit for read-write command, or the acknowledgment bit ACK ′, during certain periods of the clock. H1.
  • the register 60 has seven parallel inputs which are respectively connected to the outputs of the AND gates 31 to 37.
  • a first input of each AND gate 31 to 36 constitutes respectively one of the inputs E7 to E2 of the circuit 25.
  • a first input of the AND gate 37 is connected to the output of flip-flop 81 memorizing the state of the switching of the power supply to the motor, by a link marked EM, internal to the specific integrated circuit 25.
  • a second input from each of the doors 31 to 37 is connected to an output of the sequencer 69 to control the loading of seven bits in parallel in the register 60.
  • the decoder 65 and the decoder 66 each have an output connected respectively to an input of the sequencer 69.
  • the decoder 65 recognizes the address specific to the integrated circuit 25, it provides a signal at input of the sequencer 69.
  • the register 60 has an output serial connected to a first input of the AND gate 59. A second input of this gate is connected to an output of the sequencer 69, which controls a serial transmission to the microprocessor, and an output of this gate 59 is connected to the SDA conductor.
  • the counter 68 has: a clock input connected to the output of the filter 63; a validation input connected to an output of the sequencer 69; a first output connected to an input of the sequencer 69 to supply it with a pulse during the duration of each eighth period of the clock H, which corresponds to the reception of an R / W bit; a second output connected to an input of the sequencer 69 and to a first input of the gate ET72.
  • the counter 68 is a counter by nine which counts the pulses of the clock signal H1. Its second output provides another clock signal denoted H3 consisting of a pulse for each ninth pulse of the clock signal H1. Each pulse of the clock signal H3 therefore corresponds to the time interval reserved for the emission of an acknowledgment signal ACK by the circuit 25 or the reception of a reception signal ACK ′ sent by the microprocessor 16 .
  • a second input of the AND gate 72 is connected to an output of the sequencer 69.
  • the output of the gate 72 is connected to a clock input of the counter 71.
  • the counter 71 is a counter by five which counts five periods of the clock H3 to scan four groups successively, each group consisting of an encoder and a switch; and which has a fifth period of the H3 clock to return to a absence of scrutiny.
  • the counter 71 has three outputs connected respectively to three inputs of the decoder 70. The latter has five outputs of which only one is selected at a time, according to the value of the binary word applied to the three inputs. These outputs are noted S0, ..., S4 and are selected in this order when the counter 71 is incremented.
  • the output S0 is connected in parallel to the inputs of the output interfaces 49, 50, 51 which correspond respectively to three outputs MI0, MI1, MI2, of circuit 25.
  • the outputs S1, S2, S3 each control a group of three interfaces Release.
  • the output S4 is connected to a sequencer input 69. It supplies a logic signal, noted END, indicating to it the end of the scanning of the four groups of encoders and switches, in order to bring the sequencer 69 back to a rest phase.
  • the initialization device 80 has an output connected to an initialization input of the sequencer 69 and to an initialization input of the flip-flop 81, to put the sequencer 69 in a rest phase, and to cut the power supply to the motor 27 when the franking machine is switched on.
  • the flip-flop 81 has a data input connected to an output of the sequencer 69, for storing a start or stop order.
  • the output of the flip-flop 81 is connected to an input of the preamplifier 82.
  • the output of the flip-flop 81 is also connected, inside the integrated circuit 25, to a first input of the AND gate 37.
  • the second input of the door AND 37, as well as the second inputs of AND gates 31 to 36 are connected to an output of sequencer 69 which commands the parallel loading of a word of seven bits of data in register 60, for their transmission in the form of series .
  • the sequencer 69 is in a rest phase following an initialization by the device 80, at power-up; or following a scan completion signal supplied by the output S4 of the decoder 70; or after the execution of a start-up order or engine shutdown; or following the detection of an end of transaction signal, by the detector 67.
  • the sequencer 69 goes into an activation phase as soon as a start of transaction signal is detected by the detector 67. It then commands the AND gate 64 to load into the register 60 the bits transmitted by the microprocessor 16. It validates the counter 68. At the end of the seventh clock pulse H3, the signal supplied by the output of the address decoder 65 is stored by the sequencer 69. If this signal does not indicate that the address specific to circuit 25 has been detected, the sequencer 69 blocks the transmission of an ACK acknowledgment, then it goes into the rest phase at the end of the ninth clock pulse H3. Otherwise, it sends an acknowledgment of receipt ACK on the driver SDA by imposing a low level, during the ninth period of the clock H3. Then, it goes into the scanning and transmission phase, or else into the motor control phase, depending on the value of the R / W bit, which is supplied to it by the output of the first stage of register 60 during the eighth period of l 'clock H3.
  • the sequencer 69 then enters a motor control phase.
  • the motor control word is loaded into circuit 60 and is then decoded by circuit 66 which supplies a logic signal to the sequencer 69. If the control word has the hexadecimal value 6A or EA, the decoder 66 provides a high level which corresponds when the engine is started. If the control word has another value, the decoder 66 provides a low level which corresponds to a shutdown.
  • the output of sequencer 69 which is connected to a control input of flip-flop 81 writes the value of this logic signal there. If it is a start command, the preamplifier 82 supplies the output MOT with a current to saturate the power transistor 28.
  • the sequencer 69 After decoding the word controlling the motor, the sequencer 69 sends an acknowledgment of receipt ACK to the microprocessor, by imposing a low level on the conductor SDA, by means of the AND gate 59; then returns to a rest phase.
  • the engine remains in works if it has been started or remains stationary if it has just been stopped.
  • the decoder 70 selects a group of three output interfaces, for example 40, 41, 42, to bring three columns of the matrix to a potential close to the reference potential.
  • the sequencer 69 validates the gates 31 to 37, 72, and 59, to load seven bits of data in parallel into the register 60 then transmit them in series on the conductor SDA, with an eighth bit constituting a stuffing.
  • the microprocessor 16 sends an acknowledgment ACK ′, consisting of a high level, during the clock period which follows the eight transmission periods of a data byte.
  • This acknowledgment is loaded into the first stage of the register 60 under the control of each ninth pulse of the clock H1.
  • the output of the first stage provides this acknowledgment of receipt ACK ′ to the sequencer 69.
  • the end signal supplied by the decoder 70 causes the sequencer 69 to return to the rest phase. If the circuit 25 does not receive an acknowledgment of receipt ACK ′ for the first, or the second, or the third byte of data, the sequencer 69 returns to a rest phase and waits for a new order starting with a start signal.
  • the transmission of the state of the motor from circuit 25 to the microprocessor makes it possible to achieve a very reliable control of the motor, since a transmission error, affecting the motor control word, is detected quickly, during the next scan, thanks to the bit M which is retransmitted to the microprocessor.
  • the number of values (6A or EA) of the control word triggering the starting of the engine is much lower than the number of values (two hundred and fifty six) causing the engine to stop. A disruption of the transmission is therefore much more likely to cause an engine shutdown, rather than an unexpected start-up.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Control By Computers (AREA)
  • Electronic Switches (AREA)
  • Control Of Stepping Motors (AREA)

Claims (6)

  1. Frankiermaschine, die Freistempel unter Buchung der Werte dieser Freistempel aufdruckt und die aufweist:
    - einen Motor (27) und Druckräder, die erhabene Ziffern tragen, zum Drucken eines Freistempels,
    - einen Mikroprozessor (16) zum Steuern des Motors und zum Buchen des Werts jedes Freistempels,
    - Stellungskodierer (21 bis 24), die an je ein Druckrad zum Übersetzen der Werte der Ziffern als Freistempel in Form von binären Worten angeschlossen sind,
    - Handsteuerschalter (SW′1 bis SW′4),
    - eine erste Schnittstelle, die durch Befehle des Mikroprozessors angesteuert wird, um die durch die Kodierer und die Zustände der Schalter übersetzten Werte abzufragen und an den Mikroprozessor zu übertragen,
    - eine zweite Schnittstelle, die durch Befehle des Mikroprozessors angesteuert wird, um die Stromversorgung des Motors ein- und auszuschalten,
       dadurch gekennzeichnet, daß die erste Schnittstelle eine speziell für diese Anwendung konzipierte integrierte Schaltungslogik aufweist, die Einrichtungen (31 bis 72) aufweist, um im Anschluß an den Empfang eines vom Mikroprozessor (16) ausgesendeten einzelnen Befehls die von allen Kodierern (21 bis 24) übersetzten Werte sowie die Zustände aller Schalter (SW′1 bis SW′4) der Maschine abzufragen und an den Mikroprozessor (16) zu übertragen.
  2. Maschine nach Anspruch 1, dadurch gekennzeichnet, daß die zweite Schnittstelle in die gleiche spezielle, integrierte Schaltung (25) integriert ist wie die erste Schnittstelle und daß sie gemeinsam mit der ersten Schnittstelle aufweist:
    - einen Bus (SDA, SCL), der an den Mikroprozessor (16) angeschlossen ist,
    - Mittel (61 bis 63) zum Filtern der vom Mikroprozessor (16) gesandten Signale,
    - Mittel (60) zum Umwandeln der in Reihe empfangenen binären Daten in parallele Form,
    - Mittel (65) zum Dekodieren einer Adresse,
    - Mittel (67) zum Erfassen eines Operations-Anfangssignals und eines Operations-Endesignals, das vom Mikroprozessor übermittelt wird, und daß die zweite Schnittstelle ihrerseits aufweist:
    - Mittel (81) zum Speichern des Schaltzustands des Motors,
    - mindestens einen Teil (82) eines Schaltverstärkers, um die Stromversorgung des Motors (27) umzuschalten.
  3. Maschine nach Anspruch 2, dadurch gekennzeichnet, daß die spezielle integrierte Schaltung (25) eine innere Verbindung (EM) aufweist, die die zweite Schnittstelle mit der ersten Schnittstelle verbindet, um an den Mikroprozessor zusammen mit Bits (B2, .. B7), die die von den Kodierern (21 bis 24) übersetzten Werte und die Zustände der Schalter (SW′1 bis SW′4) darstellen, ein Bit (M) zu übertragen, das den Schaltzustand des Motors (27) (Betrieb oder Stillstand) anzeigt.
  4. Maschine nach Anspruch 2, dadurch gekennzeichnet, daß die erste und die zweite Schnittstelle weiter gemeinsam in der speziellen Schaltung (25) eine Folgeschaltung (69) aufweisen, die Mittel zum Speichern von vier Betriebsphasen aufweist, die sich gegenseitig ausschließen:
    - eine Ruhephase im Anschluß an jedes Einschalten der Maschine, oder im Anschluß an einen Befehl zur Rückkehr in den Ruhezustand, der von der Folgeschaltung selber oder vom Mikroprozessor ausgegeben wird,
    - eine Aktivierungsphase, falls die spezielle integrierte Schaltung (25) ein Operations-Anfangssignal empfängt, wobei diese Phase die Erfassung einer Adresse, die der speziellen integrierten Schaltung eigen ist, und eines Bits ermöglicht, das entweder einen Befehl zum Abfragen und zum Übertragen der von den Kodierern übersetzten Werte und der Zustände der Schalter oder einen Befehl zur Umschaltung der Stromversorgung des Motors anzeigt,
    - eine Abfrage- und Übertragungsphase, die auf eine Aktivierungsphase folgt, falls die spezielle integrierte Schaltung (25) im Anschluß an ihre Adresse ein Bit empfängt, das einen Befehl zum Abfragen und Übertragen der von den Kodierern übersetzten Werte sowie der Schaltzustände der Schalter anzeigt, wobei auf diese Phase eine Rückkehr zur Ruhephase folgt,
    - eine Phase zum Steuern des Motors (27), die auf eine Aktivierungsphase folgt, falls die spezielle integrierte Schaltung (25) im Anschluß an ihre Adresse ein Bit empfängt, das einen Befehl zum Umschalten der Stromversorgung des Motors (Betrieb oder Stillstand) anzeigt.
  5. Maschine nach Anspruch 1, die Kodierer (21 bis 24) und Schalter (SW1 bis SW4) aufweist, welche veränderliche Verbindungen zwischen Zeilen und Spalten einer Leitermatrix herstellen, dadurch gekennzeichnet, daß die spezielle integrierte Schaltung (25) Ausgänge (UNI1, UNI2, ...) aufweist, deren Anzahl mindestens der Anzahl der Spalten der Matrix entspricht und die je mit den einzelnen Spalten verbunden sind.
  6. Maschine nach Anspruch 5, dadurch gekennzeichnet, daß die spezielle integrierte Schaltung (25) eine Anzahl von Eingängen aufweist, die mit den Matrixzeilen verbunden sind, wobei diese Anzahl größer als die Anzahl der Matrixzeilen ist, mit denen die Kodierer (21 bis 24) verbunden sind, wobei mindestens eine Matrixzeile nur mit den handbetätigten Schaltern (SW′1 bis SW′4) verbunden ist und die Kodierer (21 bis 24) und die Schalter (SW′1, ... SW′4) in Gruppen (21-SW′1, 22-SW′2, ...) verbunden sind, wobei jede Gruppe eine Anzahl von Ausgängen aufweist, die höchstens der Anzahl der Zeilen der Matrix entspricht, und wobei die Ausgänge jeder Gruppe jeweils mit den entsprechenden Zeilen der Matrix verbunden sind.
EP91110957A 1990-07-04 1991-07-02 Frankiermaschine mit einer als Schnittstelle dienenden gedruckten Schaltung Expired - Lifetime EP0464778B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9008489A FR2664407B1 (fr) 1990-07-04 1990-07-04 Machine a affranchir le courrier, comportant un circuit integre specifique constituant des interfaces.
FR9008489 1990-07-04

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EP0464778A1 EP0464778A1 (de) 1992-01-08
EP0464778B1 true EP0464778B1 (de) 1994-08-31

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US (1) US5267172A (de)
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2688930B1 (fr) * 1992-03-23 1995-06-16 Alcatel Satmam Dispositif de connexion sans contact electrique.
US5552991A (en) * 1993-12-09 1996-09-03 Pitney Bowes Inc. Control system for an electronic pastage meter having a programmable application specific intergrated circuit
US5483458A (en) * 1993-12-09 1996-01-09 Pitney Bowes Inc. Programmable clock module for postage metering control system
US5696685A (en) * 1994-07-06 1997-12-09 Pitney Bowes Inc. Control system for an electronic postage meter having a programmable print head controller
DE4445053C2 (de) * 1994-12-07 2003-04-10 Francotyp Postalia Ag Frankiermaschineninterne Schnittstellenschaltung
DE59710554D1 (de) * 1996-01-31 2003-09-18 Francotyp Postalia Ag Frankiermaschine
US5878234A (en) * 1996-09-10 1999-03-02 Sierra Wireless, Inc. Low power serial protocol translator for use in multi-circuit board electronic systems
US6134665A (en) * 1998-01-20 2000-10-17 Digital Equipment Corporation Computer with remote wake up and transmission of a status packet when the computer fails a self test
US7999596B2 (en) 2009-03-26 2011-08-16 Texas Instruments Incorporated Digital suppression of spikes on an 12C bus
US9763392B2 (en) 2010-04-09 2017-09-19 Edge Technology Heated spray system for frost protection
JP5225520B1 (ja) * 2012-03-02 2013-07-03 三菱電機株式会社 エンコーダ入力装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3692988A (en) * 1971-01-18 1972-09-19 Pitney Bowes Inc Parcel postage metering system
DE2361951A1 (de) * 1973-12-13 1975-06-19 Bbc Brown Boveri & Cie Datensammelsystem fuer fernwirkunterzentralen
US3904946A (en) * 1974-06-05 1975-09-09 Pitney Bowes Inc Feed back control system for a postage meter
FR2335002A1 (fr) * 1975-12-11 1977-07-08 Secap Machine a affranchir a comptage electronique
FR2346929A1 (fr) * 1976-03-31 1977-10-28 Forclum Force Lumiere Elect Installation de surveillance de capteurs
US4525785A (en) * 1979-10-30 1985-06-25 Pitney Bowes Inc. Electronic postage meter having plural computing system
CH667743A5 (de) * 1981-04-06 1988-10-31 Hasler Ag Vorrichtung zum einstellen einer frankiermaschine und verfahren zum betreiben der vorrichtung.
US4519048A (en) * 1982-12-08 1985-05-21 Pitney Bowes Inc. Postage meter system for communicating platen movement to a microprocessor to signal completion of printing
US4630210A (en) * 1984-10-04 1986-12-16 Pitney Bowes Inc. Microprocessor controlled d.c. motor for controlling a load
US4635205A (en) * 1984-10-04 1987-01-06 Pitney Bowes Inc. Microprocessor controlled d.c. motor for indexing postage value changing means
US4942394A (en) * 1987-12-21 1990-07-17 Pitney Bowes Inc. Hall effect encoder apparatus
US4897793A (en) * 1988-01-26 1990-01-30 Francotyp-Postalia Gmbh Configuration for a franking machine
GB8819647D0 (en) * 1988-08-18 1988-09-21 Alcatel Business Systems Franking machine
US5121327A (en) * 1989-10-18 1992-06-09 Pitney Bowes Inc. Microcomputer-controlled electronic postage meter having print wheels set by separate d.c. motors

Also Published As

Publication number Publication date
DE69103698T2 (de) 1994-12-15
US5267172A (en) 1993-11-30
FR2664407B1 (fr) 1992-09-11
FR2664407A1 (fr) 1992-01-10
EP0464778A1 (de) 1992-01-08
DE69103698D1 (de) 1994-10-06

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