Classifications

• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B19/00—Programme-control systems
  • G05B19/02—Programme-control systems electric
  • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
  • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
  • G05B19/0423—Input/output

Definitions

• the present invention relates to centralized management logic devices, that is to say devices which make it possible, according to different predefined data, to control different elements of an application, for example different elements of a machine tool in the mechanical industry such as sensors, actuators, various elements of a motor vehicle such as headlights, indicators, control elements, etc.
• centralized management devices comprising a programmable central unit, for example based on a microprocessor, which emits signals capable of controlling different elements.
• the object of the present invention is therefore to provide a logical device for centralized management of a plurality of elements to be managed, which overcomes most of the drawbacks mentioned above while allowing to obtain results identical to those which were obtained with the devices of the prior art.
• the present invention relates to a logical device for centralized management of a plurality of elements to be managed, characterized in that it comprises: a central management unit comprising two first and second input-output lines able to transmit and receive at least data messages comprising an address, control input means, a plurality of signal repeater means, each of the repeater means comprising two first and second input-output terminals and means input-output bypass of said signals, said repeater means
• SUBSTITUTE SHEET (RULE 26) being connected in series between their first and second input-output terminals to form a ring management circuit between two ends, the two said ends being respectively connected to the two first and second second input-output lines of said central unit, and a plurality of controllable automatic addressing means each connecting the bypass input-output means of a repeater means an element to be managed.
• FIG. 1 represents the block diagram of an embodiment of a centralized management logic device according to the invention
• FIG. 2 represents the block diagram of an embodiment of the repeater means entering into the constitution of the embodiment of the device according to FIG. 1,
• FIG. 3 represents the block diagram of an embodiment of the controllable automatic addressing means forming part of the embodiment of the device according to FIG. 1,
• FIG. 4 represents the block diagram of an embodiment of the central management unit entering into the constitution of the embodiment of the device according to FIG. 1
• FIG. 5 represents the block diagram of an embodiment of part of the logic module present in the block diagram of FIG. 4, corresponding to the control and command of the direction of propagation of the signals transmitted by the central unit,
• FIG. 6 represents an operating diagram explaining the implementation, in the device according to the invention, of the bursting and concatenation functions
• FIG. 7 represents the block diagram of an embodiment of another part of the logic module present in the block diagram of FIG. 4, corresponding to the functions "burst” and “concatenation” in association with a logic of control and ordered,
• FIG. 8 represents the block diagram of an embodiment of the means performing the "concatenation" function in accordance with the representation according to FIG. 7, and
• FIG. 9 represents the block diagram of an embodiment of the means performing the "bursting" function in accordance with the representation according to figure 7.
• FIGS. 1 to 9 show a same embodiment of a centralized management logic device. Consequently, the same references designate the same elements there, whatever the figure on which they appear.
• FIG. 1 represents the block diagram of an embodiment of a logic device according to the invention, for centralized management of a plurality of elements to be managed.
• This centralized management logic device comprises a central management unit 1 comprising two first 2 and second 3 input-output lines, control input means 4, a plurality of signal repeater means 5, 6, 7,. .., each of the repeater means comprising two first 8, 9, 10, ... and second 11, 12, 13, ... input-output terminals and bypass input-output means 14, 15, 16, ... signals.
• These repeater means are mounted in series with respect to each other between their first 8, 9, 10, ... and second 11, 12, 13, ... input-output terminals for forming a ring management circuit 17 between two ends 18, 1 respectively connected to the two first 2 and second 3 input-output lines of the central unit 1.
• the logical centralized management device further comprises controllable automatic addressing means 20, 21, 22 , ... each connecting the bypass input-output means 14, 15, 16, ... of a repeater means 5, 6, 7, ... to an element to be managed 23, 24, 25 , ....
• the central unit 1 has the function of delivering to one of its two input-output lines 2, 3 messages in the form of signals or signal trains such as, for example, series of bits "0" and "I".
• the constitution of these messages is adapted to the general configuration of the device. It can be broken down into two entities: a control entity which can be defined by a first field for addressing composed of "i" bits, a second field for the sub-address composed of "j" bits and a third field allowing to define the number of information contained in the messages and exchanged between the central unit 1 and the elements to be managed made up of "k" bits, and a data entity whose size depends on the message.
• the logic central management unit 1 is configured to send "go" messages so that they travel through the ring management circuit 17 from a first input-output line, for example its input-output line 2, towards the second, that is, its input-output line 3, the messages passing successively through the various repeater means 5, 6, 7, ... in this chronological order.
• the different addresses intended to identify the elements to be managed have increasing values, for example "1", “2", “3”, ... "N”, following the chronological order of the repeater means 5, 6, 7, ... in the direction of rotation on the ring management circuit 17, going from the input-output line 2 to the input-output line 3, i.e. -to say in chronological order of the elements to be managed 23, 24, 25, ... associated with these repeater means.
• N 62.
• the central unit 1 sends on the ring management circuit 17 successive messages each comprising a different address which will be assigned to an element to be managed and will be stored in the controllable automatic addressing means 20, 21, 22 associated with this element to be managed, according to the operation described below.
• the central unit 1 sends, on its first input-output line 2, a first message called "go" comprising, for example, the address "1".
• the repeater 5 is blocked and derives this first message to the controllable automatic addressing means 20 which analyze it and store the value of the address "1" while returning to the central unit 1 , in the opposite direction to that defined above, that is to say in the "repeater 5" direction towards the first input-output line 2, a "return” message confirming that this memory has been stored. address "1", then by unlocking the repeater 5.
• the central unit 1 sends on its input-output line 2 the message “go "next with an address with a value greater than the first, for example” 2 ".
• This message will be analyzed by the addressing means 20 which will not recognize its address and, therefore, will remain transparent. This message therefore passes through the first repeater 5 and is applied to the first input-output terminal 9 of the repeater 6 which is blocked and which derives this message towards the addressing means 21 associated with the element to be managed 24.
• the addressing means 21 store the address "2”, send a "return” message to the central management unit 1 confirming that address "2" has been stored in memory and release the repeater 6.
• the maximum number of addressing operations is a function of the number of addressing means connected to the ring circuit 17. It is limited to "N", that is to say to "62" in the example chosen .
• the device can operate and manage the various elements 23, 24, 25, ... as described below, it being specified that the meaning of propagation of "go" messages in the ring management circuit 17 is defined automatically as a function of the address of the message and of the state of this circuit, and that the "return” messages, if they exist, always propagate in the opposite direction to the propagation of "go” messages.
• the central unit When an element must be ordered in a predetermined order, following a command order applied to the input 4 of the central unit 1, for example by a user by pressing a button, the central unit prepares a message comprising the address of the element to be managed and the order which corresponds to the command to be performed on this element.
• the device in fact has two operating modes, a first mode called “cyclic” which ensures determinism and security, and a second mode called "random", these two modes being explained below.
• This message is sent in the ring management circuit 17 so as to traverse the latter in the direction of the input-output line 2 towards the input-output line 3.
• 11 crosses the various repeaters 5, 6, 7 , ... each time being bypassed on the bypass input-output terminal 14, 15, 16, ...
• the message is not processed by the addressing means and continues to progress in the ring circuit 17.
• the addressing means transmit the message of the command to the element to be managed to operate the desired command.
• the element to be managed in association with its addressing means, sends a confirmation "return" message to the central unit, in the opposite direction to that of the propagation of the order message. that he had received.
• This "return” message blocks the repeater associated with the commanded element during the time of its transmission, the repeater becoming active again at the end of the "return” message.
• FIG. 2 represents the block diagram of an exemplary embodiment of the repeater means 5, 6, 7 ..., and more particularly of the repeater means 5, entering into the constitution of the embodiment of the device illustrated in FIG. 1 , it being specified that all the repeater means are identical and that, from the description of one of them, it is possible to deduce the embodiment of all the others.
• These repeater means 5 comprise a first input-output terminal 8 essentially constituted by a transmitting means 30 and a receiving means 31, and a second input-output terminal 1 1 constituted, symmetrically, by a transmitter 32 and receiver 33. Consequently, these terminals 8 and 1 1 can constitute inputs as well as outputs for both receiving and transmitting signals.
• These transmitters and receivers are for example constituted by optocouplers which also provide galvanic isolation between the various repeater means.
• the transmitters 30 and 32 receive, through respectively two multiplexers 36 and 37, the signals which are produced in a control logic 34 which receives, on bypass inputs 35 belonging to the bypass input-output means 14, signals from the addressing means 20 and / or from the element to be managed 23.
• the repeater means 5 also comprise a first covering module 38, one output of which is connected to an input of the multiplexer 36 and of which another output is connected, through a logic gate 39, to the addressing means 20.
• the inputs of the dressing module 38 are respectively connected to an output of the control logic 34 and to an output of the addressing means 20.
• the function of this dressing module is to complete the message which will be sent by the transmitter 30 to obtain a complete "return" message capable of being recognized by the central management unit 1 if the "go" message has been received on the first input-output terminal 8.
• the repeater means 5 also comprise a second covering module 40, one output of which is connected to the transmitter 32 through the multiplexer 37 and the other output of which is connected to an input of the addressing means 20 through the logic gate 39
• the inputs of the covering module 40 are respectively connected to an output of the control logic 34 and to an output of the addressing means 20.
• This covering module 40 makes it possible to process the message which will be sent by the transmitter 32 to obtain a complete "return" message capable of being recognized by the central management unit 1 if the "go" message has been received on the second input-output terminal 1 1.
• These repeater means 5 further comprise, at the output of the two receivers 31 and 33, receiver logic modules 50 and 51 whose inputs and outputs are respectively connected to the control logic 34 and to the addressing means 20 through two logic gates 41 and 42.
• a repeater as illustrated in Figure 2 has essentially three modes of operation, a transmit mode, a receive mode and a repeat mode.
• the operation of this repeater can be broken down into four phases, a phase A which is a phase of waiting for the reception of the "go" message, a phase B which is a phase of reception of the "go” message, a phase C which is a phase of analysis of the "go” message and a phase D which is a response phase, that is to say of sending the "return" message.
• phase A the modules 50 and 51 are respectively listening to the connections 8 and 11, the transition to phase B being made at the arrival of a "go" message.
• the module 50 performs the following treatments: - activation of a message signal during reception and sending of this signal to the control unit 34 and to the addressing means 20 via the logic gate 42,
• phase B that is to say upon receipt of the message, the control logic 34 prohibits listening to the circuit 17 by blocking the module 51 and validates the routing of the message by the multiplexer 37 to obtain the transmission through the transmitter 32 of the message received at input 8 and reshaped by the module 50.
• the transition to phase C is made upon detection of the end of the "go" message.
• the module 50 deactivates the message signal during reception and sends it to logic 34 and to addressing means 20 via logic gate 42.
• logic 34 blocks repeater 5 and addressing means 20 analyze the address of the received message. If these addressing means 20 do not recognize the specific address assigned to the element to be managed 23 o if they recognize a broadcasting address assigned to all the elements, alo these addressing means 20 send to the logic 34 an end of exchange signal which returns the repeater to phase A. If the addressing hubs 20 recognize the specific address assigned to the element to be managed 23, they go to phase D. During this phase D, the repeater 5 processes the "go" message prepares the "return" message.
• a control order is sent to the logic 3 which blocks the modules 50 and 51 and activates the multiplexer 36 so that the data transmitted by the addressing means 20 dressed by the module 3 can be transmitted by the transmitter 30.
• the addressing means 20 On the detection of the end of the "return" message, the addressing means 20 generate, for the logic 34, an end of exchange signal which returns the repeater to phase A. The reverse process is carried out for all messages received at entrance 11.
• FIG. 3 represents the block diagram of an embodiment of controllable addressing means 20 forming part of the embodiment of the device according to FIG. 1 described above.
• these addressing means 20 comprise a reception processing module 43 whose inputs are connected to bypass outputs 55 belonging to the bypass input-output means 14 of repeater means 5 defined below. above and whose outputs are respectively connected to inputs of a comparator 44 and to control inputs of an address extractor 45.
• the addressing means 20 further comprise an address memory 46 whose inputs control 47 are connected to the outputs of comparator 44 through the address extractor 45.
• This address memory are respectively connected to the control inputs of a transmission processing module 48 whose outputs are connected to bypass inputs 54 belonging to the bypass input-output means 14 of repeater means 5 defined above, and to inputs of a module for processing the state of the signals 49, this module As also connected a comparator 44.
• the addressing means described above have two possible function, a function for the automatic assignment of the address and a work function. For the function allowing automatic address allocation, two cases must be considered: the initialization function and the deactivation function.
• the module 49 blocks all of the covering means 38, 40, the multiplexers 36, 37 and the transmitters 30, 32 via the bypass input 35 of the control logic 34.
• the module 43 receives it from the bypass outputs 55 of the repeater means 5. It sends it to the comparator 44 and the address extractor 45.
• the comparator 44 compares the address of the message with a predefined reference value which corresponds to a "message-address label". If the comparator does not recognize this label, there is no initialization and the addressing means await a new message.
• the extractor 45 extracts the address to be stored contained in the data field of the received message and commands its storage in memory 46.
• This memory 46 sends an order signal to the module 49 to initialize it and another order signal to the module 48 which generates a "return" message which is transmitted to the repeater 5 via the bypass inputs 54 of this repeater 5.
• the addressing means 20 are initialized.
• the deactivation function is the one which allows to pass from the initialized state to the non-initialized state. To carry out this deactivation, a deactivation "go" message is sent to the management circuit 17.
• the deactivation process of the addressing means 20 is substantially identical to that of its initialization.
• the comparator 44 compares the address of the “go” message received with a predefined reference value which corresponds to a “message-address reset label”. As long as the comparator does not recognize this label in the "go" message received, the addressing means retain their initialization state. If the comparator recognizes the reset label, it performs the following processing: the memory 46 is emptied, it generates the end of exchange signal, the module 49 is deactivated and sends an order signal to block the transmitters 30, 32, the covering modules 38, 40 and the multiplexers 36, 37. The repeater 5 goes into standby and waits for a new message.
• the element to be managed 23 receives the data of the "go" message via the module 43 and a signal for recognizing the message sent. by the comparator 44.
• the same element 23 provides the module 48 with a request to send a "return” message as well as the data to be transmitted.
• Any message received at the inputs-outputs 8 and 11 of the repeater 5 is derived and presented to the module 43 via the receiver 31, the module 50, the logic gate 41 the input-output terminal 14 (if the reception is done on the input-output 8), or vi the receiver 33, the module 51, the logic gate 41 and the input-output terminal 1
• the module 43 analyzes the message received and presents the address of the message to comparator 4.
• the comparator 44 knows that the addressing means 20 are initialized because it receives a signal generated by the module 49. It compares the address of this message with that which is stored in the memory 46. The processing is finished if n there is no equality of addresses.
• the data of the message is transmitted to the element to be managed 23.
• the latter processes this data according to the requested application, then supplies the module 48 with a request for request d emission of a "return” message as well as the data associated with this message.
• the module 48 composes the "return” message so that it is sent via the repeater 5 to the central management unit 1.
• FIG. 4 represents the block diagram of an embodiment of the central management unit 1 entering into the constitution of the embodiment of the device according to FIG. 1.
• This central unit 1 essentially comprises a central management logic module 60 which comprises two input-output 61 and 71.
• Input-output 61 is connected to an output transmitter 62 through a transmission processing module 63 and to a receiver 64 through a reception processing module 65.
• the output 66 and input 67 respectively of the the transmitter 62 and the receiver 64 are connected together to form the line of inputs-outputs 2 defined above.
• the input-output 71 is connected to an output transmitter 72 through a transmission processing module 73 and to a receiver 74 through a reception processing module 75.
• the output 76 and the input 77 respectively of the 72 and receiver 74 are linked together to form the line of outlets 3 defined previously.
• the central management unit 1 also comprises a plurality of modules having different functions which are all linked together by a bus 80. These modules with different functions are for example constituted by an interface module 81, a maintenance module and errors 82, an interface module for different applications 83 and an exchange memory module 84.
• the central management unit 1 also comprises command input means 4 which allow potential users of the device to draw up different control orders and / or to exchange data in the exchange memory. The central management unit can thus be integrated into a reception system and interact with it via the command input means 4.
• the bus 80 is connected to the inputs 88 and 89 of the central management logic module 60 through a control module 90 generally constituted by a micro-sequencer such as, for example, a PROM memory looped back into a register, and through a module exchange memory interface 91.
• the exchange memory 84 advantageously comprises two parts, a "data" part and a "frame" part.
• the "frame” part is used for the management of the entire ring circuit 17 by the central management unit 1.
• This "frame” part can be contained in a PROM or in a RAM or in a combination of these two types of memory.
• the "frame” part is composed solely by a RAM, it is the reception system, via the input means 4, which provides the data necessary for the management of the "frame” part and which stores them in this memory.
• this "frame” part is composed of a combination of a PROM and a RAM, the PROM constitutes a cyclic frame background and the reception system comes to insert the messages in this cyclic frame.
• the "data” part is used to store all the data that propagates throughout the device.
• a device according to the invention is installed in a motor vehicle and comprises a set MES "headlights-addressing means-repeater", the device operates in the following manner.
• the MES assembly receives a "go" message with a headlight switch-on command. In the "return” message, it returns the "headlights on” information if this information is present on an application input of the ME assembly, that is to say if it has been previously stored in the exchange memory 8 because an MES assembly cannot create information.
• a set MES provides on its application outputs the information that it has received in a "go" message sent by the central management unit 1. In the "return” message, it transmits to the uni central management unit 1 the information present on its application inputs stored in the exchange memory 84.
• the central management unit does not have a reception system, the "headlight switch-on" command is carried out on the basis of a command injected into an application input of a MES assembly.
• the "headlight ignition control” information is taken by this MES assembly to be transmitted to the exchange memory 84 in a "return” message. From this moment, the device operates in the same way as described below, from this exchange memory 84.
• the central management unit When the central management unit is inserted into a reception system, it is this system which carries out the application "controlling the lighting of the headlights", the ring circuit 17 serving only as a transmission support for forward the information contained in the "outward” and “return” messages.
• the device according to the invention is advantageous because it is said to be “fault tolerant”, that is to say that it knows how to take into account and to compensate for so-called “simple” failures. For example, it is capable of withstanding a wire segment cut between two MES sets and continuing to operate correctly without loss of information and ensuring initial determinism. In the case where several wire segments connecting two successive M sets are cut , only the MES assemblies between the two extreme cut wire segments are isolated, all the others remain accessible.
• the device continuously performs its self-monitoring e when a fault is detected on circuit 17 by monitoring means included in the central management logic 60, the part 100 (described below with reference to FIG. 5) which has the function of automatically defining the direction message propagation in the ring management circuit 17 is activated.
• "go" messages are sent in the circuit from the input-output line 2.
• the central unit 1 then goes into mode waiting to receive the "return” message.
• the monitoring means check the complete consistency of this message and compare its address with that of the "go” message. If there is no error detected, the exchange is considered to be good. If an error is detected (for example inconsistency of the "return” message, mismatch of the two addresses), the address of the "go” message is saved in an intermediate register of logic 60. The same "go” message is sent again, possibly several times for security. If the error is confirmed, the value of the address saved in the intermediate register is stored as the breaking address in a memory of part 100 of logic 60.
• FIG. 5 represents the block diagram of the part 100 of the central management logic module 60 which has the function of automatically defining the direction of propagation of the messages in the ring management circuit 17.
• This part 100 comprises, from a bus 103 conveying the different messages to be sent in the ring management circuit 17, an address extraction module 104 whose output is connected to a first input 105 of a comparator 106, the other input 107 of the comparator being connected to an output 108 of an analysis and control module 109, this analysis and control module 109 being able to deliver to this output 108 a reference value corresponding to the value of the breaking address.
• the comparator 106 is capable of delivering on its two outputs 110 and 11 1 two types of control signals depending on whether the addresses of the messages applied to its input 105 are less than, or greater than or equal to, the value of the breaking address, these control signals controlling the analysis and control module 109 to control, either the opening of the transmission means 62-63 and reception 64-65 forming the input-output line 2 and the closing of the means of transmission 72-73 and reception 74-75 to send the messages conveyed on the bus 103 having addresses lower than the value of the breaking address on the input-output line 2, ie the closing of the transmission means 62-63 and receiving 64-65 and the opening of the transmission 72-73 and reception 74-75 means forming the input-output line 3 for sending the messages conveyed on the bus 103 with addresses greater than or equal to the value of the breaking address on the input-output line 3, which makes it possible to obtain the results defined above.
• the device guarantees the routing of this type of message whatever the state of the ring circuit 17.
• the device according to the invention can, in an advantageous embodiment, manage two types of data, so-called “trivialized” data and so-called “boolean” data.
• the "trivialized” data are transparent to the device, that is to say that they can be processed without being adapted or modified.
• "Boolean” data correspond to trivialized data sets and are generally in the form of logical signal sequences "0" and "I".
• the transfer of information in the device is carried out in the form of a message which is generally a set of pulse trains.
• These messages are exchanged via the ring management circuit 17 between the central management unit 1 and the signal repeater means 5, 6, 7, ... to reach, through the addressing means 20, 21, 22 , ..., the different elements to be managed 23, 24, 25, ..., and vice versa
• the central unit 1 develops the different messages necessary for the management of different elements with information Bl, B2, B3, ... , Figure 6, which its contained in the exchange memory 84 and stores in this exchange memory the information it has received from the elements to be managed.
• the central management logic module 60 performs a bijection between the data of a message arriving or leaving by the input-output lines 2, 3 (for example eight consecutive bits whose ran in the message is "modulo 8" ) and the addresses of the exchange memory 84 In this case, it is said that the device operates "by trivialized information".
• the device can also operate by duplicating information.
• the central management logic module 60 performs the automatic transfer of information at the input or output of a repeater hub to the input or output of another repeater means, or several others.
• This module 60 transforms the bijection mode defined above into a overjection.
• at an address of the exchange memory 84 there corresponds an input and at least one output, this mechanism being able to be used with unmarked data or Boolean information.
• i comprises, on the one hand means for bursting a datum (for example hui consecutive bits whose rank in the message is "modulo 8") consisting of "8 Boolean information in "8" information trivialized in the exchange memory 84, and on the other hand concatenation means to obtain the opposite function from that of the bursting.
• a datum for example hui consecutive bits whose rank in the message is "modulo 8”
• concatenation means to obtain the opposite function from that of the bursting.
• the association means make it possible to associate, with input information stored in a box of the exchange memory 84 (whether this information comes from an MES assembly or from the reception system via the input means 4) , one or "n" information as output, knowing that all this information must be of the same nature.
• the bursting means make it possible to decompose "n" consecutive elementary bits whose rank in the "return” message is "modulo n” into "n” information which can be stored in the exchange memory 84, knowing that this information can take two boolean values.
• the concatenation means make it possible to gather "n" information contained in the exchange memory 84 into “n” elementary bits whose rank in the "go” message is "modulo n", knowing that this information can take two Boolean values.
• This central management logic module 60 is associated with a transcoding table 120 (FIG. 6) which makes it possible to control, through in particular the central management logic module 60 and the exchange memory interface module 91, the addressing of the exchange memory 84.
• FIG. 6 is diagrammatically represented the operating diagram of the mechanism described above in which 121 represents, in a first case, a message arriving by an input-output line 2, 3 in the central management unit 1 ( from the repeater means) and which, thanks to the bursting means contained in the central management logic module 60, is split 122 into Boolean information Bl, B2, ..., Bn which are stored in the exchange memory 84 according to the transcoding table 120.
• FIG. 6 is schematically represented the diagram of the mechanism described above in which 121 represents a message sent by the central management unit 1 and obtained by grouping 123 boolean information Bl, B2, ..., Bn contained in the exchange memory 84 thanks to the concatenation means contained in the central management logic module 60 in association with the transcoding table 120.
• FIG. 7 represents the block diagram of an embodiment of another part 130 of the central management logic module 60 present in the block diagram of FIG. 4, corresponding to the functions "burst” and “concatenation” in association with a control and command logic circuit 133.
• This part 130 of the logic module 60 comprises a concatenation module 131, the block diagram of an embodiment of which is shown in FIG. 8 described below. Its input 132 is connected to the exchange memory 84 through the exchange interface module 91 and its output 1 34 is connected, on the one hand to the first input-output line 2 through a first register send buffer 135, and on the other hand to the second line of output outputs 3 through a second send buffer register 136.
• the concatenation module 131 and the two send buffer registers 135 and 136 are controlled from the control and command logic circuit 133.
• This part 130 further comprises a burst module 137, the block diagram of an embodiment of which is shown in FIG. 9 described below.
• the output 138 of this burst module 137 is connected to the exchange memory 84 through the exchange interface module 91.
• the first and second input-output lines 2, 3 are connected to the input 139 of this burst module 137 through, respectively, two reception buffer registers 140 and 141.
• the burst module 137 and the two reception buffer registers 140 and 141 are controlled by the logic control and command circuit 133 .
• FIG. 8 represents the block diagram of an embodiment of the concatenation module 131.
• This module very schematically comprises, from a data bus 150 constituting its input 132, a module acting in mode transparent 151 and a module operating in Boolean mode 152, that is to say for performing detection and coding of Boolean type information.
• These two modules 1 1 and 1 52 are mounted in parallel on the bus 150 and their respective outputs 1 53 and 1 54 are connected to the input 155 of a data storage module 156.
• This data storage module is essentially made up of a set of “n” flip-flops 157.
• the output 158 of this data storage module 156 in fact constitutes the output 134, defined above with reference to FIG. 7, of the concatenation module 131.
• the two transparent mode 151 and boolean mode modules 15 are controlled from a management module 159 which is synchronized and controlled from a logic counter 160 (modulo "n").
• FIG. 9 represents the block diagram of an embodiment of the burst module 137.
• This module comprises a storage module for received data 161 whose input 162 is connected to a data bus 163 which constitutes input 139 defined above.
• This module for memorizing received data 161 essentially consists of a set of "n" flip-flops 164.
• the output 165 of this module 161 is connected to the inputs 166 and 167 respectively of a module acting in transparent mode 168 and of a module operating in Boolean mode 169.
• the outputs 170 and 171 of these two modules 1 68 and 1 9 are connected to an output data bus 172 which constitutes the output 138, defined above with reference to FIG. 7, of the burst module 137.
• the two transparent mode 168 and Boolean mode modules 16 are controlled from a management module 173 which is synchronized and controlled from a logic counter 174 (modulo "n").
• the embodiment of the centralized management logic device described above comprises only one central management unit 1 However, in order to obtain a device having even greater reliability, it is possible to make a device according to the inventio comprising a second central unit coupled to the first with repeater means of the same type as those described above.

Landscapes

• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Automation & Control Theory (AREA)
• Small-Scale Networks (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=9446178

Family Applications (1)

Country Status (3)

Families Citing this family (5)

Family Cites Families (6)

• 1993
  • 1993-04-19 FR FR9304558A patent/FR2704337B1/fr not_active Expired - Fee Related
• 1994
  • 1994-04-13 WO PCT/FR1994/000411 patent/WO1994024618A1/fr not_active Application Discontinuation
  • 1994-04-13 EP EP94913640A patent/EP0672270A1/de not_active Ceased

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events