CH632350A5 - Data processing assembly - Google Patents

Description

The present invention relates to a data processing system according to the preamble of claim 1. The general structure of a data processing system typically comprises one or more processors, a main memory and a set of different types of peripherals or terminals (often referred to as I / O units) which may be more typically card readers, magnetic strip units, card punchers, printers, discs, control terminals, etc. Optimal systems generally have a structure in which the peripheral devices are processed by independent interface control units, so that the processor is free to access the data and process that contained in the main memory. In structures comprising separate control means for the input / output peripheral devices, it is possible to carry out parallel or simultaneous processing occurring at the same time as the input / output (I / O) operations. These concurrent I / O processing operations occur in the same program as that of one of the processors and which begins all input / output operations. In addition to the program, means are required to determine whether the I / O operations are inactive or have been completed.

For example, if a program requests that a data folder be loaded into main memory, it must be possible to determine if the operation has been completed before the data can be used. Thus, an input / output operation is started or started by the program as for certain types of initiation instructions which typically provide an address indicating an I / O descriptor, which is stored in the main memory. This descriptor identifies the device which sent or transmitted the data, the type of operations such as reading or registration; it identifies the domain of the positions of the main memory to be used for the input / output operation. In general, this I / O descriptor is transferred to a control means (I / O control means) to control the transfer of data between the peripheral terminal and the main memory.

When the input / output operation is completed, for example by transferring the data from the peripheral unit to the main memory to load the main memory, a declaration of completion is required which is typically called result descriptor. Generally, this descriptor is transferred from the I / O command to a characteristic position in the main memory known for the program used. Typically, the result descriptor comprises information identifying the particular peripheral terminal and information as to the result or the state of the particular input / output operation, to give information indicating whether the transfer was complete and correct or whether exceptional conditions have occurred and if any error or any particular situation has occurred for the transaction concerning the particular peripheral terminal.

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Thus, when a program begins an input / output operation, the program must include means for determining whether the input / output operation has been completed. A classic technique for this is that the program has instructions for periodically querying the result descriptor, to determine when and if a particular input / output operation has been performed. However, it is much simpler for an input / output control means to indicate whether the transfer operation has been completed. To do this, it is usually necessary to interrupt the operation that the processor is performing and to force it to examine the result descriptor to make an adequate decision. This shutdown or interruption of processor activities is generally called interruption.

When an interruption occurs, the processor must stop the program on which it is working and make a fixed notation of the point in the execution program where the interruption occurred and it must then store the contents certain control registers and flip-flops to have information when it must return to the program at the end of the interrupt cycle; then the processor must transfer its attention and its operation to the program intended to treat and maintain the condition of interruption.

Some systems such as the system described below have a program for dealing with interrupt conditions; this program is often called the main control program or MCP program. This program must keep a record of current input / output operations and associate the particular interruption with the particular input / output operation of which it is the origin. Then analyze the results of this interrupt cycle to see if no unusual circumstance or exception has occurred or if no error condition has been found, requiring corrective or corrective intervention. The interrupt program must take the results of the input / output operation and make them available to the program that started the input / output operations, then determine whether the other input / output operations are waiting to start and, if so, take steps to begin other necessary entry / exit operations.

In many known system structures as well as in the present system, many memory access calls or requests come into the memory device but, given the bandwidth and the time available, limited for the various peripheral units, many I / O transfers are incomplete and cause access errors.

Many known system structures provide only one or two communication paths or channels for a large number of peripheral terminal units, so that I / O transfers from a particular peripheral terminal unit must wait for their turn in shared access and use a communication bus. This results in system congestion as well as delays. There are also difficulties in multiple programming systems since efforts are made to adapt a job to several important input / output requests with another job which is linked to the processor and which has only limited input / output requests.

Many current data processing systems have a single switching path or a limited number of communication paths between the central processing unit and the peripheral units. Generally, there are, in a communication path, one or more input / output control means. When a processor requests an input / output path, the path will generally be available if: the peripheral unit does not start a transfer operation; the peripheral unit is not active in a transfer operation or any other operation with an input / output control means; the peripheral unit or the input / output control means is not active with other operations.

The data transfer speed of the input / output control means is a factor which limits the operation of the system since the often slow transfer speed of certain peripheral units (which have passed through the input / output control means) unnecessarily binds the activity. processor and memory at the low speed of the peripheral terminal unit.

Thus, many data processing systems have had a set of input / output control means comprising buffer memories, to allow a particular device or a group of devices to communicate with the main system. When there is a set of input / output control means (through which the communication channels pass to the individual peripheral units or groups of such units), certain known systems have used the method of data transfer in sequential mode , so that the various input / output control means take their turn for the allocation of the peripherals associated with them.

A difficulty arises when a certain number of peripheral units and their input / output control means are more active than others and when a certain number of channels concerned in fact require a longer communication time than that which their is assigned. A channel can be locked as a communication path between the main system by the input / output control means, on a peripheral unit. Thus, one can encounter cases in which certain channels are modified quickly in such a way that this generates a large number of access errors. Access errors relate to situations in which the bytes of data transferred by the input / output control means do not contain the complete message units,

but only consist of unusable fractions of message units. As a result, the central processing unit does not receive or transfer useful information and fixes itself on a permanent request for the same input / output operations, and this repeatedly. Thus, when the peripheral units are placed in a situation in which they are unable to send or receive a recording or a complete message unit, there is a risk of access error which results in incomplete cycles on the particular channel plan and incomplete transfers of the requested information data.

It is desirable that the maximum of data is transferred by all the input / output control means and without such access errors which result in incomplete cycles of data transfer (which are unusable and which constitute a loss of costly time).

Thus, in such a system structure, one encounters problems as to the duration allocated to each of the various channels for the data transfer operations as well as the problem of the priority state assigned to such or such channel among the set of canals.

Currently, in data processing systems, comprising multiple peripheral units (many of which are located at different sites), it is necessary to have groupings of the input / output control means to process the multiple peripheral units in each given site.

Thus, priority problems concern not only the priority which must be assigned between the peripheral units at a given local site, but also the problems of priority allocation between the various sites, each of them being provided with their own means. input / output control.

In order to remedy the problems mentioned, the data processing assembly according to the invention comprises the characteristics forming a constituent part of claim 1.

With the data processing set described below, it is possible to achieve the following goals:

- Avoid that the central processing unit is affected by the control and adjustment of data transfers between the main system memory and a large number of peripheral units.

- Increase the speed of data transfer between a large number of different peripherals which are all connected to the main system and which have a main memory and a processor. This concerns the transfer of main memory to any device, in the exchange direction or in the opposite direction.

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- Create an intelligent I / O interface control unit, which frees the central processor from numerous loads and which meets the needs of various peripherals, requiring access to the main memory.

- Ensure an intelligent I / O interface control unit, which can receive an I / O instruction from a central processing unit, then ensure from this moment the command, control and execution of this instruction to transfer data between the main system memory and any selected peripheral unit. This is done asynchronously, according to needs and requests. The interface unit thus processes the control of transmission errors of all the words and message blocks and, in addition, informs the main system of the state of any data transfer cycle, as for the state of its execution, and error status. The interface unit thus controls requests from a peripheral unit or for access to the main memory and informs the main system of the activity of the peripheral unit, that is to say of its unavailability.

- Allow easy extension of the modular type system. The I / O subsystem of the central processing unit serving a set of terminals is organized so that the interface units (line control processors) are grouped into eight-unit basic modules. Each module has a distribution card unit which interfaces the group of eight line control processors and the main system through the IOT unit of the main system. The distribution unit can thus define the properties between any of the eight line control processors of the basic module. In addition, when there is a set of basic modules in the system, the distribution unit of each basic module can have a priority rank (called global priority) such as the priority ranks of a basic module. given base, among a set of basic modules. Another object of the I / O subsystem concerned is therefore to provide means for setting a global priority (priority between the basic modules of the system) and the local priority.

- Delete access errors so that all data requested at a time determined by the main system (i.e. a length of a data message block) is always transmitted and checked for errors in a complete cycle without interruption (except in an emergency).

- Allow rapid completion of a data transfer operation between the main system memory and a given peripheral unit, without interruption or incomplete data transfer, when a communication channel is established (except for certain emergencies).

- Supply the main system with the variable state of any line command processor at all times, and with the results (complete, incomplete or errors) of any data transfer cycle.

- Provide modular building blocks to facilitate the development of the system by increasing the number of peripherals that the system can contain, simply and economically.

- Create an I / O subsystem in which the central processor is freed from the execution of the I / O data transfer cycles and in which this workload is distributed in the system through the I control units / O, LCP grouped into modular block units. Embodiments of the subject of the invention will be described, by way of example, with reference to the appended drawings in which:

fig. 1A is a diagram of a central data processing set having two different types of I / O subsystems; the two I / O subsystems being called: a) central control subsystem (CC) with input / output controllers (IOC), and b) line control processor input / output subsystem (LCP) ;

fig. 1B, IC, 1D, 1E are diagrams of the various components of the central control of the I / O subsystem;

fig. 2 is a diagram of a modular unit of the I / O subsystem,

LCP, called LCP basic module, showing the connection with the various peripherals;

fig. 3 is a diagram of the main central unit;

fig. 4A is a simplified diagram of the basic link between the central main unit, the line control processor and a peripheral unit in the line control processor I / O subsystem;

fig. 4B is a table showing the various codes of the various instructions that can be executed by an LCP line control processor;

fig. 4C is a table showing how four information digits (ABCD) are organized so that a line command processor can inform the main unit of operational results via a result descriptor;

fig. 5 A is a table of digital information (descriptor) used for the input / output translator (IOT) to create command messages (C / M);

fig. 5B is a diagram of the boundaries of the data fields of the descriptors of FIG. 5A;

fig. 5C is a block diagram of the input / output translator (IOT) linked to the main unit (processor and memory) and to the line command processor (LCP);

fig. 5D is a table showing the distribution of information in the IOT descriptor register;

fig. 5E represents the message level interface between the IOT unit and the distribution card unit of the LCP basic module;

fig. 5F is a diagram of the IOT notebook memory;

fig. 5G is a diagram of the address memory of the notepad type of the IOT unit (input / output translator);

fig. 6A is a logic diagram of the interface between the main unit and the LCP line control processor;

fig. 6B is a generalized block diagram of a line control processor;

fig. 6C is another generalized block diagram of a line control processor, with details of the data buffer;

fig. 6D is a detailed functional block diagram of the line command processor;

fig. 6E is a diagram of the intercooperation logic and of the control signals between the input / output translator (IOT) of the main unit and the distribution card unit of the line control processors in a basic module;

fig. 6F is a table showing the distribution of a message block and the composition of a digital word;

fig. 7A is a logic diagram of a line control processor which processes a peripheral unit, showing the counting states upon receipt of instructions;

fig. 7B is a diagram of the processing of a registration operation by the line command processor;

fig. 7C is a diagram of the processing of the read operation by a line command processor;

fig. 7D is a diagram of the logical processing of the result descriptor by the line command processor;

fig. 7E-1 and 7E-2 form an overall logic diagram of the line command processor.

Description of the preferred embodiment:

The digital system described below consists of a processor, a memory, a series of input / output controllers (IOC) forming a first I / O subsystem and a system of LCP line control processors. which constitute a second I / O subsystem. Line control processors basically process input / output operations for particular devices with minimal interference to the operations of the main processor. In addition, no device is hung up to wait for memory access, since the LCP processor for that device is always available to deal with that device.

A large number of data processing systems

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according to the prior art use a hierarchical system of the main memory, system in which it is necessary to transfer information between a large capacity memory, slow, and a small processor memory working at high speed, before being able to have the information . The system allows the processor and the I / O subsystem to directly access any location in the memory and, since the memory size can be up to one million bytes, much more information for the processor, without introducing an additional I / O link. This system can include a high-speed bipolar memory (cycle time: 250 ns) as well as an error correction system. Bipolar memory is not only fast, but it is much more insensitive to the type of error that creates program failures. When an error is detected, the error is corrected during the normal memory cycle and no additional time is necessary for the correction cycle.

Various operational relationships between the main memory of the processors and the other units of the present system can be found in the publication of the Burroughs company entitled "Burroughs B2800 / B3800 / B4800, MS-2, Reference Manual, catalog 1090560, 1976".

Normally, I / O memory cycles are only a small fraction of the total number of available memory cycles. However, during periods of high I / O activity, the probability that two devices request the same memory cycle increases. If, as a result of simultaneous requests, a device cannot access the memory within the period of time which is allocated by the system, precious time is lost by repeating the operation. In addition, during periods of low I / O activity, many memory cycles are not used.

I / O activity problems are resolved in the system described by distributing I / O processing to a group of LCP line control processors. By doing so, it is enough for the central processor to start the I / O activity, then it no longer participates in the input / output (I / O) operation. The central processor starts the I / O activity with a device called input / output translator (IOT).

The LCP processor, once started, can receive a large amount of data and, in most cases, a whole message block. At certain operating points, the LCP processor requests access to the memory and, when this access is allocated, the LCP processor transfers the information from its intermediate word memory to the memory, at the maximum speed of operation of the memory . If, at this time, the requested access to the memory is not allocated, the LCP processor continues to introduce the word in the intermediate memory and to wait for a possibility to access the memory. Thus, the device is protected against the absence of activity, since the data is transferred to the buffer memory of the LCP processor which transfers this data to the main memory without losing a memory access period.

The result of this process and this system is the removal of the load maximums imposed on the memory by the I / O activity requests; instead, the I / O subsystem uses the memory cycles that would be lost. As this I / O processing method is more efficient, the system allows higher input / output (I / O) data transfer speeds and can also receive more I / O devices.

In the present computer system, there are two categories of input / output subsystems, that is to say that the second I / O subsystem controls and the first subsystem of a input / output translator cooperates with a group of command line processors, the control of the system being facilitated by the use of descriptor information, which crosses the various units.

A descriptor result is a report to the main processing system, which describes how the operation was completed or why the operation could not be completed. The result descriptors of the processor and the I / O control systems are words with a length of 16 bits. LCP result descriptors can be longer than a word, and each bit of the result descriptor represents the state of a certain condition that must be reported to the main system.

Line command processors and I / O controllers always write the result descriptors at the end of an operation; the processor writes a result descriptor only in the event of an error. The result descriptors are written in predetermined places in the memory; for the processor, the place is not example address 80.

The result descriptors of the line command processors and the I / O controllers are written in positions which begin at the address indicated by the equation (CH x 20) + 200, CH being the number of the channel of the device which has been implemented. The IOT result descriptor is entered at address 260. After writing the result descriptor, the system creates an interrupt.

LCP, R / D Result Descriptor:

At the end of the operation assigned to it, the LCP processor stores a result descriptor which describes for the processor the manner in which the operation was performed. An LCP result descriptor can consist of one, two, or three 16-bit words. The first R / D result descriptor is stored in memory at the location indicated by the equation (CH x 20) + 108, CH being the channel number of the LCP processor. If more than one result descriptor information word is to be entered (expanded result descriptor), the additional words are stored in the address memory of the IOT circuit.

As shown in Table I, the first LCP result descriptor word is preceded by a one-word link and the result descriptor channel (IOT). Typically, the link is used by the operational system as the address for the next result descriptor to be examined. Table II represents the basic word format of a 4-digit data word A, B, C, D, each digit having 4 bits and each character having 8 bits. Symbols are used to designate the parts of each digit such as A8, A4, A2, Al, etc.

Table I: Result descriptor

Result descriptor

Link

16 bit LCP 16 bit IOT channel result descriptor

16 bit t

(CH x 20) + 100 1

(CH x 20) + 108

Position of LCP / channel result descriptor in memory

Table II: Data word

Digit

AT

B

VS

D

AT 8

B8

C8

D8

A4

B4

C4

D4

A2

B2

C2

D2

Al

B1

Cl

D1

one character =

8 bit = AB

Y

one word = ABCD = 16 bits

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Table III indicates the format of the I / O descriptor which is normally stored in the main memory and which is accessed to regulate a particular type of input / output operations. As noted, there are four syllables and each syllable is made up of 6 digits. These digits are numbered D1-D6, D7-D12, D13-D18, D19-D24 to indicate the relative positions of each digit. In syllable 1, the digits Dl and D2 always indicate the type of input / output operation to be performed and are generally called code-OP. Digits D3-D6 are called variant digits in that they indicate the different options that can be included in a characteristic input / output operation.

The syllable 2 contains the address of the most significant digit (MSD) of the part of the main memory which is used in this particular input / output operation as buffer zone. This buffer area is used as the start of the address. The syllable 3 contains the address of the least significant digit increased by 1 (LSD +1) of the buffer zone input / output, and which is called termination address. The most significant address and the least significant address increased by 1 represent the maximum limits of the memory of the recording which is to be transmitted. The length of the recording may or may not use the entire area within this limit. However, any attempt to exceed this limit causes the end of data transmission to this zone.

The syllable 4 is used only for disk folder descriptors and contains the disk address.

The length of the recording may or may not use the entire area within the limits between the start of the address and the end of the address. As indicated, any attempt to exceed these limits will stop the transmission of data to this area. For example, one can read punched cards in an area greater than 80 characters, that is to say with MSD and LSD + 1 to 80 characters; one can also read in this zone less than 80 characters; for example, the recording area defined in a particular program corresponds to 40 characters in a card recording. The data in columns 1 to 40 of the punch card are stored in the memory recording area allocated to MSDetLSD + 1.

(Table on next page)

General description of the system:

The I / O system is part of a digital system environment to provide means of communication between a central data processing system and a variety of peripherals that are connected to and cooperate with the system. The peripherals that work with the global digital system range from mass storage devices, such as disks or disk arrays, to system control devices such as the operator control terminal or a wide variety of devices. other peripheral devices such as printers, card readers, hole punches, tape storage devices, etc.

The I / O system described below can be divided into two categories of main subsystems depending on the control process of the various peripherals. The first category uses a process having I / O controllers (IOC) cooperating with the processor and the central control to process the I / O activity. The second category uses an input / output translator (IOT) in the general processing unit, which cooperates with the various units called line control processors (LCP). The units known as line control processors are devices which establish communication between the system (main memory and processor) and a specific peripheral device. As soon as the communication path is established, the LCP processor can receive or pass data to a determined peripheral, for subsequent transmission to the main system. As each LCP processor has its own buffer memory, data can be exchanged with a certain device at a relatively low speed. However, if the buffer memory of the LCP processor is connected in order to exchange information with the main system memory and the processor, this data can be transferred to the main system, at the highest speed authorized by the memory of the central system.

The first category of I / O subsystems, which uses I / O controllers as interfaces between a peripheral and the main memory and the processor, comprises a central control unit (CC) which connects the I / O channel and the control I / O with central processor and memory. These input / output controllers accept instructions from the processor and return data information about the outcome of what has happened, and about the particular instruction. This result information is placed in a determined location in the main memory.

In the second category of I / O subsystems, there is the system in which the processor and main memory communicate via an input / output translator (IOT) with a group of basic LCP processor modules; each module constitutes a unit of a group of eight line control processors (LCP). Thus, an instruction of the processor is translated by the I / O translator into a determined set of orders acceptable by each particular LCP processor. After an LCP processor accepts instructions from the I / O translator, it brings back certain result information which is stored in a specific location in the main memory.

Thus, in this second I / O subsystem, all communications between the main processor of the system and the memory, via a determined peripheral, are controlled by an LCP processor which is only intended for this particular peripheral.

When a line control processor (LCP) or an input / output control means comprises a central control, it comprises a unique number called the channel number. For I / O controllers, this number corresponds to a word in a processor notebook. For line command processors (LCP), this channel number corresponds to a word in the notepad memory of the input / output translator (IOT).

To perform the input / output operation of the system, an I / O request is started with an I / O startup instruction which indicates to the processor the location of the appropriate I / O descriptor in the main memory, and the number corresponding channel. The I / O descriptor contains the OP code as well as the variants of the type of I / O operations chosen as well as the start A and the end B of the address of the memory area in the main memory.

The processor accesses this I / O descriptor, then sends the OP code and its variants to the chosen I / O controller (first subsystem) or to the I / O translator (second subsystem). The I / O controller or I / O translator verifies the OP code and indicates the acceptance or rejection of the request.

In the first subsystem, the processor then loads the start (A) and end (B) addresses into the local register and informs the I / O controller that the addresses are available. These particular addresses are transferred by the I / O controller to the location of the notebook memory intended for this I / O channel.

In the second subsystem, the IOT translator directly accesses addresses A and B from the memory address lines leading to the local processor register (fig. 3) at the time of transfer from the main memory, and thus the IOT translator loads its own local notepad memory.

Access to the main memory is shared by the IOT translator, the central control and the processor. The highest priority is shared by the IOT translator and the central control. The chronology can be provided so that each central command is guaranteed and limited to each fourth memory cycle (for, for example, a frequency of 8 MHz). The IOT translator is guaranteed for other cycles. When the central control does not request memory, the IOT translator can occupy all the

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Table III: I / O descriptor format

Syllable 1

v

Syllable 2

_at_

d1

D2

d3

d4

d5

D6

d7

d8

D9

dio

Dil

84 2184 218421842184218421842184218421842184218421

Operation code

Different digits as indicated by each I / O instruction

MDS - Address of the most significant digit

Binary magnitude

"AT/

Syllable 3

_at_

J \.

V

V

Syllable 4

d13

d14

d15

d16

d17

d18

d19

d2o d21

d22

d23

d24

84 2184 218421842184218421842184218421842184218421 \ m k _ /

V

LSD +1 - Address of the least significant digit increased by one v

Address of disk folders

Binary magnitude

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memory cycles. The processor takes all available memory cycles based on the lowest priority.

Thus, the I / O communications of the system require that the processor execute an I / O initiation instruction (which may for example be called OP = 94). This initiation instruction characterizes the channel number of the requested device and the position of the I / O descriptor in the main memory. The I / O descriptor indicates the action that the device must perform and specifies the limits in the memory of the data field. The descriptors and the manner of their execution vary depending on the process by which the device is controlled.

When an I / O initiation instruction is executed for a channel containing an I / O command (first I / O subsystem), the processor transmits a descriptor OP code word, variants and the address C ( if applicable) for the I / O command. The addresses A (start) and B (end) of the descriptor are stored in the I / O channel address memory of the processor. The I / O command verifies that the OP code is valid, then signals to the device that the data transfer must begin.

As indicated above, the embodiment of the current digital system relates to the splitting of the input / output subsystems. The second of these systems concerns the central system with the input / output translator (IOT), the line command processor (LCP) and all the peripheral units; the first I / O subsystem concerns, as shown in fig. 1 A, the central control unit 12 which interfaces with a set of I / O commands, 13a and 13b, which interfaces with a set of peripherals 14a and 14b, etc.

The following description relates to the first I / O subsystem comprising the I / O controllers and the CC central control members.

Fig. 1B shows the link system of the I / O channels and the processor 10p as well as the main memory 10m via the central control 12. The logic levels are created in each I / O channel 100.101 (fig. 1C) and are combined by the central control 12 before being sent to the processor 10p and to the main memory 10m. Other logic levels are created by the processor and in the memory and are distributed by the central command 12 to each I / O command such as the command 13a (FIGS. 1A and 1B). There are thus logical levels which pass through the central control 12 which plays the role of connection block between the processor 10p and the I / O channels. The priority logic 10 ^ in fig. 1C determines which of the I / O channels will access the main memory 10m if more than one channel requested access at the same time.

As shown in fig. 1C, there is provision, for the central control 12, a translator capable of translating the BCL data (common Burroughs language) and the binary exchange code in extended decimal coding (EBCDIC), with the core of the memory 10m. The I / O control units, 13a, 13b (fig. 1A) ask the central control 12 to use the translator 12t (fig. 1C) or to short-circuit it. The translation is done when the data is exchanged between the I / O control unit such as 13a and the main memory 10m. Additional time is not necessary for I / O operation, even if a translation is required. The translator's logic translates the input BCL data into data in EBCDIC or the output EBCDIC data into BCL data. EBCDIC codes to which BCL codes are not assigned create a code corresponding to the symbols *? * In BCL code.

The central control 12 acts as an interface between an I / O channel and the main memory 10m during the operation of the system, as shown in FIGS. 1B and 1C. This command determines the priority of memory accesses, if more than one channel requested access, and translates the input data for the I / O channel, such as channel 100, memory 10m, or channel I / O to memory. The central control correlates the various channel functions. The sequence of events is started by the 10p processor when an I / O channel is required.

When a program to be carried out requires a peripheral unit, such as 14a or 14 ^, in fig. 1A, the processor 10p executes the I / O initiation instruction. This instruction reads an I / O descriptor from the memory 10m and sends the necessary information to the I / O channel 100 via the central control 12. This information contains the type of operation (OP code) and the information variant. The remaining part of the I / O descriptor containing the start (A) and end (B) addresses is stored in the address memory 10pam (FIG. 1C) of the processor 10p. The channel is chosen by the channel allocation level (CDL) as shown in fig. 1B, from the 10p processor.

When all the information is available, the I / O channel 100 is released from the channel start bus (STCB), fig. 1B, to work independently. When the I / O channel has been freed, it functions as another processor and shares the main memory 10m with the main processor 10p or the other channels (fig. 1 C).

If the operation to be carried out concerns a peripheral unit 14j of the input type such as a card reader, the data is received by the I / O channel 100 according to FIG. 1C and the data is stored in the buffer memory C0, in the I / O channel 100. The I / O channel then requests access to the main memory 10m via the central command 12. This request is processed by the priority logic 10 ^ which commands the other requests at the same time. As soon as memory access has been assigned to the channel, the information is transferred to the 10m memory. Information may or may not be translated based on the I / O descriptor. The information is then recorded in the main memory 10m at the location indicated by the start (A) and end (B) addresses in the address memory 10pam.

If necessary, at a certain point, the data or information to be transferred from the peripheral terminal is done by an output operation (fig. 1D). If an output operation is to be performed, an analogous sequence of events occurs as before, except that the data leaves the main memory 10m towards an I / O channel such as channel 102 in FIG. 1D. Then, when a peripheral unit, such as for example a printer 14p, requires data, the memory access request is applied to the central control 12 via the I / O channel 102. When the priority is allocated to the channel, the data is read from the main memory 10m at the address specified by the start and end addresses, in the address memory 10pam; this data is then transferred to the intermediate memory C2 of the I / O channel via the translator 12t (or shunts the translator according to the I / O descriptor). As shown in fig. 1D, the data is then transferred to the peripheral unit such as the unit 14p.

As shown in fig. 1E, the central control 12 provides the interface for the exchange with the I / O channels, the processor 10p and the memory 10m. The control information of the processor 10p is sent to the central control 12 in which it is distributed to each of the I / O channels 100, 101, etc. The central control 12 processes all the memory requests made by the I / O control units in this first I / O subsystem. The data of each I / O channel which must be written in the memory 10m are placed on the memory writing bus by the central control 12 and the data which must be read from the memory 10m is placed on the reading bus of memory and is distributed to each I / O channel.

When a request is made by an I / O channel unit, the central control 12 obtains the memory address of the address memory position reserved for this characteristic I / O channel. This address is used to access the main memory 10m and the memory cycle is then started. The memory cycle must be a write or read cycle depending on the characteristic I / O operation.

When the processor 10p requests access to the memory, the memory address concerned is obtained from the address memory lOpam in the processor 10p. This address is used to access the 10m main memory and the memory cycle begins (either writing or reading).

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Since only one memory access is possible at a given time, multiple memory requests must be treated separately; this processing is done automatically by the priority command lOp ,. (fig. IC, 1D) by the central control 12, as indicated previously. Each central control 12 contains a priority logic 10 ^ which is established or modified by an adaptation to the technical field. As the I / O channels are added to the central control 12, they are also added to the priority network. The processor 10p, under these conditions, has a lower priority than the central control 12. The highest priority request is assigned first and, as soon as it is completed, the request having the second priority is assigned automatically. This operation is repeated until all multiple requests are processed. The requests are allocated alternately to each central control unit during multiple central orders, according to the order which had the last request. If a central control does not receive access, it is allocated to the 10p processor.

During the data transfer operation, in the subsystem of the first category, the input / output controller (I / OC) can perform various functions depending on the OP code, the variants and the type of peripherals used. Typically, I / O controllers can store only one byte or, at most, one word. Then, when the data buffer of a controller is loaded, the I / O controller, or the I / O channel unit 100, 101, 102, must request access to the memory; this is why the speed of data transfer or exchange with the system is controlled first by the speed at which the device can write or read. The second I / O subsystem using the base modules in the line control processors does not have this speed limit.

When the I / O controller requests access to memory, it actually requests the processor to perform a series of operations; these operations are as follows:

a) transfer the data of the address field of the I / O channel address memory of the processor to the local address register;

b) start a memory cycle;

c) restore the address field data from the channel address memory.

The I / O controller also tells the processor how much the address must be increased to arrive at the location of the next data address field. At the end of the operation, the I / O controller establishes a result descriptor (R / D) indicating how the operation was carried out, then the I / O controller stores the result descriptor in a reserved memory position, then it flips the processor switch.

In the second category of I / O control activities, an input / output translator (or translator) (IOT) is used as the interface unit, which is located in the central processor unit 10. The IOT translator ensures the interface with a group of line control processors (LCP) installed in the LCP basic modules. Up to eight LCP processors can be housed in a basic LCP module. The basic LCP processor module can accommodate up to eight LCP processors. The LCP processor is a smart interface unit that establishes a communication path between the affected device and the processor and main system memory. This communication is established by the LCP processor upon receipt of an order descriptor (C / D) from the IOT translator, which has translated the original I / O descriptor into an order descriptor, specialized for the LCP processor. .

As each LCP processor has a large intermediate data memory, for example of 256 words, it is possible to exchange the data with a determined peripheral, at the relatively low speed of this peripheral; however, when a data buffer is full, data can be transferred from the main system at the highest speed allowed by the speed of the main memory, which is a very important speed.

The basic LCP module which has up to eight LCP processors cooperates with the IOT translator to establish communication and start the operation of a particular LCP processor. The basic LCP module also provides time signals, provides logic maintenance, power, and cooling for each group of particular LCP processors.

The IOT translator which is part of the central processing unit, and which, on receipt of an I / O descriptor, cooperates with the LCP basic module to establish a connection with a particular LCP processor in the channel, is defined by the initiation instruction I / O. The IOT translator translates the I / O descriptor into a form (order / descriptor) that the LCP processor can recognize and, when the connection is established, the descriptor thus translated is applied to the LCP processor; then data transmission can begin. While the data is transferred between the LCP processor and the main system, the IOT translator, upon a request from the LCP processor, requests memory accesses, then accesses the memory and modifies and compares the data addresses. In addition, the IOT translator controls the flow of data between the chosen LCP processor and the main system and performs translations (ASCII / EBCDIC) of the data, if necessary. At the end of an operation, the I / O translator accepts the R / D information (result descriptor) from the LCP processor and stores the result descriptor in a predetermined location.

The structure of the LCP system allows up to 68 I / O channels.

In the I / O control subsystem, there can be two central DC controls with eight I / O controllers each for a total of only 16 channels. However, in the LCP subsystem, you can have up to eight basic LCP modules per I / O translator. Each basic module can process and carry up to eight LCP processors. An I / O translator can service up to 64 LCP processors. A multiplexing adapter can be used to connect two I / O translators to a common LCP basic module. This structure can be used to improve the I / O bandwidth to the main memory.

The entire I / O system has channel addresses that must be unique in themselves. Access to the main memory is shared by the I / O translator, the central control and the processor.

In fig. 1 A, we have a global diagram of the system showing the two categories of I / O subsystems. The first I / O subsystem is a central control 12 which carries the I / O commands 13a and 13b and which is connected respectively to the peripheral devices 14a and 14b. This first I / O subsystem using a central control is connected to the main system 10 via an interconnection bus 11.

The main system 10 consists of the main memory 10m, the central processor 10p, the memory control 10c and the input / output translator 10t. A PCC interface (peripheral control unit) 10; is connected via bus 5 to a peripheral control unit 6 which contains the central control and the I / O control units of the first I / O subsystem.

The input / output translator 10t of the main system (fig. 1 A) forms a second I / O subsystem by the use of boxes such as LCP boxes numbered 0,1,2 bearing the references 160,161 (162. Each of the LCP boxes have three basic LCP modules, 0-8; for example, the base box 160 carries the basic modules 20o, 20ls 202; the LCP box 16, carries the basic modules LCP 203, 204 and 205. From the Likewise, the LCP 162 box carries the LCP 206 and 20 basic module. Each of the various LCP basic modules is connected to the I / O translator 10t via message level interface cables (PWM) 15 , each consisting of 25 lines.

Fig. 2 shows in more detail the basic module LCP 20 „. The basic module 20o is composed of eight line control processors (LCP) 20oo ... 207O in addition to a common distribution card 20od, a common maintenance card 20om and a common termination card 20ot. The distribution card 20od connects a set of message level interface cables 15 to the I / O translator 10t (see also fig. 5E).

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Each line control processor is connected to the output lines of a particular peripheral which, as shown in FIG. 2, connects the LCP 2000 ... 2007 processors respectively to the peripherals 50,51,52,53,54,55,56,57.

While each LCP processor in the basic module may be slightly different to adapt to the particularism of each device corresponding to the LCP processor, each LCP processor is essentially identical in terms of construction and operating possibilities. In fig. 2, a typical example of such an LCP processor has been shown, such as the LCP processor 2006 which comprises an interface system 21si, an interface device 22 ^ and a word buffer memory 2506 which can typically contain 256 words.

Fig. 3 shows in more detail the block diagram of the main system linked to the I / O subsystems. The main system 10 comprises a main memory 10m in which a reserve part 10, ^ is provided for each of the I / O descriptors, as well as another reserve part 10mr for the result descriptors. In addition to the main memory 10m, there is another reserve part 10nc for storing the channel numbers. I / O descriptors, result descriptors and channel numbers are information used by the system for controlling and recognizing the status of operations. A detailed description will be given later.

The processor 10p includes a local register 10pr, used to store information for the I / O translator. The 10t input / output translator has a 10ps notebook memory channel.

The local register 10pr of the processor 10p is used to register the start (A) and end (B) addresses of the appropriate I / O descriptor. In the case of the first I / O subsystem using a central control (fig. 1 A), the I / O circuit ensures the transfer of the addresses to a temporary storage position called notepad memory channel or memory channel d 'addresses. In the case of the second system using the I / O translator, it directly accesses addresses A and B from the memory address lines leading to the local register 10pr of the processor. The notebook memory channel of all 64 LCP processors is contained in the I / O translator. The notepad channel also contains the desired channel numbers.

According to fig. 4A and the transfer of information as between the main system 10 and the characteristic LCP processor 2000, a short examination of the information words and their functions indicates the nature of the functional relationship.

Order descriptor (fig. 4D):

The order descriptor (C / D) is a modified form of the I / O descriptor. The descriptor I / O is the information which resides in the main memory 10m (fig. 1) as well as in the memory 10mi (fig. 3) and which provides data of information as for the type of operations input / output to be carried out . The modification of the I / O descriptor is made by the I / O translator 10t (input / output translator, fig. 1) which receives the I / O descriptor from the system memory 10m, retains part of the instruction and transmits the part applicable to the LCP 20 ^ processor as order descriptor.

The order descriptor is a 17-bit word A, B, C, D (fig. 4B) formed by a digit of code OP (A), with variable digits 1 (B) 2 (C) and 3 (D ) and a parity bit. However, the LCP 2000 processor uses only the OP code digit and the variable digit 1 to carry out the instructions. The variable digits 2 and 3 are always equal to 0. The code digit OP (A) defines the basic operation to be performed by the LCP 20oo processor and the variable digit 1 (B) indicates the modifications to the basic operation . No memory address information is sent to the LCP processor; the system memory address functions are provided by the I / O 10t translator. Fig. 4B contains the order descriptor codes for all the operations that the LCP processor can perform. These operations are as follows: registration, reading, registration with reading, test, authorization test, conditional deletion and echo. These operations will be described later.

Description link (fig. 4A):

The descriptor link (D / L) consists of two 16-bit information words accompanied by a longitudinal parity word (LPX). The descriptor link is exchanged between the I / O translator 10t (fig. 1) and the LCP 20flo processor at determined times during the communication between the two units. The content of the descriptor link is shown in the following table. Data bits that are not specified are reserved for future use:

Table IV

Descriptor link

Data bits

Designation

AS

Denying access to system memory

A2

ASCII translation request

Cl

Address of the base module

4 bits

Cl

Address of the base module

2 bits

D8

Address of the base module

1 bit

D4

4-bit LCP address

D2

2-bit LCP address

D1

1-bit LCP address

Data (transmissions) (fig. 4A):

These are bidirectional communication lines for transferring the data of the system 10 by the LCP processor, such as the LCP processor 2000 for possible transfer to a peripheral such as the peripheral 50; moreover, it may also involve the transfer of data from the peripheral 50 by the LCP processor 20flo and thus to the system 10 to be stored in the memory 10m. In fig. 1 and 3, these channels are the message level interface (PWM) 15. The data transmission between the system 10 and the LCP 2000 processor is in the form of words (table II), except for certain transmissions which are limited to a single character or for transmissions that end in an odd number of characters. Each data word is made up of two 7-bit ASCII characters and a single parity bit. Data bits A8 and C8 are not used (Table II).

It should be noted for the order descriptor that, after receiving an order descriptor and before executing an operation, the LCP 2000 processor receives the descriptor link from the I / O translator 10t and stores it in the buffer memory of the LCP 2500 processor (fig. 2). When the LCP processor 20flo cuts off from the system 10, it reconnects for another communication and the descriptor link is brought back to the I / O translator 10, to identify the LCP processor and the progress of the operation.

Result descriptor (fig. 4A):

The LCP processor 2O00 creates a result descriptor which is applied to the system 10 after the execution of the instruction contained in the order descriptor (C / D) or when an error occurs during the reception of a descriptor d 'order or descriptor link. The result descriptor is applied to the system 10 by the LCP processor in the form of a 16-bit word format with a parity bit. Fig. 4C shows a 16-bit form for the result descriptor, the digits A, B, C, D each having 4 bits.

Longitudinal parity word (fig. 4A):

The word longitudinal parity (LPW) is a 16-bit word representing the longitudinal parity of each transmission between the system 10 and the LCP 2000 processor. The word LPW is stored in both the I / O translator 10t and the LCP processor 2000 during the transfer of information between two units. A word register

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LPW is provided in the LCP 20oo processor in which the accumulation of the word LPW by the LCP 2000 processor consists in applying each word to be transferred to the entry of the LPW register and in performing a binary addition operation without carryover (function OU- EXCLUSIVE). Then at the end of the data transfer, the EXCLUSIVE OR function is again performed between the words LPW of the transmitting unit and of the receiving unit. When no error has occurred, the two words LPW are identical and the resulting value in the LPW register is a set of 0.

Input! Output translator (IOT) (fig. 5C):

The I / O translator 10t translates the I / O descriptors of the system into suitable operational messages intended for each LCP processor. In return, the result messages of the LCP processors in the form of result descriptors are not translated by the I / O translator, but are stored directly in the memory 10mr in the form in which they are transmitted by the LCP processors. The I / O translator performs all the information transfers between the LCP processors and the main memory 10ra, transfers necessary to enhance the input / output possibilities of the second LCP I / O subsystem.

The I / O descriptors which are applied to the I / O translator by the memory 10m are represented in FIG. 5A. Part 1A of this figure shows the descriptors used by the I / O translator to create C / M order messages for the LCP processor. They can also be called C / D order descriptors. Part 1B indicates the descriptors used by the I / O translator. Operations 40 to 58 are translated into OP, LCP code and are applied to LCP processors by forming a message. The digits L of the variable field transfer information, used for the variable digits (B, C and D) of the descriptor information, are applied to the LCP processors. The digit S is used by the I / O translator as shown in the note in part 1A of fig. 5A.

Each operation shown in fig. 5A presents two OP codes; the difference is the number of addresses used by the LCP processor. The first digit of the OP code indicates the number of addresses required. For example, a quantity equal to 4 indicates two address operations (with the exception of the test which has only one); a quantity equal to 5 for the first digit of the OP code designates an operation with three addresses. The second digit of the OP code is indicated in the OP codes actually sent to the LCP processors in the form of a digit A.

Fig. 5B shows the limits of the data field of the operations in the forward direction and in the opposite direction (direct = exchange between the system and the LCP processor).

Fig. 5 A also shows four types of conventional operational messages used for controlling LCP processors, namely;

1.reading

2. registration

3. test

4. echo

The characteristic descriptor information is collected in the form of variants which accompany the OP codes. Read and write instructions require access to system memory. All operations that do not transfer data are considered tests. Thus, a test is defined as an operation which results, in the I / O translator, in the mere receipt of result information. The echo operation is a confidence test which causes the LCP processor to accept a load of buffer information from system 10 and return this load to system 10 for verification.

All communication between the main system 10 and the LCP processor takes place via a standard message level interface 15 (MLI). This communication between the I / O translator and the various LCP processors is done by a standard flow discipline which is common to all LCP processors.

In fig. 5C, the I / O translator 10t receives the I / O descriptors from the processor 10p. The I / O translator then connects via the distribution unit 20od to the requested LCP channel and sends descriptor information, translated (C / D order descriptor) in message format indicating the work of the processor. LCP. The I / O translator then goes to the LCP trained state. This means that the I / O translator responds to various LCP states (including memory requests) as indicated by the command lines between the LCP processor and the I / O translator in fig. 4A. The I / O translator ensures the transfer of information between the main memory and the LCP processors. Memory requests from LCP processors control the I / O translator for all data transfers except that of initiation.

The I / O translator or the LCP processor can initiate the connection to the main memory 10m. The I / O translator initiates a connection from the main memory to an LCP processor (to its corresponding device), by performing an algorithm which is called the Hair test. In addition, the LCP processor starts a connection to the I / O translator and the main memory by an algorithm called Poil request. As soon as the LCP processor is connected, it indicates its state by the command lines in fig. 4A. The LCP processor that initiates a Poil request must compete with the other LCP processors in the system; a connection to the main memory 10m is allocated on a priority basis which will be described later. During an operation, the I / O translator 10t can cut itself off from an LCP processor to serve another LCP processor.

Message transmissions between the I / O translator and the LCP processor relate to data and control messages that are transmitted by 16 bits at a time with one bit of vertical odd parity. Following the last message, a 16-bit longitudinal odd parity word (LPW) is transmitted with a vertical odd parity bit. Parity is checked by both the I / O translator and the LCP processor. If the LCP processor detects a parity error, the processor indicates this in the transmission of the result information (result descriptor) and stops the operation. If the I / O translator detects a parity error, it introduces it into the LCP result descriptor.

The 10t input / output translator (IOT) consists of four main functional sections, each relating to a particular aspect of the input / output operation. These functional sections are shown in fig. 5C. In addition, the functional relationships between the I / O translator and the main system (processor and main memory) as well as the LCP processor and the peripheral are also shown.

In fig. 5C, the input / output translator 10t communicates with the processor 10 and the main memory 10m. The I / O translator 10t also communicates with an LCP processor chosen as the line control processor 20oo and the peripheral device 50. A series of control lines in FIG. 5C connects the processor 10 to the initiation module 10ta to the connection module 10tb and to the data transfer module 10lc as well as to the reconnection module 10td.

Initiation module:

The initiation module 10ta accepts the information from the descriptor containing the addresses of the processor 10 and translates the descriptor code OP and assembles the information in a form usable by the LCP processor 20oo- The addresses A and B of the descriptor are stored in the 10ps notepad memory of the I / O translator (fig. 3) having places reserved for each designated channel; the remaining part of the descriptor information is assembled in a register (as shown in fig. 5D) to be subsequently transmitted to the LCP processor 20oo- As soon as the information is assembled in this descriptor information register and the addresses are saved, the contents of the first register are shifted to a second identical register. In this way, the first register can be deleted and the initiation module 10ta is thus free to accept a second descriptor.

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The information contained in the descriptor register of FIG. 5D consists of a number of elements:

a) LCP OP code: these are four mutually exclusive bits which are translated by the I / O translator of the I / O descriptor OP code; these bits tell the LCP processor what type of operations should begin;

b) LCP variants: these are three digits used to pass additional information to the LCP processor and which relate to the operation to be performed;

c) IOT digit: this digit indicates whether data transfers should be prohibited or whether or not data should be translated;

d) rear marker: when this marker is set, it indicates that a reverse operation is taking place;

e) LCP address: this address is decoded from the BF (channel number) of the processor initiation I / O instruction; this domain contains three bits which determine one of the eight LCP basic modules and the other three bits which are used in combination to choose a particular LCP processor in the determined basic module;

f) address C: this is a six-digit address domain C (folder addresses) of the I / O descriptor.

The combination of the IOT digit, the rear marker and the LCP address constitutes the descriptor link (D / L) which is used by the LCP processor to re-establish the connection to the system after a previous cut. When the processor signals to the I / O translator that all the I / O descriptor has been sent, the I / O translator cuts off from the processor and the initiation module 10 places the command on the connection module 10tb.

Connection module:

The 10tb connection module of fig. 5C aims to establish a communication path between a determined LCP processor such as the LCP processor 20oo and the input / output translator 10t. The 10tb connection module decodes the channel number which appears in the processor initiation instruction and which, with the decoded value, chooses a communication path for the LCP basic module such as the 20o module (fig. 1 A ) in which the chosen LCP processor is located. The connection module 10tb then sends the LCP address to the chosen LCP base module, then instructs the base module such as the module 20 to start the hair test.

Hair test:

The Poil test is an algorithm used by the LCP base module to establish the connection between the base module and a particular LCP processor; the Poil test algorithm is a connection which is initiated by the I / O translator (unlike an algorithm called Poil request which is a connection initiated by the LCP processor). As soon as the connection between the LCP basic module and the characteristic LCP processor is established, the basic module such as the module 20o of FIGS. 1A and 2 become transparent for the transfer of data between the LCP processor and the I / O translator. The Poli test algorithm also checks for priority, transmission errors, and busy states, and one of these checks, if successful, may cause the connection attempt to fail.

If the connection attempt is successful, the LCP processor remains connected to the I / O translator 10t until the connection is completed by the I / O translator. The LCP core module plays no other role in communications between the chosen LCP processor and the I / O translator.

During the connection test, certain conditions can be detected, which stop or fail the connection attempt, so that the existing condition is indicated in the IOT result descriptor. The following list indicates the types of conditions that can be detected and indicated:

a) the addressed channel does not contain an LCP processor or the channel's LCP processor is cut off;

b) the LCP processor of the particular channel, addressed, is busy (ie the LCP state is neither 2 nor 3; the use of count state will be described later);

c) the output is busy, that is to say that certain other LCP processors of the basic module are connected to the system 10;

d) the LCP address has a parity error.

When the I / O translator and the distribution control means of the basic module use the Poil test for the connection of a particular LCP processor, if the Poil test results in the connection of this LCP processor, the I / O translator 10t transmits the descriptor link (D / L), the LCP OP code and the variants and address C for the chosen LCP processor. After receiving this information, the LCP processor indicates to the I / O translator 10t that it is either cutting itself, or preparing to start a data transfer. Typically, the write operation (data from the main memory 10m to a peripheral such as the peripheral 50) causes the LCP processor to choose a data transfer request; moreover, a reading operation typically results in a cut.

If a data transfer is requested, the 10tb connection module places the order through the 10te data transfer module. If the LCP processor 20oo is cut, the communication between the LCP 2000 processor and the I / O translator 10t ends until the LCP processor requests a reestablishment of the communication via the reconnection module 10td.

Data transfer module:

In fig. 5A, the data transfer module 10tc is used by the I / O translator 10t to control and direct the flow of data between the LCP processor 20oo which is connected and the main memory 10m. The LCP processor can be in the connected state as resulting directly from the effect of the connection module 10tb or as resulting from the effect of the reconnection module 10td; in each case, the operation of the 10tc data transfer module is the same. When a command goes through the data transfer module 10tc, the addresses A and B of the descriptor are retrieved from the 10ps notepad memory of the I / O translator (fig. 3), because these addresses have been stored in this memory either by the initiation module 10ta or by the data transfer module 10tc (fig. 5C) at the end of a previous data transfer operation. The system requests a memory access and the address A is transferred from the I / O translator 10t by the processor memory address register 10pam into the main system 10 (FIG. 3).

Assuming that a registration operation is in progress (fig. 5C), the data of the memory position indicated by the address A is' sent by Bm to the data transfer module 10to of the I / O translator. As soon as this data is in the module, it is translated (as indicated by the descriptor) and it is used to create a longitudinal parity. Then, this data passes through the bus Bg in the chosen LCP processor, such as the LCP processor 20oo, at the same time as a trigger pulse. When the LCP 20oo processor receives the data, it acknowledges receipt by returning the trigger pulse to the 10t I / O translator.

While the data transfer is carried out from memory 10m by the LCP processor 20oo, the I / O translator 10t increments address A and compares it to address B. As long as address A is less than l At address B, the LCP 20oo acknowledgment pulse requests another memory access and allows the data transfer sequence to continue.

If the buffer memory of the LCP processor such as the LCP processor 250o (fig-2) is filled with data from the memory 10m, the LCP processor indicates to the I / O translator 10t that it is in the process of disconnecting; the I / O translator 101 then restores the address A incremented in the 10ps notepad memory of the I / O translator (fig. 3), then the connection between the I / O translator and the LCP processor is terminated. The LCP processor such as the LCP processor 20flo then begins the transmission of the data via the bus Bp to the peripheral 50; the 10t I / O translator can then freely establish a connection to another LCP processor.

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When transferring the contents of the data buffer memory 2500 to the device 50, the processor 20oo requests a restoration of the data path to the main memory 10m. This recovery is processed by the basic LCP 20o module and the 10t reconnection module of the I / O translator.

To increase the overall speed of the input / output activity (I / O), the I / O translator 10t may alternatively include an IOT multiplexer. This multiplexer allows the I / O translator to process another LCP processor during memory cycles that would otherwise be lost when the I / O translator is busy with any function not using memory.

Reconnection module:

After being connected to the I / O 10t translator and receiving the order descriptor (C / D) and the descriptor link (D / L), the LCP 20oo processor can cut itself off from the system to communicate with its corresponding device such as the device 50. If, under these conditions, the LCP processor subsequently requests access to the memory 10m, it sends a request to the basic module 20o. The algorithm called Poil request is the process by which the basic LCP module (following a request from the LCP processor) attempts to connect the LCP processor again to the 10t I / O translator. The purpose of the 10td reconnection module is to receive the Poil request and restore a data path via the I / O translator 10t.

During the reconnection attempt and cooperation with the base module such as 20o, the 10td reconnection module resolves any priority conflicts that may arise between various LCP processor requests. When the priority problem is resolved, the reconnection module establishes the data path for the LCP processors via the I / O translator 10t. It should be noted that the distribution module module has wired logic to make attempts to reconnect the LCP processor to the 10t I / O translator.

As soon as the data path is restored, the LCP processor brings the descriptor link back to the 10t I / O translator. The descriptor link initially passed through the LCP 20Oo processor during the initial connection sequence. The basic 20o module plays no other role in LCP-IOT communication. Following the transfer of the descriptor link, the reconnection module 10td places the order with the data transfer module 10tc.

The I / O 10t translator must be able to accept, store and modify the addresses of the data field to transfer the data to or from the correct memory positions. Since the main memory 10m can have up to 2 million digits (addresses between 0 and 1999 999) and as the various input / output devices can directly address the 10m memory, the addresses of the data field of the descriptor I / O must be 7 digits long. An address in the data field of the I / O descriptor must be MOD 2 or MOD 4 (MOD is the abbreviation of module); no odd address is allowed. Since odd addresses are not allowed, it is not necessary to have the last significant bit of the least significant digit. In addition, since the most significant digit can only be 1 or 0, one bit is sufficient for the digit position. In view of the above, it is possible to achieve a seven-digit address using 24 bits. The format of an address in the data field of the I / O descriptor is given in table V.

(Table at the top of the next column)

In the address, the digit G can be equal to 1 or 0, the digits G ... F can have any numerical value (0 to 9) and the digit A can have any even decimal value (0 to 8).

As shown in fig. 3, the 10t I / O translator has a 10ps notepad memory. This is shown in detail in fig. 5F. The I / O translator contains 256 words from a notepad memory, each word having a length of 24 bits. As shown in fig. 5F, the notebook memory is divided into five main areas.

Table V

Position of the digit

Bit value

Address of the data field of the I / O descriptor.

Note: H indicates an unused bit which must be zero.

The areas referenced A and B are used to store the start (A) and end (B) addresses of the memory data field; these two addresses are 24 bits long. The areas marked EXRDW 1 and EXRDW 2 are used to store the expanded result descriptors, in which each of the words is 16 bits long. The area referenced temporary storage is used to store the marks indicating the errors detected during the IOT operation.

When the result descriptor is assembled, the information in the temporary storage area is added to any existing result descriptor information. Each of the five main zones is subdivided into 64 individual zones, one for each channel.

Notepad positions are addressed by an eight-bit combination represented by the base module number and LCP number, the end of address mark (address B) and the result descriptor mark, expanded (EXRDW 1 ). The least significant six bits of the notebook address (base module number and LCP number) are derived from the BF part of the processor initiation instruction (BFA = base number, BFB = number LCP processor). The signal EXRDW 1 is created by the I / O translator 10t each time access is requested either to the word of the result descriptor developed or to the temporary storage area.

The expression ADDRESB is created by the I / O translator each time access is requested to address B or to the second expanded result descriptor area.

The elements of the 10ps notepad memory consist of 24 RAM elements (256 x 1) distributed in 64 x 4 x 24 (64 channels, 4 words per channel and 24 bits per word). As shown in fig. 5G, the Bad eight-bit address bus passes to all the RAM memories 600, 60! ... 6024 of the distribution, as does the registration authorization line 68. Each RAM memory element has a line data input and data output line; these various data lines are combined to form the data entry (RAMIN) 70; and the data output (RAMOUT) 70o.

When the notepad address is applied to the distribution and the registration authorization order is made active, the IOT address bus data is written to the RAM elements. To read from the notepad, you must indicate the desired position by the address of the notepad and the read authorization order must be implemented. The requested data is then transferred from the notebook to the IOT address bus.

Registration of an address:

During the execution of the I / O initiation instruction, the processor 10p assembles the start address (A) and the end address (B) of the data field. Then the processor transfers the full address A from the processor register 10pr to the IOT address bus. At the appropriate place in the IOT initiation sequence, the I / O translator creates the appropriate signals, then controls the module bits by gate

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base and those from LCP processor address to 10ps notebook memory. When the position of the channel of the notepad is addressed and the order authorization to register is active, the address A can register in the notepad. Then the processor 10p places the end address (B) in the IOT address bus, then again the I / O translator creates the appropriate control signals as well as the base module and the address of the LCP processor. However, at this time, the IOT translator also creates ADDRESB, so that the bus address is written in the address area B of the notepad memory (fig. 5F). The start and end addresses of the data field are then stored at the channel address in the 10ps notebook memory. When the data transfer operation begins, access to the positions of the notepad memory is obtained by the data transfer module 10tc (fig. 5C).

Message level interface:

As previously described in relation to FIG. 2, the basic module LCP 20o is characteristic of the basic modules in that each separate basic module comprises a distribution card 20od which serves up to eight LCP processors. In addition, each LCP basic module includes a maintenance card such as 20om and a termination card 20ot.

The distribution card of each LCP base module provides the interface between the LCP base module and the input / output translator 10t of the main system 10. As shown in FIG. 2, the message level interface 15 gives a channel to the I / O translator 10t from each basic LCP module via 25 lines. These lines are shown in fig. 5E. The functions of each of the lines identified separately are listed in Table VI.

TABLE A U VI (see also fig. 5E)

Signal name Description

ADDSEL Address selection. This signal, when set

work, indicates that the I / O translator is connected or is trying to be connected to a particular LCP processor. As soon as the connection is made, the LCP processor remains connected until the IOT translator drops ADDSEL.

AG + SIO Access is guaranteed or triggered I / O. If the LCP processor is not connected, this signal indicates that the LCP processors are requesting that a new connection be assigned and they start the Hair request algorithm. If an LCP processor is connected, this signal is the acknowledgment of receipt of information from the I / O translator or the triggering of information transmission.

TRM + MC End or Master evacuation. If no LCP processor is connected, this signal evacuates all LCP processors that are online. If an LCP processor is connected, this signal terminates the connected LCP processor.

LCPST LCP trigger. If an LCP processor is connected, this signal is the acknowledgment of receipt of information from the LCP processor or the initiation of the transmission of information. This signal is also used by the distribution card as acknowledgment of receipt during the Hair test or the Hair request.

ER + ST8 Emergency request or state 8 LCP. When this signal is activated by an unconnected LCP processor, it indicates that this LCP processor requests immediate access to the I / O translator. If activated by the connected LCP processor, this signal indicates that bit 8 of the LCP state is set.

IP + ST4 Interrupt request, test Parity error hair or state 4 LCP. When this signal is activated

by an LCP processor not connected, it indicates that the LCP processor requests access to the memory, that is to say that the LCP processor requests a new connection. If activated during a connection sequence of an initiated system (Hair test), this signal indicates that a parity error was detected during the Hair test. If activated by a connected LCP processor, IP + ST4 indicates that bit 4 of the LCP processor status is set.

PB + ST2 Busy port or LCP 2 status. When detected during the Hair test, this signal indicates that the basic LCP processor is active. If activated by a connected LCP processor, PB + ST2 indicates that bit 2 of the LCP state is set.

CS + STI Selection of channel or LCP status 1. When activated

by the I / O translator and is transmitted to a basic LCP processor, this signal indicates channel selection and that a connection or an reconnection attempt has been started. If activated by a connected LCP processor, CS + STI indicates that a bit 1 of the LCP state is set.

PARITY Parity. This bidirectional line carries parity

adequate (odd) for information on 16 data lines.

DATA xn Data lines (x = A, B, C, D; n = 1,2,4, 8).

In this unconnected state, the 16 bidirectional lines are used for addressing and priority resolution in connection or reconnection attempts. In this connected state, the lines are used for the transfer of data between the I / O translator and the LCP processor.

The message level interface 15 (MLI), which is formed by 35 25 signal lines connecting the distribution board such as the board 20od of a particular LCP basic module such as 20o to the I / O translator 10t, ensures that the signal discipline presented to the I / O translator is a classic discipline whatever the logic and operation variations encountered in the various types 40 of LCP processors. It should be noted that some of the PWM signal lines 15 shown in FIG. 5E are bidirectional lines and are assigned to multiple functions depending on the signal source and the state (connected or disconnected) of the LCP processor.

The distribution card 20od of a given LCP basic module is used to provide part of the message level interface between the I / O translator and the various LCP processors of the basic module. This distribution card also plays the role, in combination with the IOT 10tb connection module, which consists in establishing a data path to a determined LCP processor (Poil test) and, when requested by an LCP processor, it cooperates with the IOT 10td reconnection module to establish a path from this particular LCP processor to the I / O translator (Hair request).

55 LCP state counts:

While a particular LCP processor is connected, there is a standard communication procedure with the I / O translator. Although the sequence of events followed during the communication procedure may not be the same for all 60 LCP processors, the events that occur at a point in the sequence will be identical. The phases of the sequence which are numbered 0 to 15 are called counting states and are transmitted to the I / O translator. The I / O translator examines the counting states each time it receives a trigger pulse from a 65 LCP processor and, depending on the counting state, it ensures the correct operation. A more detailed description of the sequence and use of the count states will be given later. Fig. 6A is a diagram showing the various counting states and the

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corresponding logical sequence. Detailed explanations of this logic and counting states will be given later.

LCP basic module background:

A local common background is provided in each of the basic modules LCP 20o, 2QU 202, etc. Each background connects all eight LCP processors in the base module. This background is made so that all the signal lines lie along the length of this element, so that all the lines are available for all the processors of this basic module. From each position of an LCP processor, these background lines fall into two general types:

a) those going to the distribution card and to the I / O translator,

b) those going to the maintenance and termination cards.

With the exception of the various voltage and clock lines, those connected to the maintenance card (such as for example 20om in fig. 2) are used for local maintenance functions and those off-line.

Among the lines that go to the distribution card, and those that go to the I / O translator, some, such as the parity data lines, must pass through doors to go to the various LCP processors. This door function is authorized only when the LCP processor is in the connected state; when the LCP processor is disconnected, the door is prohibited. The LCP processor is in the connected state when it can transfer data between the I / O translator and itself. The disconnected state of the LCP processor is that in which the LCP processor is disconnected from the I / O translator, but can transfer data between itself and its peripheral unit.

In addition to the door lines, there are lines that are assigned to each separate LCP processor, for example the line from the distribution board to a single LCP processor. Lines that do not require gates are used for signals such as LCP reconnection requests or LCP address lines.

While an LCP processor is connected to an IOT translator, this LCP processor only accesses the background of the base module. This is done during the connection time, when there is an IOT-LCP data transfer. At the end of the data transfer, the LCP processor cuts off both the IOT translator and the background of the basic module to free it up and allow its use by other LCP processors in the system. Once disconnected, the LCP processor is free to communicate, via the front plane, with the corresponding peripheral such as the device 50. When a disconnected LCP processor requires the re-establishment of the connection of the I / O translator, this processor LCP sends a request signal through the background lines which are assigned to the distribution card such as the 20 ^ card. The reception of the LCP request causes the distribution card to start the Poil request algorithm and initiate the IOT 10td reconnection module (fig. 5C).

Line order processor:

An LCP line control processor is a device that serves as an interface unit between a specific peripheral device and the main system. There are various types of LCP processors,

each one being designed to cooperate with a particular type of peripheral device. As the peripheral devices are different in terms of their operating characteristics, the LCP processor is designed so as to process, control and in particular be adaptable to its own peripheral device. However, there are some general characteristics of an LCP interface unit which are common to all LCP processors. Basically, the common characteristics of each LCP processor are: the possibility of transforming serial data into parallel data or of transforming parallel data into serial data, the possibility of transforming a character format into a word format or transform a format of a word into a character format; recognize and take appropriate action in response to certain normal command or signal characters.

Fig. 6B shows a generalized block diagram of a line control processor, this figure also showing the relationship between the distribution card unit 20od and the I / O translator 10t. If the LCP processor is assumed to be in the connected state and if a registration operation has been started, the data of the I / O translator 10t enters the LCP processor through the background receivers 23r. Then the 24xl multiplexer is used to choose the operating data source which, in this case, is the 10t I / O translator.

The output of the 24xl multiplexer passes through conductors to both the 24W LPW (longitudinal parity word) circuit as well as to the 24x2 multiplexer which allow the data from the 24xl multiplexer to pass through the data buffer 2500- The LCP processor continues to receive data from the I / O translator 10t until the data buffer 2500 is filled.

In the period when the LCP processor receives data, the LPW circuit 24w creates the sum LPW; then, at the end of the transmission, the I / O translator 10t sends a longitudinal parity word (LPW) which, if there is no error in the transmission, erases the LPW 24w circuit. If the 24w circuit does not disappear, this corresponds to an error.

When the data buffer 2500 is full, the LCP processor cuts off from the main system (IOT) by prohibiting its control circuits of background transmitter 23x and background receivers 23r; then the LCP processor establishes a data path towards the peripheral, such as the device 50, by authorizing its control circuits of forward plane transmitter 28x and front plane receivers 28r. As soon as this path is established, the LCP processor uses the multiplexer 27x to choose the data (translated or untranslated data) from the data buffer memory 2500 to transmit it to the peripheral device 50. The transmission continues until the data buffer 2500 is empty and, at this time, the LCP processor requests a reconnection (for the I / O translator) either to store a result descriptor or to request other data.

If the read operation is in progress and the LCP processor is cut off from the main system (IOT), the data of the peripheral device 50 enters the LCP processor via the forward plan receiver 28r. The output of the receiver 28r passes through the multiplexer 24xl which then chooses the peripheral device 50 (via the front plane receiver 28r) as the data source. The output of the 24xI multiplexer short-circuits the 24W LPW circuit and passes to the 24x2 multiplexer which chooses the 24x multiplexer | as input signal to the buffer memory 2500. When the data buffer memory 2500 is filled, the front plane receivers 28r and the front plane control circuits 28x are prohibited; then the LCP processor reconnects to the I / O 10t translator; the receivers 23r and the control circuits 23x of the background are then authorized.

The LCP processor then begins the transmission (to the main system 10) for the data from the intermediate memory 2500 via the multiplexer 27x and the control circuit 23x, to the I / O translator 10t. During this transmission, the output signal from the multiplexer 27x then passes through the multiplexer 24xi in the LPW circuit 24w. Then the intermediate data memory 2500 becomes empty, the LCP processor sends a signal to the I / O translator 10t indicating that the longitudinal parity word LPW arrives, then it controls the gates for the final sum LPW via the multiplexer 27x and from the 23x control circuit, to the 10t I / O translator.

After the transmission of the longitudinal parity word LPW, the LCP processor can either disconnect from the main IOT system to receive additional data from the peripheral device 50 or, if there is no other data, the LCP processor can store a result descriptor and go to the free state.

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In the operations described above, the information data may have been transferred between the LCP processor and the peripheral device in the form of bits, characters or words, depending on the peripheral device concerned. The data transmission process is typically controlled by the type of peripheral devices used.

Typically, the information data is transferred between the LCP processor and the I / O translator 10t in the form of words with, in some cases, character transfers such as, for example, the first and last character of a transmission. This data is transferred between the I / O translator 10t and the LCP processor of FIG. 6B and are controlled by the exchange of trigger pulses, and the recognition is done by the I / O translator 10t of the LCP processor of counting state.

As previously indicated in relation to FIG. 6A, the counting state of the LCP processor gives standardized information which is transmitted to the I / O translator 10t and which allows this I / O translator to take the following appropriate measures according to the information concerning the counting state .

While an LCP processor is connected by the main system, it follows a normal communication procedure with the 10t I / O translator. Although the sequence of events followed in the communication procedures may not be the same for all LCP processors, the particular events that occur at any point in the sequence of the communication procedure are all similar. The phases of the communication sequence, numbered 0 to 15, are called counting states and are referenced STC. These counting states are transmitted to the I / O translator 10t which examines the counting state (STC) each time it receives a trigger pulse from the LCP processor and, depending on the counting state, the I / O translator O can take appropriate action.

According to fig. 6A and Table VII, it can be seen that each counting state has a particular function and, moreover, depending on the type of LCP processor and descriptor concerned, the counting state has different outputs. Table VII briefly describes the various LCP count states.

TABLE VII Counting status Description STC = 0 Master erase.

STC = 1 Logout. The LCP processor communicates with its peripheral device. STC = 2 Not ready. The LCP processor is free. The device is not ready. The LCP processor can receive information describing the system.

STC = 3 Ready. The LCP processor is free. The device is ready. The LCP processor can receive descriptor information from the system. STC = 4 Ready. The LCP processor transmits data from its buffer to the system. STC = 5 Emission of the descriptor link. The LCP processor issues the descriptor link to IOT to reestablish the connection. STC = 6 Reception of the descriptor link. The LCP processor receives the descriptor link from the I / O translator during the I / O connection sequence.

STC = 7 Result descriptor. The LCP trans processor puts its result descriptor at the I / O translator. STC = 8 Registration. The LCP processor receives data from the system.

STC = 9 Coded state. One character is transmitted; the LCP processor sets the bit Dl (fig. 4C, result descriptor) as a reference for the I / O translator. The I / O translator decrements the address by 2.

TABLE VII (continued)

Counting status Description

STC = 10 Registration of one more word. The LCP processor data buffer can store only one more word. STC = 11 I / O descriptor LPW. The LCP processor receives and controls LPW for the I / O descriptor received in STC = 2 or STC = 3.

The I / O descriptor, after having been translated by the I / O translator, becomes the order descriptor. STC = 12 Interruption. There is no more data to transfer.

The LPW processor is transmitted and is checked. STC = 13 Authorization to break. The transferred data have been retained; the LCP processor requests a return to STC = 8 (registration) or STC = 4 (reading).

STC = 14 Character transfer. The last communication consisted of a character instead of a word. STC = 15 LPW result descriptor. LCP processor

sends the LPW for the result descriptor to the I / O translator.

According to fig. 5C, the processor 10p begins the input / output chain operations by the execution of an I / O initiation instruction. Under these conditions, the processor passes certain information comprising the channel number of the LCP processor through the I / O initiation module 10m of FIG. 5C. The channel number is decoded to determine the number of the base module and the address of the LCP processor which then passes through the connection module 10tb. The connection module then chooses the appropriate LCP base module and sends a signal (channel selection) to the appropriate distribution card, such as the 20od card for the base module such as 20o, requesting that a connection attempt be done. The operation described above is called the Hair test and is a way for the main system to find the connection on an LCP processor; furthermore, this constitutes a process by which the distribution card 20od, in response to the connection request, also attempts a connection to a particular LCP processor.

Following the transmission of a channel selection command, the I / O translator 10t sends the address of the desired LCP processor to the distribution card of the selected base module. At the same time, the I / O translator sends the address selection command to all the basic modules of the system. The distribution board which receives both the address selection and the channel selection starts a Poli test and responds to the I / O translator with an LCP trigger; distribution cards which only receive the address selection command consider it as a busy signal and are prevented from communicating with the I / O translator. When the I / O 10t translator receives the LCP trigger signal, it drops the channel selection order.

When the distribution card receives an address selection and channel selection command, it creates a signal which authorizes the LCP address to be placed in the LCP address register of the distribution card. The output signal BCD (binary signal in decimal coding) from the address register LCP is decoded to authorize one of the eight lines. Each line represents an LCP processor of the basic module. When an LCP processor finds that its address line is active, this LCP processor responds to the distribution card, the LCPON signal signifying LCP connected. When this signal is received in the distribution card, a connected flip-flop (CONF) is set to the state. Then, depending on the state of the I / O transmission line (IOSND / fig. 6C) of the connected LCP processor, this results in the activation of the control lines either for data reception or for transmission data, as between the LCP processor and the I / O translator (fig. 6C).

When a distribution card detects the absence of the channel selection order, it responds to the I / O translator with the LCP state accompanied by a trigger signal. The LCP processor is

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then connected to the I / O translator and remains connected until the I / O translator cuts the address selection order. The distribution card no longer participates in other IOT / LCP communications.

The above events show the phases leading to a successful connection attempt; however, the connection attempt may have failed for one of the following reasons:

a) there is no LCP processor at the addressed location or the LCP processor at the addressed location is off;

b) the LCP processor is active, that is to say that the LCP counting state is not 0 or 2 or 3;

c) the channel is active, that is to say that a second distribution card of the basic module is active;

d) a parity error was detected in the address.

The detection of one of these errors causes the connection attempt to fail and a result descriptor corresponding to this failure is sent to the main system 10mr to be written in the memory 10m (fig. 3).

During the following description, reference will be made, where appropriate, to particular flip-flops and signal levels, which are not indicated in particular in the block diagrams. As the production and use of such elements are known, the description will not be repeated, for the purpose of simplification.

Hair request:

An LCP processor, after having been connected to an I / O translator 10, and having received the order descriptor and the descriptor link, can cut itself off from the main system 10, to communicate with its corresponding peripheral device such as the device 50 If, subsequently, the LCP processor requests access to the 10m memory, it sends a request (LCPRQ) via the distribution card. The Poil request is a process allowing the distribution card to attempt to reconnect the LCP processor to the I / O translator, in response to an LCP request. A certain number of events occur during this mode of operation in Hair request.

When several LCP processors of the basic module 20o simultaneously request access, the distribution card 20, ^ determines which of them will have access, by checking their priority level; thus, the LCP processor which requests and has the highest priority level (this priority is chosen as installation time) accesses the distribution card. This priority level is called basic priority since it concerns the LCP processor which has the highest priority level among the eight LCP processors of the basic module.

As soon as the basic priority operation is processed, the distribution card assigns a global priority (which was also assigned and chosen at the time of installation) to the LCP processor making the request. The global priority establishes the priority rank between the various basic modules of the whole system, compared to the priority ranks of the LCP processors of a single basic module. The 20od distribution board contains a series of pins or socket connections which are connected to each LCP processor. These pin and socket connections can be linked to a priority encoder which assigns an internal basic priority number ranging from 0 (lower level) to 7 (higher level) for each LCP processor. Thus, when there are several LCP processors of the same basic module which simultaneously request the connection, the distribution card controls and chooses the LCP processor having the highest priority.

Another set of pin connections on the distribution board is connected to each LCP processor. These connections are handled by a specialist so that each LCP processor receives an external or global priority number to allow the input / output translation interface of the main system to choose, among the LCP processors, the one found in different modules. basic system. Thus, when a global priority number is received by the I / O translator, and there are simultaneous requests from other LCP processors and other basic modules, the I / O translator chooses that of the processors LCP with the highest global priority number; this is only done after solving the internal base priority problem using the distribution board.

These distribution cards which receive requests from their associated LCP processor each send an interrupt signal (IP + ST4) to the I / O translator 10, (see the message level interface FE and table VI, fig. 5E). Then the I / O 10 translator, detects the IP + ST4 signal and begins the reconnection sequence and sends a guaranteed access signal to all the basic modules of the system. The guaranteed access signal causes the distribution boards which send the IP + ST4 signal to the I / O translator 10 to start their Poil request algorithm.

In response to the guaranteed access signal, the distribution cards making the request send their individual overall priority to the I / O 10 translator. The I / O translator compares the global priorities of the distribution cards which make the request (i.e. sends the channel selection signal by the distribution card which makes the request and which has the highest overall priority , at a later rate) and the I / O translator sends an address selection signal to all the distribution boards in the system. The distribution card which receives both the channel selection and address selection signal responds to the I / O translator with the LCP trigger signal, then sets its LCP address flip-flop to state, thereby controlling the specific address line of the LCP processor making the request. When the LCP processor finds that its own address line is active, it responds to the distribution card with the connected LCP signal (LCPCON).

When the LCP trigger pulse is received, the I / O translator 10 cuts the guaranteed access signal and the channel selection signal; when the distribution card detects the absence of the guaranteed access and channel selection signal, and when it detects the presence of the LCPCON signal, it then assumes that a connection must be established and responds to the I / O translator with a pulse of LCP triggering accompanied by the LCP counting state and the descriptor link.

The Hair request is then finished; the distribution card is no longer excessively involved in LCP-IOT communication. The LCP processor and the I / O translator continue the reconnection sequence until the LCP processor is connected and, after that, control passes to the data transfer module 10, c of the I / O translator. The LCP processor remains connected until the I / O translator cuts the address selection signal.

Error checking:

Each transmission between the I / O translator and a particular LCP processor is checked for errors. The error checking procedures used are as follows:

a) verification of the vertical parity of each word transmitted;

b) verification of the longitudinal parity of each transmitted block.

a) Vertical parity:

In read operations, the LCP processor sends information to the I / O translator 10t on 16 lines of message level interface (MLI) data (fig. 5E) accompanied by a parity bit on the MLI parity line ( fig. 5E). The data and parity lines go to the parity controller-generator of the IOT basic control circuit board. In read operations, the parity controller-generator is used to count the number of bits 1 on the PWM data and parity lines. If the total number of bits 1 (containing the parity bit) is odd, then the parity is correct and a signal term PAROK is created (fig. 6D). If the total number of bits is even, the PAROK signal is not created; the absence of the PAROK signal when the data is received causes the I / O translator to set the vertical parity error flip-flop (VPERRF) to the state.

Similarly, the recording operations of the 16 data lines of the main system 10 pass through a controller.

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parity generator of the IOT basic control circuit board. The data of the 16 lines is examined and, if there is an even number of bits 1, the circuit creates the signal PARGEN. This PARGEN signal is then used to force a status bit 1 in the message level interface parity line to accompany the data to the LCP processor. On the LCP basic distribution board, the state of the parity bit controls the parity controller-generator circuit. The parity controller-generator circuit examines the states of the 16 data lines and creates a PAROK signal, if the total number of status bits 1, including the parity bit, is an odd number.

b) Verification of the longitudinal parity:

Longitudinal parity checking is an error detection method in which a verification word, created by a transmitting unit, is compared to a verification word created in the same way by a receiving unit. Verification words are created by treating each word in the transmission as a 16-bit number, then preforming an OU-EXCLUSIVE operation (by adding binary sound report) of each word in the transmission. At the end of the transmission, the transmitting device or transmitter sends the verification word which it has assembled by the receiving device. If there is no error in the transmission, the addition of the verification word by the transmission device to the verification word of the receiving device gives a sum of 0. Thus, if the sum is not not equal to 0, a longitudinal parity error flip-flop is identified (LPERRF).

As indicated in relation to fig. 6B, the LCP processor has a 24W LPW circuit. Similarly, there is a longitudinal parity check circuit in the 10t I / O translator. This circuit connects a path parallel to the data bus represented by the 16 lower lines in FIG. 5E.

The line control processor (LCP), such as the 20Oo element, is better understood if we refer to FIG. 6C which represents a basic block diagram of the main elements concerned by the addition of certain characteristic details for the RAM buffer memory such as 2500 of the LCP processor 20oo-

The LCP 250 buffer is a random access memory (RAM) which comprises 256 bits (0-255) and a depth of 18 bits. We can thus write 256 words of 18 bits. According to a characteristic embodiment, the buffer memory 2500 can have a buffer section A 25a having 90 longitudinal words of 18 bits each; another section is designated by 25xl; the section of the order descriptor C / D bears the reference 25c; a buffer zone B 25b can typically have a length of 90 words (that is to say from address 128 to address 218); another buffer zone bears the reference 25x2; the R / D result descriptor area bears the reference 25r; another zone is marked 25x3; the area of the descriptor link D / L bears the reference 25d.

The RAM buffer 2500 is addressed by a memory address register 36 having a system address register section 36s and a device address register section 36d which communicate with the buffer memory 2500 via '' an 8-bit address bus B8. The RAM 2500 buffer is functionally composed in the vertical direction (fig. 6C) of 16 bits and a parity bit with an eighteenth bit called the end mark bit, the end mark bits being in the storage section marked 25e.

A data bus 47 provides the data input and output channel for the buffer 2500 to communicate with the main system 10 through the system interface logic 21si; the buffer memory 2500 communicates with its peripheral unit via the interface 22di. The interface logic 21si of the system, the interface logic 22di of the device and the common logic 22c are represented schematically by blocks which relate to more specific elements described in relation to FIG. 6D.

Fig. 6F represents a message block of the type used in the LCP 2500 buffer memory of FIG. 6C. As indicated in the description of FIG. 6C, for the RAM 2500 buffer, it is a message block characteristic of n words; this block provides 90 words (or n = 90) of data storage; we can also have three words for the R / D result descriptor; one can have three word positions for C / D order descriptors as well as one word position for C / M order messages.

Fig. 6F also shows a basic word format, in which a word is made up of four digits, namely: A, B, C and D,

plus one parity bit referenced VPB (vertical parity bit), which makes a total of 17 bits per word.

As shown in fig. 6F, the four digits A, B, C, D are each formed by 4 bits called bit 8, bit 4, bit 2 and bit 1.

In fig. 6C, the buffer memory 2500 also has an eighteenth bit or end marker bit, which is placed at the location referenced 25e in FIG. 6C.

The main or central system 10 communicates with the peripheral terminal unit via the LCP processor. The LCP processor provides means for transferring transfer control information and data from the main system 10 to the peripheral terminal units such as 50 and vice versa. The LCP processor examines the C / D order descriptor coming from the main system 10 and puts itself in a state to perform the necessary operations, if it detects a particular order. It also transfers the same C / D order descriptor, unmodified, to the peripheral unit. The peripheral unit acts on the C / D order descriptor and brings the R / D result descriptors back to the main system 10 via the LCP processor. The message block and word formats are shown in fig. 6F. The C / D characteristic order descriptors and the R / D result descriptors will be described later.

The LCP processor accepts the C / D order descriptor transmitted by the main system 10. The C / D descriptor contains a digit of an OP code, 3 variant digits and 6 C address digits. The order descriptor C / D is received by the LCP processor via 4 digits per transmission for a total of 3 words (4 digits per word). The two least significant digits all contain zeros.

For each word, there is a vertical parity bit (VPB) and the entire C / D descriptor is followed by a longitudinal parity word (LPW). If a parity error is detected in the transmission of the C / D descriptor, the LCP processor switches to the R / D result descriptor mode and reports a description of the error to the main system 10.

The random access buffer memory (random access memory) 250 (RAM of the LCP processor) constitutes an intermediate memory for the whole of the order descriptor, the vertical parity bit and the longitudinal parity word of the LCP processor, the control processor. line.

The LCP processor examines the first word of the C / D order descriptor and determines whether one is in operation called by convention ECHO OP, HOSTLOAD OP, or OP (FIN) READ NO. If there is one of these operations, an appropriate marker is put.

Descriptor link (D / L):

After receiving the C / D order descriptor, the LCP line command processor accepts the D / L descriptor link. It is a two-word transmission followed by a longitudinal parity word LPW. If there is an error, the LCP processor switches to R / D result descriptor mode and reports the descriptor error to system 10.

The intermediate random access memory RAM 2500 acts as intermediate memory for the whole of the descriptor link D / L, the vertical parity bit (VPB) and the longitudinal parity word LPW.

Disconnection mode:

After receiving the D / L descriptor link, the LCP processor goes into disconnected mode.

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Reconnected mode:

If there is an ECHO OP operation, the LCP line command processor goes into reconnected mode and starts operating in ECHO OP, which means receiving two intermediate data sets (each of 180 bytes, or 90 words of 16 bits) and retransmits the same data to the 10m system memory.

If there has been an operation other than ECHO OP, the LCP processor examines whether the peripheral terminal unit is ready. If the peripheral terminal unit is in the not ready state, the LCP processor connects to the R / D result descriptor and reports this to the system 10.

If the peripheral terminal device is ready, the LCP processor begins to communicate the C / D order descriptor to the peripheral while at the same time it plugs into the free state to make itself available for a possible operation of conditional deletion. The LCP line command processor stops in this free state until one of the following two events occurs:

1. The peripheral terminal device puts the LCP line command processor into state for the data transfer state.

2. The system 10 communicates an operation order of conditional deletion or unconditional deletion.

If situation 2 above occurs, the LCP line command processor accepts a word from system 10, followed by the longitudinal parity word LPW, and the LCP processor determines if there is a valid, conditional delete operation. In all cases, the LCP processor communicates the information to the peripheral terminal device. If the situation corresponds to case 1 above, the LCP processor goes back to the disconnected state; in this state, the data transfer can be made between the LCP processor and its peripheral terminal device.

After the transmission of the C / D order descriptor to the peripheral terminal, the LCP processor is controlled by the state of the peripheral terminal which defines the operating mode and the memory requirements. The data is transferred in message blocks with a longitudinal parity word (LPW) of 16 bits following each block and a parity bit for each word (with the exception of the disk packet controller situation, the message block is formed by a segment). When the LCP line command processor detects an error in the data received from the peripheral terminal or from the main system 10, it reports this information to the peripheral terminal and starts on the R / D result descriptor word and informs the main system 10.

In read mode, data transfer between the LCP line control processor and the peripheral device depends on the requirements of the peripheral device. The transfer of data between the LCP processor and the main memory 10m depends on the speed of access to the memory of the main system 10. As the peripheral can work in flow mode and that the LCP processor must compete with others LCP processors to access the memory, the above LCP processor alternates between these two buffer zones to adapt the transfer speed of the peripheral terminal.

Table VIII indicates some types of C / D order descriptors used for the LCP processor. All the other C / D descriptors are transparent to the LCP processor and pass through it to go to the peripheral terminal:

TABLE VIII

Order descriptors:

The LCP processor is transparent to all order descriptors except the following descriptors determined by testing the first word of the C / D descriptor:

1. ECHOOP (bit Al is true).

2. HOSTLOAD (A4 and B8 are true).

3. READ NO T / O (end of time) (A8 and B8 are true).

4. CONDITIONAL DELETION OP (A2 and B8 are true).

5. UNCONDITIONAL DELETION OP

The OP code digits of the C / D descriptor are defined as follows: Reading (A8): Any operation in which the data is transmitted from the LCP buffer memory to the main system (1000).

Registration (A4): Any operation during which data is transferred from the main system memory to the buffer memory of the LCP processor (0100).

Test (A2): Any operation during which no data transfer occurs between the LCP processor and the system memory, but results in R / D storage in the system memory (0010).

Echo (Al): Operation which results in the reception of a message block from the system memory and the transmission of the same block to the system memory (0001).

Normally, the R / D result descriptors are created by the peripheral unit and are accepted by the LCP processor in the form of one, two or three words. When the LCP processor only creates an R / D descriptor, a word is sent to the main system 10. Table IX shows the conditions applied to the LCP processor to create a result descriptor:

TABLE IX

Result descriptors:

Bits

Condition

AT 8

Not ready

A4

Descriptor error

A2

System vertical parity error

Al

System LPW error

B8

End of time

B4

Remote device vertical parity error

B2

Remote device LPW error

B1

(Empty)

According to fig. 6C, for the lines between the interface 22di and the peripheral terminal, there can be, on the peripheral terminal, a channel interface produced in the form of a channel-dependent interface (called DDP interface) 50d which is adapted to the specifications of each given peripheral terminal.

The LCP processor communicates with the peripheral terminal via the DDP device, in asynchronous mode. The registration operation is a transfer in which the LCP processor registers in the peripheral terminal. The read operation is a transfer during which the LCP processor reads in the peripheral terminal.

According to fig. 6C, the line referenced HTCL / is the host transfer command level line; when the LCP processor registered in the peripheral terminal, the signal is that of an asynchronous level which signifies the presence of data in the data lines. This level is deactivated by the peripheral terminal which sends a DML / (peripheral message level) or DINTL / (peripheral terminal interrupt level) command to the LCP processor.

When the LCP processor reads data from the R / D result descriptor of the device, this HTCL / signal is the asynchronous signal sent by the LCP line control processor indicating that it has received the data through the data lines. On receipt of this level, the peripheral terminal must be deactivated according to DML / or DINTL / commands. When the peripheral terminal creates DML / or DINTL / deactivation, the LCP processor ensures HTCL / deactivation.

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When the peripheral terminal controls the LCP processor in C / M order message mode, the host transfer command level HTCL / is sent to the peripheral terminal when the LCP processor buffers are empty and no end of system has been detected. The peripheral terminal must respond to the HTCL signal / by DINTL / and a change of state.

The line in fig. 6C which is referenced HINTL / is the host interrupt line and is used by the LCP processor to indicate to the peripheral that the LCP processor wishes to interrupt the operation. The response at this level by the device must be DINTL / and a change of state; the LCP processor responds to this signal by disabling its HINTL / host transfer control level. Following the detection of the trailing edge of the HINTL / signal, the LCP processor responds to the new operating mode described by the status line shown in FIG. 6C under the references ST-4 /, ST-2 /, ST-1 /.

When a system interrupt 10 is activated in registration mode, the host interrupt level HINTL / signifies that the last data word has been transmitted and that the LPW signal is in the data line of bus 47. It is not the peripheral terminal does not have to respond to the interruption with a DINTL / signal or a change of state.

In read mode, when the LCP processor detects the order to stop reading, it activates the host interrupt level HINTL /. In C / M order message mode, the LCP processor activates the host interrupt level HINTL / upon detection of a read completion command.

The line in fig. 6C which bears the reference HCL / relates to host erasure which indicates to the peripheral terminal that the LCP processor has been erased by the main system 10 or that a parity error has occurred during reading.

The combination of host transfer control level and host interrupt level (HTCL / -HINTL /) indicates to the peripheral unit the presence of a C / D host load order descriptor . The peripheral terminal responds by activating the line referenced DINTL / (peripheral interrupt level) and the counting state ST = 2; the LCP processor acknowledges receipt by deactivating the two levels of HTCL / -HINTL /. Following the trailing edge of the DINTL / signal, the LCP processor transfers the data in registration mode.

In fig. 6C, there is a bidirectional data bus Bd having 16 data lines and a parity line between the LCP processor and the peripheral terminal. When these lines are controlled by the LCP processor, they are in the active state as long as the HTCL / host transfer command level is active. When the command is provided by the peripheral terminal, these lines are activated as long as the message level of the peripheral terminal DML / is active. The direction of transfer is determined by the state of the peripheral terminal. The line referenced DML / relates to the message level of the peripheral terminal and is a unidirectional line. When the LCP processor reads data or an R / D result descriptor from the peripheral terminal to the LCP processor, the message level of the peripheral terminal DML / is used as a transit signal to indicate the presence of stable data in the lines of data. When the peripheral terminal receives a C / D order descriptor or data from the LCP processor, this DML / signal is used as the level of acknowledgment of receipt of the data.

The peripheral terminal (via the interface channel) uses the DINTL / signal (peripheral interrupt level) to request the LCP processor to change the operating mode. This is done by activating the DINTL / signal and presenting the appropriate status in the ST-4 /, ST-2 / and ST-1 / status lines. The status lines must be stable during the activation time of the DINTL / signal.

Registration method:

The DINTL / level is an acknowledgment level for the HTCL / host transfer control level and the LPW data word; moreover, it constitutes the response to the HTCL / or HINTL / signals in the C / M order message mode. The DINTL / signal produces a change of state. When the LCP processor registers in the peripheral terminal, the interrupt level of the peripheral terminal DINTL / is based on the leading edge of the signal HTCL / or HINTL /. The DINTL / signal is deactivated by the trailing edge of these signals (HTCL / -HINTL /).

Reading mode:

The peripheral interrupt level DINTL / is a transfer trigger without data, used exclusively to modify the states; the DINTL / signal is received by the HTCL / host transfer control level / in read mode. When the LCP processor reads in the peripheral terminal, this terminal activates DINTL / in place of the peripheral message level DML / and deactivates DINTL / when the peripheral terminal detects the leading edge of the host transfer command level HTCL /.

Host loading mode:

This mode concerns the transfer or loading of data from the peripheral terminal such as 50 (fig. 6C) in the LCP processor (host) for the reading mode and vice versa for the registration mode.

The interrupt level of the peripheral terminal DINTL / is the level of acknowledgment of reception of the signals HTCL / -HINTL / as host load order. The peripheral terminal activates DINTL / and goes to state 2 (table X). The LCP processor acknowledges receipt by deactivating both HTCL / -HINTL /, and this in registration mode; it begins writing to the memory of the peripheral terminal. To interrupt this operating mode, the peripheral terminal 50 activates DINTL / in the same way as in normal registration mode.

State of the lines:

In fig. 6C, the unidirectional lines ST-4 /, ST-2 / and ST-1 / indicate to the LCP processor the state of the peripheral terminal and, from there, the LCP processor determines the type of operating mode which is requested. For example, according to a characteristic embodiment, eight states 0-7 are provided as shown in Table X, which the peripheral terminal can use to indicate the following conditions: the peripheral terminal is not online; read operation; registration operation; result descriptor; C / M order message; processor clock reset, LCP, (RT); loan or registration order descriptor (C / D); last word in a block or result descriptor and longitudinal parity word (R / D-LPW) to be transmitted immediately.

A characteristic coding system for the status lines of a characteristic peripheral terminal is shown in Table X. f Table at the top of the next page)

The interface discipline between the LCP processor and the peripheral terminal via the terminal channel interface (DDP 50d, fig. 6C) can again be locked in read mode or registration mode.

Reading mode:

When the LCP line command processor reads in the peripheral terminal (state = 1 +7), the peripheral terminal (such as terminal 50 in fig. 6C) places a word in the data lines and activates the message level of DML / peripheral terminal. The LCP processor acknowledges receipt of this situation by activating the host transfer control level (HTCL /). The peripheral terminal then deactivates the DML / signal and the LCP processor deactivates HTCL /. This operation continues until state = 1.

1. The LCP processor activates the host interrupt level (HINTL /). The peripheral terminal acknowledges receipt of this by deactivating the peripheral message level (DML /) if it is active and it activates the peripheral terminal interrupt level (DINTL /)

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Line condition

Condition

Data direction in line

ST =

ST-4 /

ST-2 /

ST-1 /

0

0

0

0

Peripheral terminal not online

1

0

0

1

Reading

Starting from the peripheral terminal

2

0

1

0

Registration

To the peripheral terminal

3

0

1

1

R / D

Starting from the peripheral terminal

4

1

0

0

Order message

No data transfer

5

1

0

1

HD clock reset (RT)

No data transfer

6

1

1

0

Loan or registration C / D

To the peripheral terminal

7

1

1

1

Last word of a block or R / D-LPW to follow

To or from the terminal

peripheral by a change of state. This indicates to the peripheral terminal that the LCP processor has a C / M command message to send to the peripheral terminal.

2. The peripheral terminal activates the peripheral terminal interrupt level (DINTL /) instead of the DML / peripheral message level 20, by an adequate change of the status lines. The LCP processor acknowledges by activating the host transfer command level (HTCL /) and, following deactivation of DINTL /, it deactivates the host transfer command level HTCL / and enters the appropriate state . The DINTL / signal does not transfer data in the data lines.

3. When the peripheral terminal detects the transmission of the last word of a block, it goes to state ST = 7 with the leading edge of the DML / signal. The LCP processor responds to the peripheral terminal with the host transfer control level (HTCL /) and waits until the next transfer is a longitudinal parity word LPW. The LPW signal is transmitted with the DML / peripheral message level and is responded to by a Host Transfer Control level (HTCL /).

4. If the LCP processor detects a vertical or longitudinal parity error, the LCP processor does not acknowledge receipt of the DML / peripheral message level from the peripheral terminal.

Instead, the LCP processor creates a Host Clearance Level (HCL /).

40

Registration method:

If the LCP processor writes data to the peripheral terminal (state = 2 + 7), the following operations take place:

The LCP processor places a word on the data lines and activates the host transfer command level (HTCL /). The peripheral terminal 45 acknowledges receipt of this situation by activating the peripheral terminal message level (DML /). The LCP processor then deactivates the host transfer command level (HTCL /), then the peripheral terminal deactivates the peripheral message level (DML /). 50

This operation continues (table X) in state ST = 2 until:

1. The peripheral terminal goes to state ST = 7, then activates the peripheral message level DML / which identifies the LCP processor

indicating that the last word in the block has been received. The next word ss in the data lines must be an LPW longitudinal parity word when the HTCL / host transfer command level is again implemented. Then, the peripheral terminal activates the peripheral interrupt level DINTL / instead of the message level of the peripheral terminal DML /, accompanied by a change of the status lines.

2. For ST = 2 or ST = 7, the LCP processor activates the host interrupt level HINTL / instead of the host transfer command level HTCL /. In this mode, HINTL / represents an interrupt and indicates that there are no longer any 65 LPW longitudinal parity words on the data lines. The peripheral terminal acknowledges receipt of this situation by activating the peripheral interrupt level DINTL / and a change of state. LCP processor

disables the HINTL / host interrupt level and enters the correct mode after disabling DINTL /.

When the LCP processor is in R / D result descriptor mode, it reads an R / D result descriptor from the peripheral terminal (state = 3 + 7). When in R / D mode, the LCP processor reads the result descriptor from the data lines of the peripheral terminal. The R / D result descriptor can have a length of 1 to 3 words with a longitudinal parity word LPW. The first and second words of the three-word R / D result descriptor are read in the state ST = 3. The last word of the R / D result descriptor is read in the state ST = 7. The message level of the DML / peripheral terminal means that there is stable data on the data lines. Each R / D result descriptor word transferred is received by the HTCL / host transfer command level. If a result descriptor with an R / D word is received by the LCP processor, the data transfer occurs after message of state ST = 3 to ST = 7 at the same time as a message level of peripheral terminal DML / which corresponds to a result descriptor with an R / D word. The next word in the data lines is an R / D LPW longitudinal parity word that is triggered by the DML / peripheral terminal message level. After the LCP processor has finished reading, a complete R / D result descriptor as well as its appropriate longitudinal parity word LPW, the terminal returns to the state ST = 6. It can then accept a C / D order descriptor.

C / M order message mode:

This concerns the case in which the LCP processor writes an order message in the peripheral terminal (state ST = 4). When the LCP processor is in read mode and is directed to the C / M order message mode (DINTL / + ST = 4), the LCP processor continues to transmit the data to the main system 10 until :

1. detection of the system read end signal is detected, which results in the activation of the host interrupt level HINTL /, or

2. the data buffer zones A and B (or buffer memory 2500, fig. 6C) are empty and the end of system read signal is not detected; as a result, the LCP processor activates the HTCL / host transfer control level indicating that the main system 10 is still waiting for data.

Clock reset mode (R / T):

This occurs when the peripheral terminal resets the clock of the LCP processor (state ST = 5). A change of state to ST = 5 resets the clock of the LCP processor. This change of state occurs with a trigger. The peripheral terminal must remain in the state ST = 5 for at least 500 ns.

Sending order descriptor mode (C / D):

In this case, the LCP processor writes a C / D order descriptor in the peripheral terminal (state = 6). In this C / D sending order descriptor mode, the LCP processor writes three words followed by a longitudinal parity word LPW. The order level of

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Host transfer HTCL / which accompanies the descriptor C / D and the word LPW is received by the interrupt level of peripheral terminal DINTL / and a change to the appropriate state.

Last word mode of a block:

In this state ST = 7 (table X) and during the read operation, with ST = 7, the LCP processor reads the last word of the data block (or even R / D result descriptor) of the peripheral terminal. The last word will be the word LPW. During a registration operation, with ST = 7, the LCP processor writes the last word of a block in the peripheral terminal. The next word will be a longitudinal parity word LPW.

Conditional deletion:

After the LCP processor has entered the C / D order descriptor in the peripheral terminal and before this peripheral terminal changes from state ST = 6, with the peripheral interrupt level DINTL /, the main system 10 can complete the operation (OP) by sending a conditional delete signal. In this case, the LCP processor deactivates the HTCL / host transfer command level, then activates the HINTL / host interrupt level as long as the state ST = 6 and DINTL / is not active.

Unconditional removal:

The main system 10 can create an unconditional cancellation signal. As a result, the LCP processor creates an HCL / host clear level for the peripheral terminal. No acknowledgment of receipt is necessary for the peripheral terminal.

The LCP (line control processor) subsystem is made up of a number of separate LCP processors which communicate with the main system 10 through the I / O translator 10t. While each of the LCP processors has essentially the same basic structure and performs the same functions of the basic system, there are very slight variations between the various types of LCP processors, since each LCP processor is adapted to the operating conditions of the terminal particular device it serves.

The following description relates to the description of the operation of a preferred embodiment of an LCP processor intended for a peripheral terminal such as a supervision terminal.

The necessary functional elements of the LCP processor are registers, counters, encoders, decoders, buses, logic elements, etc. In addition, there is a transceiver produced by large-scale integration (abbreviated as LSI) for communication between the LCP processor and its peripheral terminal. In the LCP processor, there are, functionally, two divisions serving for communication between the LCP processor and the main system 10. These two functions are designated by reading module and writing module. These modules exist on the functional level, but do not constitute materially distinct elements, since many logical levels which compose them are common to the two modules. The read module is used to transfer data from the LCP processor to the main system 10 and it is implemented when the transmission flip-flop (XMITF) of the LCP processor is set to the state. The registration module is used to transfer the data from the main system 10 to the LCP processor and it is implemented when the reception flip-flop (RECVF) is set to the state.

Functionally, the components of the LCP processor are divided into three main sections: A) terminal control; B) flow of data; C) logical section of the system. To understand how the LCP processor communicates with the main system 10 and with the associated peripheral terminal such as the terminal 50, we will examine the functional characteristics of the following components:

A. Peripheral terminal control section:

1. Universal asynchronous transmitter / receiver (UART).

2. UART multiplexer.

3. Block check character register (BCCR).

4. Block check character decoder.

5. End code decoder.

6. Memory address register.

B. Data flow section:

1. Input multiplexer.

2. OP code register.

3. Variant register.

4. Valid OP encoder.

5. LCP buffer (RAM).

6. Terminal bus multiplexer.

7. Terminal bus.

8. Vertical parity checker / generator.

9. Data lock register.

10. LPW longitudinal parity word register.

11. LPW encoder.

12. End code decoder.

C. Logical section of the system:

1. Metering status register (STC).

2. STC decoder.

The functional components shown above are shown in Figs. 6B, 6C, 6D, 6E and 6F and in particular in fig. 6D.

According to fig. 6D and the peripheral terminal control (section A) described above, the universal asynchronous transmitter / receiver UART 31 is used as the interface between the asynchronous serial data channel of the interface of the peripheral terminal 22di and the parallel data transmission channel of the LCP processor. The transmitter part of the UART device 31 transforms a data character of parallel type and the control levels into serial type information containing a start bit, the data, a parity bit and a stop bit. The receiver part of the UART device 31 transforms the serial information containing a start bit, the data, a parity bit and a stop bit into a data character of parallel type. The UART device 31 creates a parity bit for the information transferred to the interface of the terminal 22di and it also checks the vertical parity of the information received by the terminal interface 22di.

The UART device 31 includes means for selecting different character lengths, checking and creating even or odd order parities and choosing one of the two stop bits. For use with a particular LCP processor, the UART 31 device may have options to have the following characteristics:

a) a character containing seven data bits;

b) creation or verification of even vertical parity;

c) a stop bit.

The UART 27x multiplexer accepts an eight-bit character, either AB digits (first two) from the terminal bus 47 or from the block check character register (BCCR) 33. The selected input is sent for the data input of parallel type of the UART device 31. The UART 27x multiplexer is used only for the transfer of data or for a block verification character of the LCP processor by the terminal interface 22di.

The block check character register (BCCR) 33 is a register which consists of eight separate flip-flops operating in bistable switching mode, the inputs being connected to the AB bus terminal digits 47. When the LCP processor transfers data to the peripheral terminal interface 22dj, the BCCR device 33 accumulates a block check character (BCC) to send it to the terminal interface 22di. When the LCP processor receives the data from the terminal interface 22di, the device (BCCR) 33 also accumulates a block check character to be checked again in comparison with another block check character (BCC) sent by the terminal interface 22di. The accumulation of block check characters is started at the

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reception of the first character following an STX signal (start of text) or of an SOH character (start of header) or continues until reception of a TEX character (end of text). Only messages and command sequences containing an STX or SOH character ensure the accumulation of a block check character (BCC).

The accumulation of a BCC character consists in applying each character to be transferred to the input of the BCCR device 33 and in performing a binary addition without carryover (OR-EXCLUSIVE function). Before each operation during which a BCC character will be accumulated in the BCCR device 33, the register is emptied. At the end of a data transfer, the OU-EXCLUSIVE function is again performed between the BCC characters of the transmitting and receiving units. If there is no error, the two BCC characters will be identical and the result in the BCCR 33 device will consist of only zeros.

The block verification character decoder 34 receives the output signal from the BCCR device 33. At the end of the transmission from the peripheral terminal 50, a BCCR character is received and is verified in comparison with the content of the BCCR device 33. If the two BCC characters are identical, the output signal from the BCCR device 33 is equal to a signal composed of zeros and the decoder 33 creates the level BCCOK (block check character in order) which is used in the BCC error logic.

Examples of interconnection between peripherals and I / O interfaces are described in particular in US patents Nos. 3510843,3514785 and 3526878. Examples of circuits concerned by the communication between the remote units and the corresponding buffer registers are described in particular in the US Patent No. 3,390,399.

The memory address register 36 is an eight-bit register which creates addresses for a buffer 250o of the LCP processor with 256 words. The register 36 is controlled so as to give the selective or sequential addressing of the intermediate memory, as required by the data transfer operation which must be carried out.

The termination card 20ot (fig. 2) provides a period of 1 s which is authorized for an operation only during a reading, when the LCP processor is conditioned so as to receive the data from the peripheral terminal such as the terminal 50. When the authorization inputs are active, the clock authorizes the peripheral terminal at a period of 1 s to start the transmission or continue an interrupted transmission to the LCP processor. If the period of 1 s elapses without transmission from the peripheral terminal, the time countdown flip-flop (TIMOUTF) is set to state and creates an end of time level (TIMOUTL) and the LCP processor begins end of the read operation by setting an end flip-flop (ENDF). However, this clock can be prevented from operating by the program by placing an adequate code in the digit variant 1 in the order descriptor (fig. 4B).

According to fig. 6B and 6D and the previous description concerning the data flow section of the LCP processor (section B), the 24xl input multiplexer ensures the selection of a 17-bit word from three sources: the input lines of data B ,; the output lines of the B25 RAM 2500 data buffer and the 24m peripheral interface levels that are created by the service or maintenance card (such as 20om fig. 2) from the outputs of the button switches maintenance panel button. The selected levels received by the 24x1 input multiplexer are transferred to the OP code 42 and to the variant register 43, to the 24x2 multiplexer or to the valid OP 44 coder, as required by the operations to be carried out.

The OP code register 42 receives the digital OP code from the C / D order descriptor and in combination with the output of the variant register 43, it indicates the operation to be performed by the LCP processor. The variant register 43 receives the variant digits contained in the C / D order descriptor and, in combination with the output of the OP code register 42, it specifies other operating details which the LCP processor must perform.

The valid OP coder 44 is a network which receives the C / D order descriptor information at its input; then, if the OP code digits and variant digits 1,2,3 coincide with the values representing the operation valid for the LCP processor, this coder develops a valid OP level (VOP) which authorizes the descriptor of order C / D to be loaded into the OP code register 42 and the variant register 43.

The RAM buffer 2500 of the LCP processor is formed by a network of 18 random access memories RAM, each having a capacity of 256 bits of information. Fig. 6C shows the RAM 2500 in more detail. The buffer network can store 18 bits in each of the 256 address positions; there are 16 data bits, a parity bit and a 25th end marker bit (fig. 6C) to identify a word position containing an end code.

According to fig. 6D, the 24x2 terminal bus multiplexer network selects a 17-bit word from four sources: the 24xl input multiplexer; the parallel data output line of the UART device 31; the LPW 24w register output and the 24rd result descriptor levels. The output from the 24x2 terminal bus multiplexer network passes to the terminal bus 47. Adequate voltage levels are provided to LCP components (such as the data lock register 49, the vertical parity controller / generator 48, the buffer memory 2500, the LPW register 24w, the decoder 52 and the end of code decoder 35, etc.) whose inputs are connected from the terminal bus 47.

The terminal bus 47 connects the output of the 24x2 terminal bus multiplexer network by the following components: the data locking register 49, the RAM 2500 buffer memory of the LCP processor, the LPW register 24w, the parity controller / generator vertical 48, the BCC register 33, the end of code decoders 52 and 35 and the UART 27x multiplexer.

The vertical parity controller / generator 48 creates an odd parity for each word transferred by the LCP processor to the main system 10. The controller / generator 48 checks the odd parity of each word transferred by the main system to the LCP processor. Each word to be transferred from the particular LCP processor to the main system 10 is first placed in the 17-bit register called the data lock register 49. The data lock register 49 then transfers the word to the main system 10. L use of the data locking register increases the speed of data transfer by allowing faster access to the data stored in the intermediate memory RAM 25 oo of the LCP processor.

The register 24w of the longitudinal parity word LPW is formed by 16 distinct flip-flops working in bistable tilting mode. This register receives, as input signals, those supplied by the terminal bus 47. When the main system 10 sends a C / D order descriptor, a D / L descriptor link or data to the LCP processor, the longitudinal parity word register LPW 24w accumulates a longitudinal parity word LPW to verify it in comparison with the word LPW of the main system 10. When the LCP processor sends data or an R / D result descriptor to the main system 10, the LPW longitudinal parity word register 24w also accumulates an LPW longitudinal parity word to be sent to the main system 10. The accumulation of the word LPW consists in applying each word to be sent or received at the entry of the LPW 24w register, and perform a binary addition without carryover (OU-EXCLUSIVE function).

The register 24w of the word LPW is started on states which are all equal to one, before each operation during which a word LPW will be accumulated in this register 24w. At the end of a data transfer from the main system 10, the EXCLUSIVE OR function is performed between the accumulated word LPW and the word LPW coming from the main system 10. If there has been no error, the two words LPW are identical and the resulting value of the register 24w LPW will be formed by zeros.

In fig. 6D, end of code decoders 52 and 35 are used to determine receipt of a final code character. The

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decoder 52 processes the digits AB and the decoder 35 processes the digits CD. The end of code decoder 52 for the digit AB is used to identify a final code in the first character position of a word originating from the main system. This decoder is also used to identify a final code of any character 5

sent through the 22di device terminal interface. If the decoder 52 receives such a final code, it creates the EDCODE level and the SYSEND level. The digital CD decoder 35 is used to identify a final code in the last character position of a word in the system. The reception of such a final code by the decoder 35 creates the voltage level SYSEND.

The above description relates to the second section B of the LCP processor. The third section C, the logic section of the LCP processor, will be examined below, referring to FIG. 6D.

The counting status register 53 (STC) is a four-bit register. This register creates counting status levels (STCnL)

intended for use by the LCP processor and levels referenced LCSTUn (LCP status levels) for transmission to the main system 10. In combination with the floating logic levels, which exist, the register STC 53 also controls the sequence of operations. of the LCP processor. Each counting state developed by the register STC 53 defines a different phase of operation in the execution of a descriptor of order C / D as indicated previously in relation to FIG. 6A. The decoder 54 is a decoder for transforming a binary decimal coding (BCD) into a decimal code with modifications of the quantities BCD of the register STC 53 into decimal quantities requested by the processor LCP.

According to fig. 6E, the system relations between the main LCP elements concerned and the processing control signals of these elements will be examined. Fig. 6E shows the main logic and control lines between the I / O input / output translator 10t, the distribution card 20od (from the basic module 20oo) and the particular line control processor LCP 20O0 as well as the peripheral terminal 50.

Referring first to the lower group of control lines of the LCP processor 20oo and its distribution board 20od, the reference LCPREQ (n) is a group of eight request lines; the letter n represents one of the digits 0-7 for each characteristic LCP processor of the basic module 20oo. Each of these signals is controlled by a particular LCP processor via the distribution card 20od. This signal is used by a particular LCP processor to request a connection with the main system 10; this signal puts the 20od distribution card on demand Poil.

The following designation LCPCON is the designation for 45

LCP processor connected. This line is controlled by the LCP processor connected (0-7) on the 20od distribution card. This signal is controlled by the LCP processor when it detects its own LCP address and is not in an offline state. The signal is a response to the LCP address and indicates to the distribution card 20od the presence of the LCP processor which has been addressed.

The denomination LCPSTL means level of triggering of processor LCP. This line is controlled by the LCP processor connected by the distribution card. It is a name of the particular LCP processor for sending or acknowledgment 55 depending on the direction of sending the data.

The IOSND reference designates the I / O transmission. This line is controlled by the LCP processor, connected to the 20od distribution card. This line defines the direction of the lines of the bidirectional data marked DATA (xn). When this line 60 is activated at the low level, the data lines are controlled by the distribution card 20od on the main system 10 via the I / O translator 10t.

The reference LCSTU (n) designates the state of a particular LCP processor, n designating one of the LCP processors 0 to 7. This line is controlled by the particular LCP processor connected to the distribution card 20od and indicates the LCP processor status as shown in fig. 6A.

According to fig. 6E, there are a certain number of connections between the LCP processor such as the processor 20oo and the distribution card 20od. DATA (xn) represents the message level interface (as shown previously in Fig. 5E in which the bottom 16 lines are data lines for the ABCD digits). The next line directly above is the PARITY line, which transfers the parity bits. These 17 lines constitute the message level interface; these lines are bidirectional, that is to say that the transmission takes place in one or the other direction as a function of the logic control lines used to determine the direction of the transmission.

The name EMRREQ in fig. 6E is the emergency request line. This line is controlled by one or more LCP processors on the distribution boards. LCP processors can control the emergency request line at any time. The expression emergency request means that an LCP processor quickly requests access to the system to avoid a data transfer failure. Only LCP processors, whose failure to access the system requires operator intervention or difficult recovery in the event of an error, can order the emergency request in combination with their LCP request. LCP processors that do not request emergency prohibit their LCP request by this line. A distribution card detecting an emergency request ensures the transmission of an overall priority equal to seven for the main system 10 during a Hair request.

The designation TERM in fig, 6E relates to a termination voltage level. This level is created on the distribution card and is sent to the LCP processor for the end of an operation.

The designation LCP AD n in fig. 6E concerns an LCP address (n can be equal to 0-7) to designate the particular LCP processors. One of the eight signal lines is controlled by the distribution board for each particular LCP processor. The LCP processor receiver is put on the correct line. This signal functionally corresponds to a line connection for the LCP processor. An LCP processor which receives its LCP address is connected to the main system 10 by the distribution card.

The STIOL reference in fig. 6E corresponds to the I / O trigger level signal. This line is controlled by the connected distribution card. This signal represents the transmission or the acknowledgment of reception of the system according to the direction of passage of the data.

The ARQOUT line in fig. 6E is the output of the distribution card, the input of which is designated ARQIN. These signals represent entry of the access request and exit of the access request. These signals are controlled and received only by distribution cards and correspond to short lines between adjacent distribution cards. They are used during the Hair test to resolve the priority of the distribution board. The DCB 1 and DCB 2 lines represent the activity levels of a distribution card. These levels are created on each active distribution card in a basic module to resolve the distribution card priority in the module during a Hair request sequence.

The PTALB line indicates the active hair test level. This is a bidirectional signal level between the distribution boards of the same basic module. A distribution card performing a Hair test operation sends this level to the other distribution cards prohibiting them from performing a Hair test or a Hair request.

The REQACC line indicates access requested. This line is ordered and is only received by distribution cards. The line is used to indicate that an interrupt request is implemented by the distribution cards.

The BUSY line in fig. 6E indicates that a basic module is at the active level. This corresponds to the level of the bidirectional signal created on a direction card, when this card has made the connection with the main system 10. The level is sent to the other distribution cards of the same basic module to indicate that the plan is being used. rear LCP.

According to fig. 6E, the relations between the I / O 10t translator and the card

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20od distribution will be discussed below. In the upper left part of fig. 6E, the designation LCPST relates to an LCP processor trigger pulse. This pulse is created on the distribution board by the LCP trigger level and is sent to the main system via the 10t I / O translator.

The reference PB / ST 2 designates the active channel or the status line 2 of the LCP processor. This line corresponds to the message level interface as shown in fig. 5E. In the not connected state, this line indicates that a channel is active during a Hair test algorithm. In the connected state, this line carries a bit 2 corresponding to the state of the LCP processor towards the system 10.

Each basic module can not only serve a main system 10 via its distribution card (20od, fig. 2), but also cooperate with multiple distribution cards and serve other main host systems. Each distribution card of the basic module can serve a different host system and each host system can have the same basic organization as that shown in fig. 3.

The reference IP / ST 4 indicates a request for interrupt or Poil test parity error or else a status line 4 of the LCP processor. In the unconnected state, this line is used to make an interrupt request by the LCP processor or to indicate an address parity error during a Poil test connection attempt. An interrupt request indicates that an LCP processor is requesting access to memory. In the connected state, this line carries a bit 4 corresponding to the state of the LCP processor for the main system.

The reference ER / ST 8 designates an emergency request or a status line 8 for the LCP processor. In the unconnected state, this line represents an emergency request from the LCP processor. The emergency request indicates that the LCP processor requires immediate access to the main system. In the connected state, this line carries a bit 8 of the state of the LCP processor to the main system. As soon as it is connected, the LCP processor indicates by its state its requirements to the system memory. The state of the LCP processor is controlled by door, continuously, and can only be considered valid by the system at the time of sending / acknowledgment of the LCP processor.

In addition, there will be described below, according to FIG. 6E, the connections between the I / O translator 10t and the distribution card 20od, the connections called parities and DATA xn relating to the message level interface lines described above. The reference CS / ST 1 relates to the expression channel selection or status line 1 of the LCP processor. In the disconnected state, these lines carry the channel selection signal from system 10 to the distribution card. The expression channel selection is used in combination with the expression address selection in the two connection algorithms.

However, in the connected state, this line passes bit 1 of the LCP processor state to the main system 10. This line is bidirectional. The receiver on the distribution card can be any conventional device in TTL technique. The control circuit of the distribution card is a three-state control circuit such as the 8097/8098 circuit (National Semiconductor Corp.) or an equivalent circuit which is implemented only in the connected state.

The expression TRM relates to the final level. This signal is sent by the main system 10 to the distribution card at the end of a data transfer operation.

The ADDSEL line in fig. 6E concerns address selection. This signal line indicates that the main system is connected or that an attempt to connect is made to a particular LCP processor. This line is used in combination with the channel selection signal for the two connection algorithms to make the connection. As soon as a connection to the LCP processor is ensured, the system and the LCP processor remain connected until the signal line is deactivated by the system. When the line is activated, the system can be considered to be in the active state.

According to fig. 6E, the expression AG / SIO relates to the expression assured access or I / O triggering. When the interface is in the unconnected state, this line ensures the passage of an assured access signal. The assured access signal is used to acknowledge receipt of a connection termination request and to initiate a Hair request algorithm.

When the interface is in the connected state, this line ensures the passage of an I / O trigger signal. This signal corresponds to the send / acknowledge line of the system, in the transfer of information between the system 10 and the LCP basic module. The real signal is a minimum pulse of 100 ns sent by the system and which is locked by the distribution card. The distribution board triggers the first 50 nanoseconds from the signal to allow the cable to rest.

According to fig. 6E, the control signals such as those between the LCP processor 20oo and the peripheral terminal 50 designate an RMDTLN line. This concerns the remote data line level. It is a bidirectional signal level which allows the transfer of serial type data between the LCP processor and the peripheral terminal, in one direction or in two directions, depending on what is chosen by the level.

The operating sequences of the LCP processor will be described below. The “logical” expressions concerned are the active and non-active states, to avoid any ambiguity which could result from the use of expressions such as true or false.

Receipt of instructions by the line command processor:

Previously, according to fig. 6A, the logical passage concerning the counting states (STC) between the processor LCP 20O0 and the main system 10 has been examined. According to FIG. 7A, a simplified passage diagram will be examined in more detail, showing the reception of instructions by the LCP processor. This flow diagram shows the basic actions of the LCP processor while receiving instructions as well as the actions that may occur as a result of initial instruction changes, receiving the time output level, or the presence of fault.

Before reception of any of the seven possible instructions from the main system 10, the LCP processor is normally in the free state, in the counting state 3. However, the LCP processor can also be in the STC state 3 for the reading operation while awaiting either a conditional deletion instruction from the main system 10 or a given transmission from the peripheral terminal 50.

The following description relates to the actions of the LCP processor during reception of instructions from system 10 and during preparation for execution of instructions. These actions are referenced a), b) and c).

a) System-LCP connection. When the LCP processor is in the STC 3 state, the system establishes a connection with the LCP processor by means of a Poil test sequence; the LCP processor receives its unique address level LCPAD (n) as shown in FIG. 6E. Receiving the LCPAD level (n) causes the LCP processor to send the LCP connection level (LCPCON, fig. 6E) to the associated distribution card 20od and it creates the LCPADL level (address level of the LCP processor) which authorizes parts of the LCP logical section. The LCPAD address level (n) also authorizes the background network of the LCP processor by creating a door system level (GATSYS). Then a trigger signal (STIOL) is received by the distribution card (20od, fig. 6E) setting the STIOF signal (synchronous trigger flip-flop). Setting the STIOF level activates the right module of the LCP processor by implementing the RECVF signal (reception flip-flop), authorizing the setting of the register 24w LPW (fig. 6D) at the logical state 1 and by putting the selected flio-flops in the initial state. The C / D command descriptor is received in the LCP processor and is placed in the OP code register 42 and the variant register 43 (FIG. 6D). Receipt of the C / D descriptor results in the sending of an LPW character to the 24w LPW register. The C / D descriptor is checked for validity and the OP validity flip-flop (VOPF) is set

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in the state. The LCP processor then goes from state STC 3 to state STC 11 (FIG. 7A) to receive the character LPW from system 10.

b) Reception of an LPW character by the LCP processor. In fig. 7A, in the STC state 11, a longitudinal parity word (LPW) is received by the system 10 and is checked with respect to the content of the register 24w LPW to check the longitudinal parity of the C / D transfer. The vertical parity is also checked, then the vertical level of agreement (VLOK) as well as the level of vertical parity of agreement (VPAROK) are put in the state. The address of the buffer memory of the LCP processor is preset to 253 in the memory address register MADR 36 (fig. 6D) and the setting of the register 24w LPW to logic state 1 is again authorized; then the LCP processor goes to the STC state 6 to receive the D / L description link of the system 10.

c) Reception of the descriptor link and LPW descriptor link. In the STC 6 state, the LCP processor receives two words from the descriptor link D / L of the system 10 and an LPW character is accumulated in the register 24w LPW. An LPW character is then received from the main system 10 and is checked against the content of the 24w LPW register. The descriptor link D / L and the character LPW are stored in the address positions of the buffer memory, positions indicated by the memory address register MADR 36 at the addresses 253, 254 and 255 (FIG. 6C). From the STC 6 state, the LCP processor drifts to the STC 8 state for a registration operation or to the STC 1 state for a read operation or even to the STC 7 state, if it has occurred a descriptor link error.

There are alternate path situations, for example; a) when a conditional delete instruction is received by the system 10, or b) when a data transmission is received by the peripheral terminal 50, or c) when an end of time level is created, or d) upon receipt of test instructions. Fig. 7A gives further details of such alternative situations.

a) Receipt of a conditional removal instruction. In the STC 3 state, when a conditional delete instruction is received from the system 10, as the LCP processor is waiting for the transmission from a peripheral terminal 50, a delete flip-flop (CANCF) is put into the state and the LCP processor goes to the STC state 11 to receive a longitudinal parity word of order descriptor LPW. From the STC 11 state, the LCP processor goes to the STC 7 state and sends a result descriptor to the system 10, indicating the end of the delete operation.

b) Reception of a transmission from a peripheral terminal. In the STC 5 state, during the read operation, if an active terminal flip-flop (TRMBSYF) is set to the state indicating that a terminal has started to transmit, the LCP processor goes to the STC 1 state to receive data from the peripheral terminal. The LCP processor continues to receive the data and completes the remaining read operations according to the instructions in the C / D order descriptor.

c) Reception of an end of time level. During the reading operation by the LCP processor in the STC 3 state, waiting for the transmission from the peripheral terminal (and if a 1 s clock is not prohibited) there is a delay of 1 s in the reception of the transmission and the end of time level (TIMOUTL) is created. When the TIMOUTL level is active, the final flip-flop (ENDF) is set to the state and the terminal end level (TMCNP) is created; the LCP processor goes to state STC 1. In state STC 1, a request to reconnect the system is implemented and the LCP processor goes to state STC 5 (fig. 7B). In the STC 5 state, with the ENDF signal set to the state, the read operation ends and the LCP processor goes to the STC 7 state to send an R / D result descriptor to the system 10. It is possible to also receive an end of time level when the LCP processor is in the STC 1 state.

d) Receiving test instructions. In the STC 11 state (fig. 7A), if a TESTF signal (flip-flop test) is implemented, indicating the reception of a test instruction, the LCP processor ends the test operation by going to l STC state 7 and by sending an R / D result descriptor to system 10.

Error condition. The presence of two types of error condition (ea) and (eb) during instruction reception acts by the LCP processor as follows:

(ea): Order descriptor parity error. In fig. 7 A, in STC 11 state, if the VLOK level (validity level in order) is not active or if VOPF (validity operation flip-flop) is not set, the LCP processor enters STC 7 state and sends an R / D result descriptor containing a descriptor error to the system.

(eb): Descriptor link parity error. In the STC 6 state, if the VLOK level is not active, the LCP processor goes to the STC 7 state and sends an R / D result descriptor containing a descriptor link error to the system 10.

Registration operation:

According to fig. 7B, we have a simplified sequential logic diagram to show the phases concerned by the registration operation. It is assumed that the data is transferred from an intermediate memory of the system 10 to the peripheral terminal 50, followed by a partial storage of the data containing a character of final code in the last character position (CD digits) of a word .

The following phases (a ... i) describe the operation of the LCP processor such as 20oo during the transfer of data from the system 10 to the LCP processor and from the LCP processor to the peripheral terminal 50.

a) Reception of data from the system. In the STC = 6 state, when a registration operation is given by the C / D order descriptor, the LCP processor authorizes the setting of the register 24w LPW to the logic state 1, then goes to l STC = 8 to receive data from system 10. When using an IOSF level (I / O transmission flip-flop) and resetting it at this time, to authorize the bidirectional data lines, the data passes from the system 10 to the LCP processor. There are control levels of the SLAIN multiplexer (selection of input A of the multiplexer) and SLBIN (selection of input B of the multiplexer). Both are inactive and connect the data lines to the 24xl multiplexer network in Figs. 6B and 6D. There are other levels of SLARAM multiplexer control (selection of level A of the terminal bus of the multiplexer) and SLBRAM (selection of level B of the terminal bus of the multiplexer). These two elements are also inactive and connect the 24xl input multiplexer network to the input of the 24x2 network.

In the state STC = 8, the reception flip-flop (RECVF) is set to the state and activates the registration module of the LCP processor. The setting of RECVF causes the LPC buffer registration authorization level (WESYS) to be implemented. Thus, the data is transferred from the main memory 10m of the system by the buffer memory 2500 of the LCP processor, one word at a time, via the terminal bus 47 of the LCP processor. An asynchronous trigger signal (STIOL) from the corresponding 20od distribution card (fig. 6E) accompanies the transfer of each word, when it is received by the LCP processor; the LCP processor sends a trigger level (LCPSTL) to the system 10 to acknowledge receipt of the word. As each word is placed on the terminal bus 47 while being sent to the intermediate memory 2500, it is also applied to the input of the vertical parity controller / generator 48, to the 24w register of character LPW and to the end decoders. code 52 and 35. The vertical parity is checked and the word of longitudinal parity is accumulated in the register 24w of character LPW. The transfer of the words continues until the next data word address 251 is reached in the memory address register 36. The processor LCP then goes to the state STC 10 of FIG. 7B to receive a final word from the system. In the STC 10 state, the LCP processor receives the final word to fill the intermediate memory, then goes to the STC 12 state to receive the LPW character from the system 10.

b) Reception of an LPW character and disconnection from the system 10. In the state STC = 12, the LCP processor receives an LPW character from the system 10 and checks it against the LPW character accumulated in the LPW character register 24w during the data transfer. The

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LCP processor then authorizes the setting of the register 24w of character LPW to the logical state 1, then passes to the state STC = 1, cutting off from the system 10 to transfer the data to the peripheral terminal 50. The multiplexer bus terminal controls the SLARAM and SLBRAM levels (selection of A and selection of B of the 24x2 element) which are both inactive to connect the output of the intermediate memory 2500 to the input of the 24x2 network of the bus multiplexer of terminal. The 24x2 input multiplexer has SLAIN (selection of level A of the multiplexer input) and SLBIN (selection of level B of the multiplexer input) control levels which are controlled, during data transfer, by the state of the even flip-flop (EVNF) to access a character, alternately between the digits AB and the digits CD of a word from the intermediate memory 2500.

c) Data transfer to the peripheral terminal. According to fig. 7B, in the state STC = 1, the reception flip-flop (REVCF) is reset and authorizes the reception module of the LCP processor. The Terminal Startup Level (TERST) is created to prepare the LCP processor to work with the peripheral terminal. The TERST level authorizes the setting of the UART Master flip-flop (MCUARTF) to erase the UART device 31 (fig. 6D). Activation of a terminal active flip-flop (TRMACTF), an emission flip-flop (SENDF) and the terminal activity flip-flop (TRMBSYF) are also authorized, by activating the logic terminal command for the registration operation and indicating that the peripheral terminal is in the active state. The memory address register 36 (fig. 6D) is set to the state MADR 0 to access the first word of the buffer memory 2500. In the UART device

31, the empty transmitter hold register level (THRE) is active and the state of the UART evacuation flip-flop (UARTETF) is authorized to provide a trigger level for the UART 27x multiplexer.

The UART device 31 accepts one character at a time from the intermediate memory 2500 of the LCP processor. The pair flip-flop (EVNF) is used in combination with the memory address register 36 to control access to the character. When the UART device 31 is loaded with a character, it serially transfers the character via the peripheral terminal 50.

When each character of the intermediate memory 2500 is placed on the terminal bus 47, it is also applied to the entry of the block verification character register (BCCR) 33 which (after reception of STX / SOH, test start / start of character header) begins to accumulate a block check character during data transfer. The UART device 31 continues to accept the characters from the intermediate memory 2500, then transfers these characters to the peripheral terminal 50 until the memory address level MADR 252 is reached in the memory register 36, indicating the access to the last word in the intermediate memory.

d) Reconnection request on the system 10. The memory address level MADR 252 sets the intermediate memory transfer flip-flop (BFXFRF), indicating that the intermediate memory 2500 requests service and the LCP processor initiates a reconnection request on the system by authorizing the setting of the LCP request flip-flop, LCPRQF. IOSF (I / O transmit flip-flop, which indicates the direction of data flow to the message level interface) is authorized to condition the system 10 data transfer lines and the setting of the MADR 253 level is authorized to allow access to the D / L descriptor link (fig. 6C). The LCP processor then goes to state STC = 5 (fig. 7B) to send the descriptor link D / L to the system 10. Then the floating logic levels create the level LCPADL (address level LCP) when the levels d LCP address (0-7), LCPADn are received by the corresponding distribution card, during the reconnection sequence, and the LCP processor creates a door system called level (GATSYS) to authorize the background network. The connected LCP level

(LCPCON) is sent to the 20od distribution board to indicate that the LCP processor is connected.

e) Transfer of the descriptor link and the LPW descriptor link. In fig. 7B, in the state STC = 5, the transmission flip-flop (XMITF) is put in the state and it activates the red module of the LCP processor. The LCP processor transfers the D / L descriptor link and the LPW character (previously received in the STC = 6 state) to send them back to the system 10. The LCP processor authorizes the setting of the LPW character register 24w to Logical state 1 and goes back to STC = 8 to receive additional data from system 10.

I) Reception of additional data and final code of the system 10. In the state STC = 8, the actions of the LCP processor which receives the second buffer load of the data from the system 10 are the same as those carried out during the reception of the first load buffer, up to the point at which the final code is recognized by the terminal bus 47. When a final code of at least one character position (CD digits) of a word is placed on the terminal bus 47, the system end level (SYSEND) is created. The SYSEND level activates the data entry of the final reference 25e of FIG. 6C (RAM 18 L) and the final marker bit (ENDFG) as well as the final code character, both of which are stored in the current intermediate memory address. The LCP processor then enters the STC 12 state to receive an LPW character from the system 10.

g) Reception of an LPW character and disconnection in relation to system 10. In the state STC = 12 of FIG. 7B, the processor LCP receives the longitudinal parity word LPW and compares it to the character LPW accumulated in the register 24w of character LPW. The LCP processor then goes to state STC = 1, disconnects from system 10 and transfers the remaining data as well as the final code to the peripheral terminal.

h) Transfer of the final code data to the peripheral terminal. In the STC = 1 state, the actions for transferring the remaining data to the peripheral terminal are the same as those during the transfer of the first intermediate memory load, until the moment when the final code is recognized on the terminal bus. 47. When a final code is placed on the terminal bus 47 by the output of the intermediate memory 2500, the final code is transferred and the final flip-flop (ENDF) is issued. The block check character accumulated in the BCCR device 33 (if a BCC signal has been created) is then transferred to the peripheral terminal unit 50. The signal SENDF (transmission flip-flop) and TRECF (flip-flop) receive terminal) are both reset, so the terminal end level (TMCMP) is active. The end of terminal level causes the LCP processor to start a connection request on the system 10.

i) Reconnection request for the end of write operation. The LCP processor requests a reconnection to the system by authorizing the state of the LCPRQF signal (LCP request flip-flop). In combination with this reconnection, the LCP processor goes to state STC 5 in FIG. 7B, sends a D / L descriptor link for the system 10, then goes to the STC state 7 to send an R / D result descriptor to the system 10.

The description above completes the explanations of the general path for a registration operation during which more than one data load is transferred from intermediate memory, and the operation of which ended with the reception of a final code. This corresponds to the description of a normal situation. However, there may also be alternate pathways and error conditions which may occur in the following situations, reported in fig. 7B: the elements a ... c relate to the action of the LCP processor when modifications of the initial registration instructions are made by the system 10 or the LCP processor.

a) Request for emergency access to the system 10. During the transfer of data from the LCP processor to the peripheral terminal 50, when the intermediate memory 2500 LCP is completely empty, a flip-flop BFXFRF is set to the state. This is the transfer flip-flop

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intermediate memory which is placed on the terminal card; this flip-flop is set to state when the intermediate LCP memory is loaded with data from the terminal or when it is empty of data during the transfer of data from the LCP processor to the peripheral terminal. When BFXFRF is put in the state, this authorizes the putting in state of LCPRQF (LCP request flip-flop, which, when it is put in the state, indicates that the LCP processor requests access to the main system memory 10m). Putting LCPRQF in the state initiates a reconnection request from system 10 to send the data to the main system or to obtain more data when the intermediate memory is empty. If a reconnection is not established before the transmitter maintenance register for the UART device 31 is ready to accept another character, the LCP processor creates the emergency request level (EMRREQ). The EMRREQ level is sent to the corresponding distribution card 20od to initiate an emergency request to be reconnected to the system.

b) Receipt of a final code (AB digits). When a final code is identified in the first character position (digits AB) of the system word 10, the signal EDCODE (end of code level) is then created. This EDCODE signal is created on the terminal control card when an end of code character is in digits A and B of the terminal bus 47. The SYSEND signal (final system code level) is also created. When this SYSEND signal is implemented, it indicates that an end of code character is on the terminal bus 47. In the STC 8 state, the EDCODE level authorizes the putting into the state of the end flip-flop. character (CHARENF) and the SYSEND level creates the eighteenth bit of the final registration mark level (RAM 18 L). The final registration mark level is created on the EDCODE level terminal control card. This is the data entry level of the final marker RAM of the intermediate memory 2500 of the LCP processor. The final code and the ENDFG signal (final marker level created on the data passage card on RAM 18 L; when active, this level identifies the address of a final code in the intermediate memory of the LCP processor) are stored in the current intermediate memory address of the LCP processor; the LCP processor then goes to state STC = 12 (fig. 7B) to receive a longitudinal parity word LPW. In the STC = 12 state, the LCP processor receives an LPW character from the system 10 and checks it against the LPW character, accumulated in the register 24w. The LCP processor then goes to state STC = 9 to initiate the reduction of the system memory address (the address must be decremented by two digits to accurately translate the address of the final code of the system memory ). From the STC 9 state, the LCP processor goes to the STC 1 state to transfer the data and the final code to the peripheral terminal 50. In the STC 1 state, recognition of the final code on the terminal bus 47 means that the LCP processor performs the same actions as during the previous registration operation in the STC 1 state, when the data, the final code and the block check characters have been transferred to the peripheral terminal 50; the LCP processor disconnects from the peripheral terminal 50 and reconnects to the system 10 and ends the registration operation.

c) Reception of the system termination signal 10. A termination signal (TERM level, fig. 6C, 6E) is sent by the system 10 to the LCP processor each time the memory location of the system intended for LCP processor operations is about to be overtaken. During the registration operation, the TERM level can be received in the states STC = 8, STC = 10 or STC = 12 (fig. 7B). The action on the LCP processor upon reception of the TERM level (termination level) depends on the counting state in which the LCP processor operates and whether the reception of the TERM level is preceded or not by the reception of a final code of the system under the following conditions:

1) Receipt of a termination signal before the final code. If the TERM level is received in the STC = 8 or STC = 10 state, the LCP processor goes to the STC = 14 state. In the STC = 14 state, whether the TERM level remains active or is now inactive, the LCP processor goes to STC = 12, receives and checks a longitudinal parity word

LPW, then goes to state STC 7 to send an R / D result descriptor to system 10. If a final code is received in the CD digits (last character) of a word in state STC = 8 or STC = 10, and if the TERM level is also received, the LCP processor goes to the STC = 14 state. In the STC = 14 state, if the TERM level is still active, the final code is not in the memory 2500 buffer from LCP processor. The LCP processor then goes to the STC = 12 state, receives and verifies an LPW character, then goes to the STC 7 state to send an R / D result descriptor to the system 10.

2) Receipt of a termination signal after the final code. Upon receipt of a final code in the CD digits of a word in the STC = 8 or STC = 10 state, the LCP processor goes to the STC = 12 state to receive the character LPW. In the state STC = 12, when the TERM level is then received, the final code is transferred to the intermediate memory 2500 of the LCP processor; the LCP processor then goes to the STC = 1 state to transfer the remaining data and the final code to the peripheral terminal 50. In the STC = 1 state, the recognition of the final code on the terminal bus 47 puts the state l ENDF element (final flip-flop: when it is set to the state, this flip-flop indicates that the terminal control section of the LCP processor has finished its work). ENDF status indicates that there is no more data to transfer; after the data, the final code and the block check character are transferred to the peripheral terminal 50; the LCP processor cuts off from terminal 50 and reconnects to system 10 to complete the registration operation.

As described below, in the STC 1 state, recognition of the final code on the terminal bus 47 puts the ENDF signal (final flip-flop) in the state. ENDF status indicates that there is no more data to transfer. After the data, the final code and the block check character are transferred to the peripheral terminal 50 and the LCP processor reconnects to the system 10 to complete the registration operation.

If a final code is received in the AB digits of a word in the STC = 8 or STC = 10 state, and if the TERM level is also received, the LCP processor goes to the STC = 14 state. In this state STC = 14, if the TERM level is inactive, the entire word containing the final code of digit AB is transferred to the intermediate memory 2500 of the LCP processor. It is necessary to correct the memory address of the system. The LCP processor goes to state STC = 12, receives and verifies the character LPW, then goes to state STC = 9 to initiate the decrease (decrementation) of the address of the memory of the system. The LCP processor then goes to state STC = 1 to transfer the data and the final code to the peripheral terminal 50.

If the TERM level is still active in the state STC = 14, then only the final code character is transferred to the intermediate memory 2500 of the LCP processor and no correction of the memory address of the system is necessary. The LCP processor goes to state STC = 12, receives and verifies the character LPW, then goes directly to state STC = 1 to transfer the data and the final code to the peripheral terminal 50.

Error conditions:

During the registration operation, the following error conditions (a, b, c, d) act on the LCP processor:

a) Access error. After transmission of the EMRREQ level to the associated distribution card, if the LCP processor does not receive a reconnection on the system 10 before the UART device 31 is completely empty, the LCP processor authorizes the setting of the flip-flop d 'access error (ACCERF). The setting of the ACCERF signal allows the setting of the ENDF signal (final flip-flop) and the LCP processor initiates a reconnection request for the system 10, to complete the registration operation and sends a result descriptor system R / D error 10.

b) Vertical parity error of the system. During the transfer of data from the system 10 to the LCP processor, if a vertical parity is not in order and if the VPAROK level is not active after each vertical parity check, the error flip-flop of

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vertical parity (VPERF) is set to indicate the existence of a vertical parity error. The absence of VPAROK level also prevents the vertical longitudinal tuning level (VLOK) from being created and that in state STC = 12, the LCP processor goes to state STC = 7 and sends a result descriptor R / D error 10.

c) Longitudinal parity error (fig. 7B). When a longitudinal parity word is checked after a data transfer from the system 10 to the LCP processor, if a longitudinal parity agreement level (LPOK) is not active, the longitudinal parity error flip-flop (LPERF) is set to indicate the existence of a longitudinal parity error. The absence of LPWOK level (the agreement on the LPW level is created by the data bus card of terminal bus 47; when it is active, it indicates that the logic section of the LCP processor system has an LPW character correct) prevents the VLOK level from being created and that in state STC = 12 the LCP processor does not pass in state STC = 7 to send an R / D error result descriptor to system 10.

d) Terminal vertical parity error. During the transfer of data from the intermediate memory 2500 of the LCP processor to the UART device 31, if the level of vertical parity agreement (VPAROK) does not remain active for each character which has been transferred, the error flip-flop vertical parity (TVPERF) is set to indicate the existence of a vertical parity error. When the LCP processor reconnects to the system 10 and completes the registration operation, the R / D result descriptor puts the system 10 in the state STC = 7 indicating the parity error.

Read operation:

According to fig. 7C, there is a simplified logic table showing the read operation. The read operation is generally performed in combination with some form of write operation. By way of example, it is assumed that a registration operation has ended and that the peripheral terminal 50 has responded with an acknowledgment character (ACK) indicating that the peripheral terminal 50 can now send information. It is also assumed that there is no delay in receiving the data from the peripheral terminal 50 and that a data buffer charge will be received, followed by partial storage of the data containing a final code. It is also assumed that the final code is received so that it is placed in the last character position (CD digits) of a word in the intermediate memory 25oo of the LCP processor (FIG. 6C).

General passage: the following paragraphs a to 1 describe the actions of the LCP processor during the transfer of data from the peripheral terminal 50 to the LCP processor as well as from the LCP processor to the system 10.

a) Disconnection from the main system 10. Referring to fig. 7C, in state STC 6, when a read instruction is specified in the C / D order descriptor of the system, the READF signal (read flip-flop provided on the data passing card; the logic state of the read flip-flop is controlled by the output levels of the OP code register; setting the READF signal indicates that a read operation is performed by the system) is set to the state. The LCP processor authorizes the setting of the LPW character register 24w at the logical position 1, then goes to the STC state 1 by disconnecting from the system 10 to receive the data from the peripheral terminal 50. The selection level A from the multiplexer 24 ^ (flg. 6D) of the terminal bus (SLARAM) is active, and the levels SLBRAM, SLAIN and SLBIN are inactive and form a path for the data passing from the UART device 31 to the intermediate memory 2500 of the LCP processor.

b) Reception and storage of data from the peripheral terminal. According to fig. 7C, in STC 1 state, when the READF signal is set, the terminal start level (TERST) is active. This TERST level causes the UART 31 device to empty and authorize the placing in the TERMACTF state (active terminal flip-flop provided on the terminal control card; the logical state of this flip-flop is controlled by TERST , TRECF and SENDF; setting the TRM ACTF signal indicates that the terminal control section of the LCP processor has been activated for the read or write operation) for the control logic of the active terminal. The READF signal also authorizes the setting of the terminal reception flip-flop (TRECF) to allow reception of the data from the peripheral terminal 50. The buffer memory 2500 has a preset address for the position MADR 255 and, in the case where the flip-flop (EVNF) is not already set to the state, this setting to the state is authorized to begin the command of the addressing of the intermediate memory. The data characters are transferred in series from the peripheral terminal 50 to the UART device 31 of the LCP processor; the UART device checks each character to see that the vertical parity is even.

b-1) Reception of a first character and generation of vertical parity. When the terminal reception flip-flop (TRECF) is set and the data storage flip-flop (DATASTF) is reset, reception of the first character activates the data reception level (DR ). The level (DR) authorizes the setting of the UART flip-flop (RSUARTF) as well as the terminal activity flip-flop (TRMBSYF). The EVNF even flip-flop is set, so that the address of the buffer increases for position 0 MADR. The setting of the DATASTF data storage flip-flop and the resetting of the initial state of EVNF are then authorized in preparation for the storage of the first character in the intermediate memory. When RSUARTF is set, the SLARAM level is created and it places the first character on the AB digits as well as on the CD digits of the terminal bus 47, thus forming a complete word. This word does not contain a parity bit. The content of the terminal bus 47 is applied to the vertical parity controller / generator 48 of FIG. 6D. The word parity on the terminal bus 47 is created and a flip-flop used to designate the odd vertical parity is put in the state or is reset, to indicate the parity, until reception of d 'a second character of the peripheral terminal 50.

b-2) Storage of a first character in the intermediate memory. When the DATASTF data storage flip-flop is set to state, resetting EVNF causes the intermediate memory to activate the registration authorization level A (ERWA). The system registration authorization level (WESYS) is also active and these two levels give the registration authorization entry for the AB and CD digits of the intermediate memory network. The first character is then stored in the two digit positions AB and CD of position 0 MADR of the memory address register 36. The transfer of the first character from UART 31 into the intermediate memory 2500 results in the delivery to the initial state of the UART flip-flop (RSUARTF). The data reception level (DR) is then made inactive; this operation is followed by resetting DATASTF (data storage flip-flop). This combination of logical states prepares the UART device 31 to accept the second character of the peripheral terminal 50.

b-3) Reception and storage of the second character. When the second character is received by the UART device 31, the data reception level (DR) is again made active and RSUARTF is set to the state. This logic of the combination with the resetting of the even flip-flop EVNF prohibits any incrementation of the address of the intermediate memory. The setting of the DATASTF data storage flip-flop and the resetting of the EVNF peer flip-flop are authorized in preparation for the storage of the second character in the intermediate memory. Selection level A of the SLARAM terminal bus multiplexer is always active and this character is placed in both the AB and CD digits of the terminal bus 47. The content of the terminal bus 47 is again applied to the controller / generator of vertical parity 48. The parity is created for the word of the terminal bus 47 and is compared with the parity created during the reception of the first character. The results of the

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comparison results in the creation of a single parity bit for the first and second characters.

When the DATASTF data storage flip-flop and the EVNF peer flip-flop are set to the state, the ERWB level (level of authorization for registration for CD digits of the intermediate memory of the LCP processor) is created and the second character is stored in the last character position (CD digits) of the intermediate memory 2500 at the address position MADR 0, by superimposing on the character previously entered at this location. The character on the AB digits of the terminal bus 47 is not stored in the intermediate memory 2500, because the ERWA level is not active (ERWA is the registration authorization level for the AB digits of the intermediate memory LCP processor). A parity bit of the vertical parity controller / generator 48 is added to the full word which is now in the memory address register at position MADR 0.

b-4) Reception of additional characters and start of the accumulation of the block check character (BCC). The LCP processor accepts additional characters. On receipt of each character, the logical state of the even flip-flop EVNF is supplemented to control the increase in the memory address register 36, so as to place the data in the intermediate memory 2500 in word format. On reception of the start character of the header (start of the text) (SOH / STX) of the peripheral terminal 50, the block verification character register 33 of FIG. 6D is allowed and each character following the SOH / STX character is applied to BCCR 33 to accumulate a BCC block check character for the message being received. The accumulation of the character BCC continues with the reception of the first data load from the intermediate memory and by the reception of successive data loads from the intermediate memory, until the reception of the final code (character ETX). The operations that occur upon receipt of the final code will be described later.

c) Full intermediate memory. When the intermediate memory 2500 of the LCP processor is fully loaded with data, the pair flip-flop EVNF and the memory address level MADR 252 are set, which authorizes the setting of the memory transfer flip-flop intermediate (BFXFRF). BFXFRF status indicates that the intermediate memory 2500 of the LCP processor requests service and the LCP processor starts a request for reconnection on the system 10.

d) Reconnection request on the system 10. After the disconnection, state STC 1, the LCP processor begins a reconnection request on the system by authorizing the state of the LCPRQF request flip-flop of the LCP processor. The setting of the I / O transmission flip-flop (IOSF) is also authorized to condition the data lines for the transfer of the data to the system 10; the setting of the MADR 253 memory address (flg. 6C) is authorized to allow access to the D / L descriptor link. The LCP processor then enters the STC 5 state and sends the D / L descriptor link and the LPW character to the system 10.

The expression MADR relates to memory address levels. These levels are created on the terminal control card from the outputs of the memory address register 36. These levels represent the address positions (table XI) in the intermediate memory 2500 of the LCP processor (FIG. 6C) and which are planned as follows:

TABLE XI

Position

Description

251

Penultimate data word

252

Last word of data

253

Information word of the descriptor link

254

Information word of the descriptor link

255

LPW descriptor link.

When one of the eight LCP processor address levels, namely the LCPADn level, is received from the corresponding distribution card 20od during the reconnection sequence, the LCPADL address level of the LCP processor is active. The LCPADL address level is created on the terminal control card when the applicable LCPADn level is active. The LCPADn level also creates the GATSYS door system level to authorize the background network of the LCP processor. The LCPCON connection level of the LCP processor is sent to the distribution card 20od to indicate that the LCP processor is reconnected. The SLAIN level is active and the SLBIN, SLARAM and SLBRAM levels are inactive, to allow the descriptor link D / L to be transferred to the locking register 49 (fig. 6D).

e) Transfer of the D / L descriptor link and the LPW descriptor link. In fig. 7C, in the STC 5 state, the transmission flip-flop (XMITF) is set to the state. The transmission flip-flop is provided on the logic board of the system and the setting indicates that the LCP processor transfers data to the system 10, thus activating the reading module of the LCP processor. The LCP processor transfers the descriptor link D / L and the longitudinal parity word LPW (previously received in state STC 6) to send it back to system 10. The LCP processor then authorizes putting the register into state 24w of character LPW in logical state 1 and goes to

STC = 4 state to transfer data to system 10.

f) Data transfer to the system 10. In the STC = 4 state according to fig. 7C, the XMITF transmission flip-flop and the IOS O I / O transmission flip-flop are always set to the state from the operation corresponding to the STC = 5 state. The asynchronous trigger flip-flop (ASYNCF) is set to allow the asynchronous transfer of the data to the system 10. The data is transferred from the intermediate memory 2500 of the LCP processor via the data locking register 49 (fig. 6D)

towards the system 10 (via the interface 22si of the system according to FIG. 6C). The transfer is done with one word at a time (with, in addition, a parity bit). The LCP processor LCPSTL trigger level accompanies the transfer of each word and, on reception of each word by the system 10, the latter sends a trigger pulse to acknowledge receipt of the word. Each word on the terminal bus 47 (FIG. 6D) for the transfer to the system 10 is applied simultaneously to the locking register 49 and to the register 24w of character LPW. The 24w register accumulates the longitudinal parity word LPW during the data transfer. When the address of the last data word of the intermediate memory 2500 (MADR 252) of the LCP processor is reached, the synchronous flip-flop (SF, which is loaded on the terminal control card and is put in the state when the LCP processor transfers the data to the peripheral terminal) is put in the state, which results in the creation of a synchronous level SFL, then the LCP processor goes into the STC 12 state to send an LPW character to the system 10.

g) Transmission of a longitudinal parity word to the system 10. In FIG. 7C, in the state STC = 12, the character LPW, accumulated in the register 24w during the operation in the state STC = 4, is sent to the system 10. The LCP processor then authorizes the putting in the state of the register 24w of character LPW to go to logic level 1 and advance to the state STC = 1 to receive additional data from the peripheral terminal 50 (via the terminal interface 22di, fig. "6C). After this operation , the LCP processor goes to state STC = 5 and sends a descriptor link of the main system 10.

h) Receipt of additional data and final code from the peripheral terminal. When entering STC 1 a second time, an active terminal flip-flop (TRMACTF) and a terminal receiving flip-flop (TRECF) are both set from the previous operation to STC state 1. The terminal reception flip-flop TRECF is on the terminal control card; this flip-flop is set to the state when the LCP processor receives data from the peripheral terminal; the TRMACTF active terminal flip-flop is also provided on the terminal control card and, when it is in the state, it indicates that the terminal control section of the LCP processor has been active for a read operation or s

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of registration. The address of the intermediate memory of the LCP processor is again updated to MADR 255 in preparation for the reception of the data from the peripheral terminal 50. In the state STC 1, the actions of the LCP processor during the reception of the second load of data of the intermediate memory coming from the peripheral terminal 50 are the same as those carried out during the reception of the first load of intermediate memory,

until the reception of the final code on terminal bus 47.

We assume that, before receiving the final code, in the STC = 1 state, we are in the following two conditions:

1) EVNF is reset, which indicates that the next character to be received will be placed in the last character position (CD digits) of a word;

2) the two RSUARTF signals (reset UART flip-flop) and the data storage flip-flop (DATASTF) are reset. Upon receipt of the final code character, RSUARTF is put into the state, which gives the logical level necessary to create the registration authorization level (ERW 18) for the final RAM code. The reception of a final code is recognized by the LCP processor when the character is on the terminal bus 47. Recognition of the final code leads to the creation of the final code level EDCODE which creates the data entry level (RAM 18 L) for the final RAM code; the final marker bit (ENDFG) is then stored at the corresponding address of the intermediate memory 2500-The setting to the EVNF and DATASTF state is then authorized, which conditions the LCP processor to store the final code in the intermediate memory 2500- When EVNF is set to state, the ERWB level is active (registration authorization level for CD digits) and the character is stored in the last character position of the same word address in which is stored the final ENDFG benchmark level.

i) Verification of the BCC character and request for reconnection for the system 10. When DATASTF is set to the state, the EDCODE level authorizes the state of the final flip-flop (ENDF). The LCP processor then receives a block verification character (BCC) from the peripheral terminal 50 and controls this with respect to the BCC character accumulated in the block verification character register 33. Setting the flip-flop final ENDF results in the reset of the TRECF terminal reception flip-flop and activation of the level corresponding to a complete terminal (TMCMP), and the end of the actions of the terminal control section of the LCP processor. The LCP processor then starts a reconnection request on the system and goes from state STC 1 to state STC 5 to send the descriptor link D / L to system 10.

j) Transfer of the D / L descriptor link and the LPW descriptor link. As in the previous reconnection on the system, in the STC 5 state, the LCP processor sends the D / L descriptor link and the LPW character to the system, then goes to the STC 4 (read) state to transfer the data to the system 10.

k) Data transfer to the system 10. In the STC 4 state, the actions of the LCP processor are the same as those described above for the STC 4 state, until the word containing the final code character is placed on the transfer bus to be transferred to system 10. Recognition of the final code causes the final system level (SYSEND) to be created and the LCP processor goes to state STC = 12 to send an LPW character to system 10 .

1) Transmission of an LPW character and R / D result descriptor to the system 10. The LCP processor sends the LPW character accumulated in the 24w register to the system 10. After sending the LPW character, as the complete level of termination (TMCMP) is now active, indicating that there is no more other data to transfer, the LCP processor goes to state STC = 7 to send an R / D result descriptor to system 10.

In the STC = 7 state, the LCP processor sends an R / D result descriptor to the system 10, then goes to the STC = 15 state (fig. 7D),

then sends an LPW character and returns freely to the STC = 3 state to await further instructions from the system 10.

The above description relates to the general path for a read operation in which more than one data load of intermediate memory has been transferred from a device to the main system, and the operation of which has been terminated by reception of a final code.

However, during a read operation, there may be other situations which create variants of logical paths and the processing of possible error conditions. The following sections a to d indicate the effect of the LCP processor when modifying the initial read instructions, either by the system 10 or by the LCP processor:

a) Reception of an end of time level. According to fig. 7E, in state 1, when the operation of the clock at 1 s is not prohibited and a data item is received by the LCP processor from the peripheral terminal 50, if the data transmission is interrupted for a period of 1 s, this results in the creation of an end of time level (TIMOUTL). When the TIMOUTL level is active, the final flip-flop (ENDF) is set to the state and the complete termination level (TMCMP) is created. A reconnection request is created for system 10 and the LCP processor goes to state STC 5. In this state STC 5, when the final flip-flop (ENDF) is put in state, the read operation is ends and the LCP processor goes to the STC state 7 to send an R / D result descriptor to the system 10. When the LCP processor is in the STC state 3, it can also receive an end of time level as shown in fig. 7E, in state STC = 3 free state.

b) Transmission still pending from the peripheral terminal. In fig. 7E, in the STC = 1 state, when the LCP processor is conditioned so as to receive the data from the peripheral terminal 50, if no data is received under these conditions, the LCP processor immediately goes to the STC = 3 state to be able to receive a conditional delete instruction from the system 10. The LCP processor then returns from the STC = 3 state to the STC = 1 state when the data transmission begins.

c) Request for emergency reconnection. During the transfer of data from the peripheral terminal 50 to the LCP processor, when the intermediate memory 2500 is completely full, an intermediate memory transfer flip-flop (BFXFRF) is set, and this initiates a reconnection request on the system 10 for storing data (the intermediate transfer flip-flop BFXFRF is set to state when the intermediate memory 2500 of the LCP processor is filled with data from the peripheral terminal 50 or when it has been emptied during the transfer data from the LCP processor to the peripheral terminal). If a reconnection is not performed before the UART device 31 receives another character, the circuit creates an emergency request level (EMRREQ). The EMRREQ level is sent to the corresponding 20ocj distribution card to start an emergency reconnection request on system 10.

d) Receipt of a final code (AB digits). The actions of the LCP processor concerning the reception of a final code, which is placed on the digits AB (first character) of a word, are more modified than those concerning the reception of a final code intended to be placed in the digits CD of a word. This condition exists due to the transmission of the peripheral terminal which can be composed of data and followed by a final code or even by the final code itself. In addition, the decrease (decrementation) of the system memory address may or may not be requested during storage of the final code, to translate the precise position of the final code in the system memory 10m. The following actions of the LCP processor corresponding to the various conditions will be described below in paragraphs dl and d2.

dl) Reception of the final code following data. If the final code follows a series of data characters and is received on the terminal bus 47 when the even flip-flop (EVNF) is set to the state, the character, when stored, is placed in the position of digits AB of a word from the intermediate memory 2500 of the LCP processor.

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When the character is received, the final code level (EDCODE) is created, so that the 18 L RAM memory (final registration mark level) is active and the final mark level (ENDFG) is stored in the address of the current intermediate memory. The final code level (EDCODE) is created on the terminal control card when a final code character is contained in digits A and B of the terminal bus 47. The final marker level ENDFG is created on the passage of data from the RAM 18 L memory and, when this level is active, it identifies the address of a final code in the intermediate memory 2500 of the LCP processor. The final registration benchmark level (RAM 18 L) is the data entry level of the final benchmark RAM memory of the intermediate memory 2500 of the LCP processor. Putting the pair flip-flop (EVNF) in the state then changes the address of the intermediate memory to the next word address. The setting of the data storage flip-flop (DATSTF) and the complement operation on the even flip-flop (EVNF) are then authorized. When the EVNF flip-flop is reset, the registration authorization level A (ERWA) is created and the final code is stored in the digits AB of the intermediate memory address, following that of the storage of the final benchmark level (ENDFG). The LCP processor then starts a reconnection request on the system to transfer the data and the final code to system 10.

During the final transfer of the data from the intermediate memory 250o from the LCP processor to the system 10 in the STC 4 state, a final code contained in the digits AB of a word will be recognized when the level ENDFG (level of final marker) is active and that the final code level of the system (SYSEND) is inactive. This logical combination indicates that the next word to be transferred contains a final code in the AB digits. In fig. 7E, the LCP processor goes to state STC = 14 to transfer a single character. In the state STC = 14, the setting of the word transfer control flip-flop (WTCF) is unconditionally authorized. The setting of the character transfer flip-flop (CTSF) is authorized to indicate that one is in the character transfer state. The final code is stored in the system memory 10m and the LCP processor first goes to the state STC = 12 to send a longitudinal parity word LPW to the system 10, then to the state STC = 7 to send a descriptor R / D result to system 10.

d2) Receipt of the final code only. As in fig. 7E, in the state STC = 1, if the transmission from the peripheral terminal 50 is a single character (final code), this character will be received on the terminal bus 47, the even flip-flop EVNF being set to the state; this signal will be placed in the position of digits AB of a word from the intermediate memory 2500 of the processor LCP. The character is stored and the LCP processor starts a reconnection request on the system to transfer the character as shown in the third block of fig. 7E in state STC = 5. The system goes to state STC = 4 and, when the final code level (EDCODE) is active, the setting of the end of character flip-flop (CHARENF) is authorized. The character is transferred to system 10 (state STC = 14) and the LCP processor goes to state STC = 12 to send a longitudinal parity word LPW to system 10. In state STC = 12, state CHARENF ( end-of-character flip-flop) puts the LCP processor directly in the STC = 9 state to initiate the decrease in the memory address 10m of the system.

Then the LCP processor goes to the state STC = 7 to send an R / D result descriptor to the system 10.

e) Receipt of a system termination signal. A termination signal (TERM level) is sent from the system to the LCP processor during a read operation, whenever memory space is available, to indicate that the operation of the LCP processor has been exceeded. During a read operation, the TERM level can be received (fig. 7E) in the states STC = 4, STC = 14 or STC = 12. The actions of the LCP processor upon reception of the TERM level depend on the counting state in which the LCP processor works when it receives the TERM level and how or not the reception of the TERM level is treated by the reception of a final code character from the peripheral terminal 50. Under these conditions, the actions of the LCP processor are examined in the following paragraphs e1 and e2.

el) Receipt of a termination signal before receipt of a final code. If the LCP processor receives the TERM level (termination signal) from the system before it has had sufficient time to receive and store a final code, the LCP processor operates as follows:

el (a) The reception of the TERM level while the LCP processor transfers data to the system in the STC = 4 state puts the terminating flip-flop (TERMF) in the state and the LCP processor enters the STC state = 12. A longitudinal parity word LPW is sent to the system 10 and setting the termination level state (TERMF) causes the LCP processor to complete the read operation and go to state STC = 7 to send a descriptor of R / D result to system 10.

el (b) In fig. 7E, the LCP processor goes from the STC = 4 state to the STC = 12 state after transfer of a word containing a final code in the CD digits for the system 10. If the TERM level is then received in the state STC = 12, setting the word transfer control flip-flop (WTCF) is authorized and the LCP processor remains in the state STC = 12 for an additional trigger time. If, during the second trigger time, the TERM level is still active, this indicates that the final code has not been transferred. The setting of the TERMF level (termination flip-flop) is authorized and the LCP processor goes to the state STC = 7 to send an R / D result descriptor to the system 10.

el (c) The LCP processor goes from state STC = 4 to state STC = 12 if the last word of the intermediate memory 2500 has been transferred. The TERM level is then received in the STC = 12 state, and the LCP processor remains in the STC = 12 state for an additional tripping time. The word transfer control flip-flop (WTCF) is put in the state and, whatever the logical state of the TERM level during the second trigger time, the LCP processor ends the read operation and goes to state STC = 7 to send an R / D result descriptor to system 10.

el (d) The LCP processor is in the STC = 14 state, if the last data word transferred to the STC = 4 state must be followed by a final code in the digits AB of the next word. If the TERM termination level is then received in the STC = 14 state, the final code is not stored and the LCP processor goes to the STC = 12 state; it sends an LPW character to the system, then goes to state STC = 7 to send an R / D result descriptor to system 10.

e2) Receipt of a termination signal after receipt of the final code. If the LCP processor receives the termination level (TERM) from the system 10 after having received a final code from the peripheral terminal 50, the LCP processor acts as indicated in paragraphs e2 (a), e2 (b), e2 (c).

e2 (a) In fig. 7E, the LCP processor goes from the STÇ = 4 state to the STC = 12 state after having transferred a word containing a final code in the CD digits to the system 10. If the TERM level is then received in the STC state = 12, setting the word transfer control flip-flop (WTCF) is authorized and the LCP processor remains in the state STC = 12 for an additional tripping time. If, during the second trigger time, the TERM level is no longer active, this indicates that the final code has been transferred. The LCP processor then goes to the state STC = 7 and sends an R / D result descriptor to the system 10.

e2 (b) The LCP processor goes from state STC = 4 to state STC = 14 if the last word transferred to state STC = 4 must be followed by a final code in the digits AB of a word. If the LCP processor goes to the STC = 14 state without receiving a TERM level, the final code is transferred to the system 10 and the LCP processor goes to the STC = 12 state to send a longitudinal parity word LPW. If the TERM level is now received in the STC = 12 state, the LCP processor does not perform any operation during reception, but goes to the STC = 7 state to send an R / D result descriptor to the system 10.

e2 (c) If the transmission from the peripheral terminal 50 is a single character (final code), if the LCP processor is in the state STC = 4, it s

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authorizes the setting of the end-of-character flip-flop (CHARENF) and goes to state STC = 12 to send a longitudinal parity word LPW. In the STC = 12 state, if the TERM level is now received, the LCP processor remains in the STC = 12 state for an additional trigger time. If, during the second trigger time, the TERM level is still active, this indicates that only the first half of the word containing the final code has been transferred and the memory address of the system has not been increased to go to l next word address. The LCP processor goes to STC = 7 to send an R / D result descriptor to the system 10. If the TERM level is inactive during the second trigger time, this indicates that the memory address of the system has been increased and moved to the next word address, requiring a decrease. The setting of the end-of-character flip-flop (CHARENF) and the inactive state at the termination level (TERM) causes the LCP processor to go to the STC = 9 state and begins to decrease the address of system memory. Starting from the STC = 9 state, the LCP processor goes to the STC = 7 state and sends an R / D result descriptor to the system 10.

Error conditions. During the course of a read operation, certain error conditions may occur to which the LCP processor reacts as follows:

a) Access error. After transmission of the emergency request level (EMRREQ), if the LCP processor has not had a reconnection on the system 10 before the reception of a second character in the UART device 31, the UART device 31 creates a level d 'overshoot error (OE). The OE level authorizes the access error flip-flop (ACCERF) and the final flip-flop (ENDF). The LCP processor then initiates a reconnection request on the system 10 to complete the read operation and send an R / D error result descriptor to the system 10.

b) Terminal vertical parity error. During the transfer of data from the UART device 31 to the intermediate memory 2500 of the LCP processor, if the parity error level (PE) is created by the UART device 31, the terminal vertical parity error flip-flop ( TVPERF) is implemented to indicate the existence of a vertical parity error. This TVPERF flip-flop has a logic state which is controlled by the output signal from the vertical parity controller / generator 48 of the LCP processor or by the parity error output of the UART device 31 (fig. 6D). The setting of the flip-flop indicates that a vertical parity error has occurred during the transfer of data between the LCP processor and the peripheral terminal 50. This flip-flop is placed on the terminal control card .

c) Block check character error. During the data transfer (fig. 6D) from the UART device 31 to the intermediate memory 250o of the LCP processor, if the block verification character agreement level (BCCOK) is not active after the verification of a character block check character, the block check character error flip-flop (BCCERF) is set to state and indicates the existence of a block check character error. The BCCOK level is provided by the decoder 34 of the block verification character register 33 in FIG. 6D.

Registration-reading operation:

This operation is essentially a registration operation followed by a read operation. In principle, the preceding description concerning the recording operation and the reading operation according to FIGS. 7B and 7C is applicable in this case. The reception of a C / D order descriptor of the operation transition from registration to reading in the OP code and the variant registers 42 and 43 (fig. 6D) ensures the initiation of a registration operation and the creation of a FLIP level (tilt level). The data is transferred from the system 10 to the peripheral terminal 50 during the registration part of the operation. When a final code is recognized on the terminal bus 47 during a data transfer from the LCP processor to the peripheral terminal 40 in the state STC = 1, the circuit creates the final code level (EDCODE). The EDCODE level authorizes the setting of the final flip-flop (ENDF) indicating that the transfer of

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data is completed. The setting of the final flip-flop (ENDF) and the creation of the FLIP level authorize the setting of the read flip-flop (READF), the terminal reception flip-flop (TRECF) and the pair flip-flop (EVNF), resetting the registration flip-flop 5 (WRITF), terminal activity flip-flop (TRMBSYF) and presetting the intermediate memory address to the state MADR 255. As a result of these operations, the LCP processor is conditioned and can receive the data from the peripheral terminal 50 without being reconnected to the system 10 to receive additional instructions.

To initiate the reading part of the read switching operation, the LCP processor does not reconnect on system 10. As in flg. 7E, the LCP processor goes from state STC = 1 to state STC = 3 to wait for a transmission from the peripheral terminal 50. The reception of the first character from the peripheral terminal 50 activates the DR level (data reception ) of the UART device 31 and authorizes the setting of the UART flip-flop (RSUARTF) and the terminal activity flip-flop (TRMBSYF). Setting the terminal activity flip-flop causes the LCP processor 20 to return to the state STC = 1 to receive the data. The read operation continues until completion, being subject to the same conditions as those indicated above for a usual read operation.

Test operation:

The test operation allows the system 10 to determine the operating state of the LCP processor without requesting an exchange of data with the memory 10m of the system. A test flip-flop (TESTF) is provided on the data pass card. The logic state of this flip-flop is controlled by the output levels of register 42 30 of OP code (fig. 6D). The setting indicates that a test instruction has been received by the system 10. In FIG. 7E, in state STC = 11, when the test flip-flop (TESTF) is set to state, the LCP processor has no request to go to state STC = 6 and receive a link of descriptor D / L. Instead, it goes to the STC = 7 state to return to an R / D result descriptor in the system 10. From the STC = 7 state, the LCP processor goes to the STC = 15 state, then in state STC = 3 (free state), in which it remains until the reception of another descriptor of order C / D. Under normal conditions, the R / D result descriptor sent to the system 10 for a test operation 40 presents zeros at all the bit positions. The system 10 then notes that the LCP processor is operational.

The reception of a C / D order descriptor containing a test authorization instruction conditions the LCP processor so that the peripheral terminal 50 can start a communication 45 with the system 10. The peripheral terminal 50 begins a communication request by sending an investigation character (ENQ) to the LCP processor. Upon receipt of the inquiry character (ENQ), the test authorization operation ends and the system begins a read operation in order to receive the data from the peripheral peripheral terminal 50. If the terminal sends any other character except a ENQ inquiry character, the character will not be recognized and the LCP processor takes no action. The test authorization operation takes place as follows (see fig. 7E):

In the STC = 3 state, on receipt of a 55 test authorization instruction, the flip-flop number 3 of the variant register (VAR3F) is set to the state. The expression VAR (1-4) F represents 4 levels of variant register. These levels are created by the data passage card, by the outputs of the variant register 43 (fig. 6D). The logical state of these levels depends on the numerical value contained in the digit of "> variant 1 of the C / D order descriptor. The setting to the state of VAR3F prohibits the setting of the test flip-flop (TESTF) but allows the setting of the read flip-flop (READF). The LCP processor goes to state STC = 11 to receive the order descriptor of the longitudinal parity word LPW from the system 10, then it goes to state STC = 665 to receive the descriptor link D / L from the system . In the STC = 6 state, as the read flip-flop (READF) is put in the state, the LCP processor disconnects from the system 10 and goes to the STC = 1 state to receive an inquiry character (ENQ ) from the peripheral terminal

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than 50. In the STC = 1 state, unless an inquiry character (ENQ) is received immediately, the LCP processor goes to the STC = 3 state to wait for the transmission from the peripheral terminal 50. When the terminal device transmits, the terminal activity flip-flop (TRMBSYF) is put in the state, so that the LCP processor goes to the state STC = 1 to receive the inquiry character (ENQ). When the ENQ character is received, setting the VAR3F variant register level prevents the LCP processor from going to state STC = 4; it also prohibits the transfer of the character to the system 10. Instead, the LCP processor enters the STC — 1 state and returns an R / D result descriptor to indicate to the system 10 that the test authorization operation is completed.

Conditional delete operation:

The conditional delete operation allows the system 10 to delete a previously sent C / D order descriptor containing a read operation. According to fig. 7E, when the LCP processor has started a read or read / pass / write operation, but the planned data transfer from the peripheral terminal 50 is not in progress, the LCP processor remains in the state STC = 3 pending a possible conditional deletion instruction. If it then receives a conditional delete instruction, the read operation is deleted and the delete flip-flop (CANCF) is set to the state. This deletion will not be carried out before the LCP processor is in the STC = 3 state. The LCP processor then goes to the state STC = 11 to receive a longitudinal parity word LPW from the order descriptor coming from the system 10. Putting the CANCF suppression flip-flop in the state prevents the LCP processor from passing STC = 6. Instead, the LCP processor goes to STC = 7 to return an R / D result descriptor to system 10, indicating that the conditional delete operation is complete.

Echo operation:

The echo operation is a maintenance aid, to search for incidents in the LCP processor. This operation begins with the registration operation in which the data is transferred from the memory 10ra of the system to the intermediate memory 2500 of the LCP processor. This operation is followed by a read operation, during which the same data is transferred back to the system memory 10m. It is assumed for example that less than one data charge from a complete intermediate memory will be transferred and that the operation ends with the reception of a final code in at least one character position of a word; as the echo operation is essentially a registration operation followed by a read operation, the following description relates only to the actions of the LCP processor which are specific to this echo operation (the read and registration operations have been examined previously in relation to the fig. 7B and 7C). According to fig. 7E in state STC = 6, and when the echo flip-flop (ÉCHOF) is put in state the LCP processor goes to state STC = 8 and accepts data from system 10. Starting with state STC = 8, the LCP processor operates as described above during a normal registration operation, until the LCP processor receives a final code, then goes to state STC = 12. In state STC = 12, although 'no data is transferred from the LCP processor to the peripheral terminal 50, the LCP processor cuts off from the system 10 passing momentarily through STC = 1. If it is connected in the state STC = 1, the LCP processor initiates a request for reconnection for system 10 by authorizing the placing of the LCP request flip-flop (LCPRQF) of the I / O sending flip-flop (IOSF) and by presetting the intermediate memory address to the MADR state 253. The LCP processor then goes to state STC = 5 and sends the descriptor link D / L to the system 10. In state STC = 5, the LCP processor transfers the descriptor link D / L to the system 10. Setting the echo flip-flop state (ÉCHOF) then brings the LCP processor back to the STC = 4 state to return the data from the intermediate memory 2500 to the system memory 10m. Starting at the STC = 4 state, the data is transferred from the LCP processor to the system 10. The actions to be performed by the LCP processor are those previously described during a normal read operation, until the LCP processor identifies a final code on terminal bus 47, then goes to state STC = 12. In the STC = 12 state, the read operation is finished and the putting into the state of the echo flip-flop (ECHOF) causes the LCP processor to go to the STC = 7 state and returns a result descriptor System R&D 10.

Return of the R / D result descriptor:

Fig. 7D is a simplified logic diagram concerning the return of the R / D result descriptor. The LCP processor enters the STC = 7 state to return an R / D result descriptor to the system 10 under any of the following conditions a, b, c, d:

at. In the STC = 12 or STC = 9 state, when a read or echo operation is completed.

b. In state STC = 5, when a registration operation is completed.

vs. In the state STC = 11, when any of the following conditions occurs:

cl) Descriptor error.

c2) A test operation is executed as specified by the C / D order descriptor.

c3) The conditional suppression flip-flop (CANCF) is set to the state.

d. In the STC = 6 state, if a longitudinal or vertical parity error has occurred.

In the state STC = 7, if the transmission flip-flop (XMITF) is not put in the state, it is implemented at this time to activate the reading module of the LCP processor. The selection level A of the terminal bus multiplexer (SLARAM) and the selection level B of the terminal bus multiplexer (SLBRAL) are both active, which allows the network of the terminal bus multiplexer (24x2, flg. 6D) to choose a word formed from the result descriptor levels for transmission to the system 10. When the result descriptor word is placed in the data locking circuits, it is also applied to the register 24w of character LPW to create a LPW character for the transfer of result descriptor. The LCP processor then goes to the state STC = 15 and sends the R / D descriptor of the character LPW to the system 10.

At state STC = 15, the selection level A of terminal bus multiplexer (SLARAM) is inactive and the selection level B of terminal bus multiplexer (SLBRAM) is active, which allows the multiplexer circuit to terminal bus (24x2, fig. 6D) to choose the outputs of the 24w register for transmission to system 10. (The SLBRAM level is used in combination with the SLARAM level to choose one of the four inputs of the terminal bus multiplexer .) These levels are created on the logic board of the system from the output signals of the STC = 54 decoder in fig. 6D. The LCP processor transfers the LPW character, returns the selected logic levels to the initial state and goes to the STC = 3 state. The LCP processor remains in the STC = 3 state until the reception of another C / D order descriptor.

In summary, the LCP processor operates in two modes: offline mode and online mode.

Offline mode:

The operation of the LCP processor / peripheral terminal combination in offline mode is used for maintenance. In each domain, multiple operations can be carried out to check the situation of the LCP processor or simply to search for faults. These operations can be carried out without normally implementing the other LCP processors of the same basic module.

Online mode:

In summary, the two basic operations controlled by the LCP processor in online mode are:

1) the registration operation during which data is received from the system by the LCP processor; this data is transferred to the peripheral terminal;

2) a read operation during which data is received from the peripheral terminal by the LCP processor and is transferred to the memory 10m of the system.

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In addition to these two basic operations, the LCP processor can pass from a registration operation to a read operation by a simple instruction; it can also perform selected test operations. The following points represent the characteristic operations that the LCP processor can perform using an instruction program of the main system 10. This is done by the order descriptors (C / D); a summary of these operations is given in table XII.

Table XII

at. Registration e. Authorization test b. Reading f. Conditional deletion c. Reading passage inscription g. Echo d. Test

Order descriptors:

The order descriptors (C / D) are instructions of the main system 10 for the LCP processor and which relate to certain operations to be carried out. The following elements summarize the order descriptors associated with each of the instructions (table XII) of the main system 10:

a) Registration:

The registration order descriptor is an instruction to transfer the data from the memory 10m of the system to a chosen peripheral terminal, for example the peripheral terminal 50. The LCP processor accepts the data from the system 10 until the intermediate memory 2500 of the LCP processor is for example complete or until the data transfer is stopped by the reception of a final code or of a termination signal from the main system 10. If the intermediate memory 2500 of the LCP processor is complete in if the final code is received, the LCP processor transfers the content of the intermediate memory 2500 to the peripheral terminal 50. The registration order descriptor is identified as indicated in table XIII.

Table XIII: (CjD entry)

Data lines

Numerical value

AT 8

0 ï

A4

1 |

A2

0> Digit OP

Al

0 J

B8

0 Ì

B4

0 d

B2

0 f Digit of variant 1

Bl

0 J

b) Reading:

The read order descriptor is an instruction for transferring data from the peripheral terminal concerned such as the terminal 50 via the memory 10m of the system. The LCP processor first accepts the data from the peripheral terminal 50 until the intermediate memory 2500 of the LCP processor is complete or until the data transfer is stopped by the reception of a final code from the peripheral terminal . When the intermediate memory 2500 of the LCP processor is complete (or on receipt of the final code), the LCP processor transfers the contents of the intermediate memory 2500 via the memory 10m of the system unless the main system 10 sends a signal termination to stop the read operation since there is no more memory space available for storing additional data. If, after the initiation of a read operation, the LCP processor does not receive data for a period corresponding to 1 s, the LCP processor counts down the time and sends an R / D result descriptor to the main system 10. The 1 s time interval can be prohibited by setting a bit (Bl) of the variant 1 digit of the order descriptor equal to 1. Table XIV corresponds to the C / D read operation.

Table XIV: (reading CjD)

Data lines

Numerical value

AT 8

1

•)

A4

0

((

A2

0

r Digit OP

Al

0

J

B8

0

"1

B4

0

1

B2

0

r Digit variant

Bl see note

J

(If Bl is equal to 1, the 1 s downcount period allocated to a terminal to respond is prohibited.)

c) Pass reading-reading:

The entry-read pass descriptor is an instruction for the LCP processor, which must carry out a registration operation and, immediately after this operation, a read operation without any intervention from the main system 10. The data is accepted from of the main system 10 and is transferred to the peripheral terminal until the reception of a final code. Upon receipt of the final code from the main system 10, the LCP processor transfers the final code to the peripheral terminal, then enters read mode. The LCP processor then accepts the data from the peripheral terminal and transfers it to the memory 10m of the system until the reception of a final code from the peripheral terminals or until the sending of a termination signal from the main system 10. If, after the start of the reading part of this operation, the LCP processor does not receive data for a period of 1 s, the LCP processor counts down the time and sends a result descriptor (R / D) to the main system 10. It is obvious that the time interval of 1 s can be prohibited if necessary by setting the bit Bl of the digit of variant 1 of the order descriptor to state 1. Table XV corresponds to the descriptor order entry registration-reading.

Table XV: (passage inscription-reading C / D)

Data lines

Numerical value

AT 8

0

A4

1

1

A2

0

) "Digit OP

Al

0

J

B8

1

B4

0

1

B2

0

f Digit variant

Bl see note

J

(If Bl is equal to 1, the countdown period of 1 s allocated to the terminal for responding is prohibited.)

d) Test:

The test order descriptor is an instruction for the LCP processor to indicate its operating state by returning an R / D result descriptor to the main system 10. If the LCP processor is present and available, the result descriptor is formed of 0. Table XVI relates to the test order descriptor.

Table XVI: (CjD test)

Data lines

Numerical value

AT 8

0 ")

A4

0 1

A2

1> • Digit OP

Al

0 J

B8

0 "Ì

B4

0 Ì

B2

0 f Digit of variant 1

Bl

0 J

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e) Authorization test:

The authorization test order descriptor is an instruction for the LCP processor to check the input data coming from the peripheral terminal; on receipt of an inquiry character (ENQ), the processor forms and transmits an R / D result descriptor to the system 10. This instruction is used to allow the peripheral terminal to initiate communication with the main system 10. Table XVII shows this order descriptor.

Table XVII: (C / D test authorization)

Table XVIII: (conditional deletion CjD)

Data lines

Numerical value

AT 8

0 1

A4

0 (

A2

j r Digit OP

Al o J

B8

0 Ì

B4

1 l •

B2

0 r Digit variant

Bl see note

Data lines

Numerical value

AT 8

0 1

A4

0 1

A2

j> Digit OP

Al

0 J

B8

1 1

B4

0 I

B2

0 r Digit of variant 1

Bl

0 J

(If Bl is equal to 1, the 1 s countdown period allocated to the terminal for responding is prohibited.)

f) Conditional deletion:

The conditional deletion order descriptor is an instruction sent to the LCP processor to start deleting another order descriptor under certain conditions. When the conditional deletion order descriptor is received by the LCP processor, and if the data is not received from the peripheral terminal during the applicable part of a read operation, then the previous order descriptor will be deleted. This C / D descriptor is shown in Table XVIII.

g) Echo:

The echo order descriptor is an instruction for the LCP processor to accept a complete intermediate memory of data (or less) from the main system 10 and to return them to the main system 10 to be stored. This constitutes a maintenance check and a diagnostic troubleshooting cycle for system-LCP operation. Table XIX represents this echo order descriptor.

Table XIX: (echo C / D)

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Data lines

Numerical value

AT 8

0 Ì

A4

0 (

A2

q> Digit OP

Al i 3

B8

0 Ì

B4

0 1

B2

q r Digit of variant 1

Bl

0 3

23 sheets of drawings

Claims (5)

632,350 CLAIMS 1. Data processing assembly comprising several remote peripheral terminals, each peripheral terminal being connected to its own specific peripheral controller (20oo to 20O7), characterized in that several of these peripheral controllers are organized in groups designated as basic modules, such each basic module has its own message level interface bus (15) connecting it via a main interface (10t) designated as input / output translator, to a central main unit (10), presenting a main processor (10p) and a main memory (10m) and in that the input / output translator (10t) comprises means for connecting and disconnecting the selected peripheral controllers with the main memory without interrupting the main processor as well as means for formulating orders input / output data transfer and to form a descriptor link identifying each data transfer order for each e particular peripheral controller, a peripheral processing controller (20oo) in this assembly comprising: a) means (24xl, 23r, 28r) for receiving information data and instruction data from its peripheral terminal (50) and from the main unit (10); b) a buffer memory (250o) for temporarily storing the information data and the instruction data, the buffer memory comprising: b 1) a memory space (25a, 25b) for storing at least one complete message block; b2) a memory space (25c) for storing an instruction word received from the main unit; b3) a memory space (25d) for storing the descriptor link specific to the peripheral controller; c) logic means for executing instruction data received from the main unit; d) register (53) and decoder (54) means for developing status signals controlling the instruction sequence to be developed by the peripheral controller in accordance with a predetermined sequence and for conveying to the main unit (10) signals representing the steps completed in the execution of the instruction data; e) logic rate means for supplying an information signal to the register and decoder means, said logic rate means detecting each operational step in the execution of an instruction and conveying the detected signals to the register (53) and decoder means (54). 2. Assembly according to claim 1, characterized in that it comprises a peripheral controller provided: - means (22di) for interchanging the data with its peripheral terminal at the processing speed authorized by this peripheral terminal while the peripheral controller is disconnected from the main unit and connected to the peripheral terminal (50); - means (21 sî) for independently interchanging the data with the main unit at the processing speed authorized by the main memory while the peripheral controller is disconnected from the peripheral terminal (50) and connected to the main unit (10) . 3. Assembly according to claim 1, characterized in that the peripheral processing controller (20oo) comprises: - means (24XI, 24X2,47,2500) for conveying an instruction word received from the main unit to the logical means for execution without further attention from the main unit (10), and - means (34,44,51,48) for producing result descriptor signals to be transmitted to the main unit (10) when the instruction word has been completely executed, these means comprising a result descriptor logic (24rd) responding to an end of message block character transmitted when each block is complete. 4. An assembly according to claim 3, characterized in that it comprises a peripheral controller (20oo) further provided with means (22di; 21si) responding to signals from the main unit, to signals from the peripheral terminal, and to signals produced by the peripheral controller itself to detect an incomplete execution of an instruction word or an incomplete transfer of data and to report this fact to the main unit. 5. Assembly according to claim 3, characterized in that the buffer memory (2500) of the peripheral controller comprises a memory space (25r) for the storage of a result descriptor word produced by the result descriptor logic (24rd) for the subsequent transfer to the main unit (10).