CA1073546A - Interface and dispatching system for telecommunications exchanges - Google Patents

Abstract

Articulation and management system for a telecommunications center in which the exchange of messages between a processor and the mini front processors is carried out by couplers installed in the processor and the mini front processors; the couplers are connected via a bus-silo. The couplers have their own logic allowing information to be exchanged by direct memory access at the processor level and by word-by-word programmed mode at the front mini-processors.

Description

~ 735 ~ 6 The subject of the invention is an articulation of logic, in particular of computers assigned to the management of a center telecommunications tral.
We know by Canadian patent application No 218. ~ 74 of January 23, 1975 the general articulation of such a management system tion which includes, on the one hand, several computers or "mini front processors "working independently, each of them managing part of the operations necessary for processing and communications service, on the other hand, a central unit of control by a central computer or "central processor" loaded essentially to control the front mini-processors rate, the set working in asynchronous mode.
The central unit also includes a processor maintenance connected to the front mini-processors and working in asynchronous mode with these, said maintenance processor being completely autonomous vis-à-vis the central processor.
According to the invention, an articulation and management system for telecommunication exchanges comprising, on the one hand, mini front processors managing each one, in asynchronous mode and so autonomous, part of the operations necessary for processing and communications service, and on the other hand, a central unit comprising a central processor associated with a central memory, a maintenance processor associated with a maintenance memory, said processors each also working in asynchronous mode and autonomously, the central processor orchestrating the activity of mini-processors and the maintenance processor controlling the normal progress of the tasks of said mini ~ rocessors, characterized by the fact that the exchange of messages between the mini-processors front and both CPU processors are performed through pairs of couplers ~ CFDl-CCDl, CFD2-CCD2) each connected to the ends of two bus-silos (bsl, bs2).
Each coupler of the same pair includes a central coupler of ~ r -1- ~
~ L ~ 7354 ~
dialogue (CCD) integrated into a central processing unit and a Front dialogue coupler (CFD) integrated into a mini-processor frontal. A bus-silo is split into two identical bus lines as soon as it leaves the central dialogue coupler. Each bus line consists of a pair of wires running from cabinet to cabinet and on which are cut as many branches as there are frontal. Information exchange between a central processor and front mini-processors are transmitted in the form of messages mutually variable lengths between the central coupler dialogue (CCD) and the front dialogue coupler (CFD) on said bus-silo so that the front dialogue coupler realizes said exchanges by program mode word for word at the level of the front processors, and that the central dialogue coupler (CCD) carry out said exchanges of information by direct memory access at the level of the central processor therefore without per-turbation of the unwinding ment of its program. The coupler to coupler exchanges are independently supervised by the central dialogue coupler and asynchronous to the central processor.
The present invention relates more particularly to the respective design of the dialogue front coupler and the coupler central dialogue, said couplers each comprising a lo-Clean, very elaborate and non-dependent gic allowing exchanges information management carried out by direct memory access at the central and by word-for-word program mode at the front ends.
The characteristics of the dialogue system according to the vention will be well understood by the description and the function-nement of an embodiment given only by way of example ple, and illustrated by the figures of the accompanying drawings in which:
- Figure 1 is a general diagram of the connections the couplers of the front mini-processors and the coupler of the central processor on the one hand, between the couplers of said front ends and the maintenance processor coupler, on the other hand;

- 2 -~ 07354G
- Figure 2 is a logic diagram of the front coupler of dialogue;
- Figure 3 shows the central dialogue coupler in its environment and a frontal dialogue coupler, and - Figures 4, 5, 6 show the logic diagram of the central dialogue coupler.
In Figure 1, the central processor PC and the pro-PM maintenance stopper each have a central coupler of dalogue CCD. Each CCD drives a bs bus-silo, the coupler CCDl from PC driving the bsl bus-silo, the CCD2 coupler from PM pilo-both the bs2 bus-silo. Each bus-silo of a coupler is double in output in two identical buses, bsla and bslb for the bus-silo bsl and bs2a, bs2b for the bs2 silo bus, connecting the central coupler CCD dialogue couplers to one of the two CFD dialogue front couplers.
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_. , ~ 735 ~ 16 frnntau ~ MPF mini-processors. Each doubled bus-silo is connected to n rows of front mini-processors MPF1 to MPF4 ~
For example, the bus ~ silo bs1a of the central dialogue coupler CCD1 is connected by its ends Y1a and X1 to the front couplers of CFD1 dialog of the ~ rontal mini-processors MPF1A to MPF4A, MPF1B to MPF4B, . ~ ... MPF1D to MPF4D, i.e. 15 FOO front-end mini-processors to F15 distributed in four rows of four front mini-processors MPF1 to MPF4 as represented in the articulation and management system.
Analogously. the bs1b bus-silo is connected by its ends Y1b and X1 to front couplers of dlalo ~ ue CFD1 of mini-processors MPF1E to MPF4H front-end, i.e. to a second group of 16 mini ~ processors front F16 to F31 distributed in four rows of four.
The connection of the PM maintenance processor on the 32 mini front processors MPF1A to MPF4H is realized ~ e similarly to ~ oyen des bus-sllo bs2a and bs2b connecting by their ends Y2a-X2 and Y2b-X2 the CCD2 central dialogue coupler with CFD2 front dialogue modules said front m-lni-proces ~ eurs.
The front dialogue couplers C ~ D1 and CFD2 of each mini front processor such as MPF1A have a common bmf bus connecting said 2D couplers to the memory of said mini-processor. The central processor PC
poss ~ of 2 separate buses, one, bpc, connecting the central coupler CCD1 in the main memory of said processor and the other, bmc, rsliant dirsctement said coupler ~ the central memory of said tnon procasseur rspresented). Even the PM maintenance processor has, on the one hand, a bpm bus connecting the central coupler C002 to the memory of said processor and, on the other hand, a bmm bus connecting said coupler to the mainte-nance tnon represented ~ of said processor.
There is total independence between the bus-silo b ~ aJ bs1b which ensure the exchange of information between the central processor PC and all the front ones on the one hand, and the bs2a, bs2b bus-silo which ensure the exchange ~ 354 ~
information between the maintenance processor PM and said rontals on the other hand.
Each bus silo "a" and "b" is made up of twenty pairs of wires whose states are managed by the central dialog coupler. These connections are wired in three types depending on the direction of the signals they convey culent:
- central to front ssns - frontal directions towards csntral - bidirectional links.
Each bus line is made up of a pair of ~ they traveling from cabinet to cabinet and to which as many branches are connected that there are ~ rontals.
The connsxion of this central dialog to the bus-silo is made through a battery of bc relay contacts (not shown) said contacts being all established in normal operation. The command and the control of the state of these relays is obtained from the processors PC, PM of the central unit so that, if a front end is in disturbance, we can get a complete isolemsnt of this one compared to the system.
The general principle of the dialogue system is developed below.
The dialogue between the central processor and the process on maintenance) and the front mini-processors are made by exchange of messages composed of a maximum of 16 words of 16 bits.
At the level of a mini front processor a message is either loaded in a silo memory. be taken from it through the logic circuits of the front interface coupler. The mini-processor by its program takes into account the number of mcts composing the message for e ~ fsctuer, word by word, only the antrées or exits of nécsssaires words.
The msssage of a frontal towards the csntral includes in the head a filing address t1er mot) followed by several characteristics t2B mot) ~ 735 ~ 6 such as the number of information words, the number of the front end sender and type of message, and finally message information t14 words maximum).
At the level of a tPC or PM ~ processor of the central unit, the message from a front end is analyzed by the logic circuits of the central dialogue coupler (tCCD) which collects the deposit address of said message in a rotating input list and transfers information of said message in the mass memory central memory or memory of maintenance), depending on the deposit address.
The message from the central office to a front end does not include an address dep8t. The first word of the message indicates the number of information words, the number of the destination front end and the type of message. Information from messages total a maximum of 15 words.
We will now give the configuration of the logic diagram of the dialogue front coupler shown ~ iguro 2.
The front dialogue coupler is connected to the bus-silo of the coupler central dialogue via the bs1wX links, that is to say, if it is the oialogue CFD1 front coupler for example, at terminals X1 of the silo bus bs1a [figure 1 ~.
The connections of said bus-silo are distributed over an LVS logics of validation of the SLO silo memory and on a positioning logic of LPV channels.
LVS logic includes, in addition to a front-end number decoder DNF, a flip-flop which stores the recognition by said number decoder front end assigned to the coupler. The connections c1, c2 of validation command tVAL) and taking into account (STR) are linked to logic inputs LVS, one SV output of which is connected to a logic of the LES silo states as well than LPV logic. The latter also receives a c3 bond from read command tLEC ~ from the bus-silo, a derivation of the link c1 and a PV output of LVS logic ~
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A REP response c4 link of the LPV logic is unidirectional in the direction from the front coupler to the central coupler. Roads bidirectional pO to p15 of the bus-silo passing through the position logic-of LPV channels and are distributed over internal logical organs of the front coupler. Thus the channels pO to p3 are connected to the number decoder ds ~ rontal DNF and voiss p4 to p6 are connected to the LES logic of states of silo SLO, Lssitées channels p4 to p6 respectively issue COC orders, dsmande occupation in writing of the silo, CFE -Pin of writing by the central or CFL end of reading by the central, transmitted by the central coupler of dialogue s these orders attack a block of ECE flip-flops controlling, in depending on the orders received from the front-end or the central office, changes of state from the silo. This block consists of five flip-flops, each flip-flop corresponds to laying in one of the possible states of the silo so that only one rocker at the times indicates the current state of the silo, These scales respectively deliver ment, as the case may be, a FLE indication reading the silo while waiting or course by the ~ SIL free frontal silo, CLE lec: ture of the siln waiting or in course by central, loading of the silo by the central, FEC occupied silo in writing by the front end.
The previous indications are respectively delivered on the '' 20 input channels d14, daa, dO9, d10 and d12 of an MSF output multiplexer information to the ~ frontal. The ECE scale block also delivers the indication CLE on a channel p ~ or the indication CEC on a channel p9, said indications being returned to the central coupler via the medium of an MSC multiplexer for outputting information to the central office and of the LPV channel positioning logic. MSC multiplexer is active during the VALr validation command The input information presented on channels pO to p15 side bus-silo are directed by LPV logic on the inputs A of a multiplexer MES associated with the SLO silo ~ said multiplexer being unlocked ~ by the CEC command, silo occupied in writing by the central. The loading of the silo ~ L ~ 735 ~ 6 by the central, CSC, is effected by the actions con ~ uguqes of the indications CEC, SV and LEC, VAL and STR commands applied on a writing logic ~
ture LOE whose output is connected to the write input EC of the SLO silo.
The CEC indication presented on the LPV logic gives the exchange a response of writing delivered on the REP wire ~
The front dialogue coupler is connected to the mini-processor front by the bmf ~ Z links, that is to say, if it is the front coupler CFD1 associated with the PC processor for example tfigure 1), at the terminals Za of the bus bmf. These connections include, on the one hand, control wires such as F1 to f11 for example transmitters of orders or unidirectional states in one or the other direction and, on the other hand, bidirectional channels dO to d15 transmitters of messages. The connection of the bmf bus to the logic circuits the front coupler is made via the adapter ADF consisting of known adaptation circuits conforming to the type of front mini-processor used.
Channels dO to d15 are connected through the ADF adapter on the inputs B of the MES input multiplexer said multiplexer being made active ~
by the FEC state of the silo. A party tdO to dO8) of said channels is linked with a decoder of the tONC coupler number) then with the MSF multiplexer ; ~~ in order to transmit the number of the front dialogue coupler to the mini ~
front processor.
LB DNC decoder is connected by a CD link, decoded coupler, to a validation validation of the LVCJ coupler which is present on a sortle common an HW link connected through the ADF adapter to the f7 wire of the bus bmf from the front end and a CV link connected to the status logic of the LES silo.
The LVC log also has a SYN output and an ADRS input connected respectively on the wires fS and ~ 6 through ADF. An order delivered on HW means at the front that the coupler number is presented to it on a half-word tvoies d8 to d15) ~ The questioning ~ u ~ frontal on the number of coupler is received on ADRS and the coupler responds on SYN that it has received well this interrogation.
Instructions from the -Frontal can be stored by the state changeover flip-flops ~ CE ~ These are the instructions following:
- FOC - "request for writing occupation of the silo"
- FFE - "End of occupation in writing"
- FFL ~ End of reading N, These respective instructions are received under the form of a bit state 1 presented on a channel d101, d111, or d121. They are memorized in BCE by application to the LES logic of the CV command from LVC and a CMD command from the front end via the f1 link, Conversely, one of the following instructions on the state of the silo can be given to the front end by ~ CE logic.
- FLE - "Reading the silo while waiting or in progress by the front end" (state 1 on a road d14) - SIL - "Free silo" (goose dO8) - CLE - "Reading of the waiting silo or sn course by the central ~ tvoie dO9).
Since the link d14 is connected to an interruption logic LI, a interruption can be generated to the front coupler when the silo goes into FLE state. I ss p6 st dO8 links being connected to said interrupt logic, the conjunction of the CFL command, end of reading by centralD and state SIL silo librs, permst also to gsn ~ rer uns interruption to the front end before it makes a request FOC write occupancy of the silo. LI logic issues ATN commands on the f2 link of the front end in order to order it to eM ectusr an interruption, that is to say that the front end must temporarily stop all traffic in order to devote ~ reading the silo of the interruptor coupler.
The front end responds by returning an acknowledgment signal to LI logic receptacle tRAC ~ on the wire ~ 3 ~ The interrupt logic LI present then on its output VDJ connected to the DNC decoder, a command validating said decoderUr which tran5 ~ Bt 18 number of the coupler at the front end on the dO8 channels d15 through the MSF multiplexer.

~ 73 ~, ~ 6 The bmF bus being coupled on two front dialogue couplers, CFD1 and CFD2, figure 1, that of the two couplers which is the interruptor will not transmit TACK to the other while keeping the RAC signal for him.
The front end can, if necessary, mask the interruption by presenting both via dOa1 a status command 1 on an input of the logic of interruption ~ He can then remove the masking of the interruption by a status command 1 presented to said logic by the channel dO91.
When the front end wants to know the state of the silo it presents a request to read status tSR) on Pil f10 and input A of the multiplexer 1D MSF which selects data from state control flip-flops BCE ~ When said frDntal wishes to know the content of the silo, it presents a request to read OR data on wire f11 and input B of the MSF multiplexing which selects the data present at the output of the silo SLO.
LB front loading of the silo is preceded by a DA command t data available) presented on thread f12. Data arrive on inputs of the MES multiplexer via WiB! 3 dO ~ d15. The write command of a word in the silo is given by the writing logic LûE which collects both 1e5 FEC commands tsilo occupied in ~ writing by the ~ frontal), DA
t data available) and CV t coupler validated).
The passage in writing or in reading of a following word is carried out via a RAD register giving the successive address of silo lines, said register being connected to forward LAA logic address. The DA command of the Prontal con ~ ugué to the FEC and CV states received by LAA logic allow it to control the advance of the address in the case of ~ writing by the -Prontal ~ In the case of a reading by the Prontal, LAA logic operates address advancement by the DA command on the Prontal con ~ uguée aux states FLE ~ t CV.
The central LEC, VAL and STR commands associated with ~ CEC states and SV allow LAA logic to control the RAD address register 73S ~;
in order to designate the next line of the silo for a writing coming from the central. In the case of a reading of the silo by the central office, the indication CLE
replaces the CECJ indicator, the other commands remaining unchanged, The indication CLE presented on LPV logic gives the central unit a read response shown on the REP wire.
The address register ~ AD is a divider by 1G. It is rsmis at zero with each change of state of the silo, the rockers ~ CE of change status with a zero address command AD0 on the RZ input of said address register. This can also be reset to zero directly at from the front end which then presents an FZA command on channel d131, said command being received in the state logic of the LES silo and returned on the RZ entry of the address register.
The silo outputs are connected on the one hand, to the MSF multiplexer andJ on the other hand, to the LPV channel positioning logic either direct for channels pO to p7 and p10 to P15J either through the MSC multiplexer for channels p8 and p9. The MSC multiplexer is released rou ~ llé by VAL or SV commands.
The silo is locked by means of an "OR" door, VS
a first input of which is connected, on the one hand, to a positive polarity at through a resis ~ ance and, on the other hand, central side, to a contact ds work of a bus-silo connection relay, lsdit contact being connected to the earth ~ The second and third inputs are linked to the front-end bus by son f ~ and f9, said front having on one or the other wire a SCL or CL0 command depending on whether the front end coupler is not plugged into the chassis of the front mini-processor or that said front is not powered.
The V5 ports then deliver a lock command INI = 0 on the logic state of the LES silo which prohibits any reading or writing of said silo, Similarly, if the coupler on the front is not connected to the coupler central ~ rels de connsxion du bus-silo au rspos), the positive potential applied through the resistor on the side of the door VS permst to ~ i735 ~ 6 This is to issue the locking command INI = 0, said command otant reported to the ~ rontal by the way d15.
The front coupler being connected to the bus-silo, the relay connection of said bus present by a contact, a state 1 on the door VS which issues an availability command INI = 1, said commands unlocking the silo state logic. The silo can thus be used in reading or writing by the first central or front-end program which requests it ~
We will now give an example of a logical sequence operations of reading and writing the silo by the central and by the frontal.
A - TRANSMISSIDN FROM A MESSAGE FROM THE CENTRAL TO A FRDNTAL -1 - Designation of a front end by the csntral -The central coupler simultaneously presents the pulse-VAL tvalidation) and STR taken into account) on the validation logic sllo LVS which, by its PV output and via LPV logic, gives the central office a REP response acknowledging receipt of said orders. The number of the front end transmitted in binary by 1E ~ central coupler on the channels from ~ rée p0 to p3 is detected by the DNF Frontal number detectaur which sn warns LVS logic, which delivers a permanent state 1 at SV output meaning in the LES and LPV logics that 12 silo SL0 has been validated, that is to say ~
that he can receive or give information. The LPV logic prepares the positioning of channels p0 to p15 for reading the silo by the central.
2 - Reading of the silo by the central - tCLE) -The central coupler presents a request for an impulse readLEC on the LPV channel positioning logic which is positioned in the direction of coupler ~ front to csntral coupler, channels p0 to p15 connected to SL0 silo outputs. If the silo is loaded, one of the rockers on the BCE block change of state of the silo previously gave the indication CLE, reading of the silo pending or in progress by the central, said indication, materialized ~ 735 ~ 6 by a logic level 1 on channel p8, stant transmitted to the central coupler by the multiplexer MSC during reception of the VAL pulse. The logic LES presents 18 level 1 of CLE on the indication wire AD0, address zero, to reset to ~ u RAD RAD register and allow the reading of the first word of the silo's message on channels pO to p15. The coupler central is warned that a word is presented to it in reading by level 1 of CLE switch on the voice p ~ through the MSC multiplexer. Orders and indications LEC, VAE, SV, STR and CLE present at the same time on the advance logic of LAA addresses allow said logic to issue a pulse in the RAD register which designates the next memory line of the silo on which the second word of the message will be read.
After reading the last word in the silo, the central coupler delivers the CFL indication to the front coupler, end of reading by the central, by presenting a logic level 1 on channel p6. On receipt by CFL on BCE toggle block changes from CLE indication to SIL indication, silo free, ie empty of information.

3 - Writing of the silo by the central - tCEC) -The central coupler Qst warned of the free state of the sllo by deleting the indication CLE, therefore by deleting logic level 1 on vo ~ e p8, Said central coupler makes a request for orcupation of silo in writing and, for this purpose, transmits the COC command, new level 1 on channel P4J to the LES silo state logic. The BC ~ rocker block passes from indication SIL to indication CEC, ~ silo occupied in writing by the central). This CEC indication is given, on the one hand, to the central coupler, by a logic level 1 presented on channel p9 and transmitted by the medium of the MSC multiplexer unlocked by the SV control, on the other hand, to the front mini-processor, by a logic level 1 presented and transmitted on channel d10 by the MSF multiplexer. As before the LES logic commands the reset of the RAD address register of the memory lines of the silo by switching this time state 1 of the CEC indication on the wire 54 ~
ADO, this in order to allow the writing of the first word of the message on the ; first line memory of the silo. The binary information presented in parallel on the channels pO to p15 and on the inputs A of the MES multiplsxer, are transmitted to the silo by said multiplex on unlocked by CEC, the screen A word is stored in the silo by a command from the LOE writing logics activated by the conjugate states of the wire ribbon ESC writing of the silo by the central), said states being: no reading LEC, non validatiDn VAL, silo validated SV, CEC rentral writing and STR impul-Control command, Among the AAC wire layer, advancing addressing by the central, only the VAL, SV, CEC and STR states are effective on the logic LAA for the advance command of the RAD address register during the phase writing. After entering the last word of the message in the silo, the central coupler sends the CFE signaling, end of writing by the central, state logic of the LES silo, said signaling being materialized by a logical level 1 presented on channel p5. Upon receipt of CFE, the BCE toggle block changed from CEC indication to FLE indication, reading of the silo waiting or in progress by the front end. LES logic delivers a AOO command allowing the reset of the address register and the designation the address of the first word in the silo.

4 ~ Leoture of the sila by the frontal ~ tFLE) -The FLE indication requests the LI interrupt logic by the link d14, said logic generating comms described above the interruption of the front end for all work other than reading the front coupler silo ~
The FLE indication is transmitted to the front end via channel d14 and the multiplexer MSF on reception by said multiplexer of an SR read command state transmitted by the front end which asks to know the state of the silo. The front, knowing that it must read, presents a DR command for reading data on 1B MSF multiplexer which transposes on dO channels at d15 the data of the first word delivered at the output of the silo. CBS data designate the type of message, the number of the receiving front end and the number of words contained in the message. After reading a word of the message, the 1 ~ 1i73S ~ 6 front ePPsctus a request for readers of the following rnot by presenting a ; impulse command nR on the address advance logic LM. Said command associated with FLE and CV states tcoupl ~ ur validated) presented on the AAF wires, address advance by front end, allows LAA logic to issue an impulse on the RAD register which designates the address of the next memory line whose information is presented at the output of the silo.
The front end recipient knowing the number of words in the message by reading the first word, after reading the last word, a ; 10 logic level 1 on channel d121, thus giving the indication FFL, end of lscture by the front end, to the state logic of the LES silo which, in response, changes from FLE indication to SIL indication, free silo, signifies audit frontal by 1B blnc of rockers BCE which delivers a logical level 1 on the lane dO8, The address registers are reset to zero by the logic.
B w TRANSMISSION OF MESSAGE FROM A FRONTAL TO THE CENTRAL
1 - Writing the silo from the front - tFEC) -The front end can put 4 commands to the LES logic of the coupler silo.
To execute a command the front end must execute an instruction of his program. This instruction must specify which coupler is used the command to be executed and must also transfer this command. This is pass in two t ~ mps:
a - first the front positions on the lines d8-d15 of bmf-Z the profile binaira corresponding to the silo coupler number, then activates wire f6 received by LVC logic, which at this time compares the received bit profile and the code of the coupler c3number on the circuit. If there is equivalence, the logic LVC returns SYN on wire fS and HW on wire f7. The coupler is now ready to receive the order.
- b - the front end now positions on lines d8-d15 of bmf-Z
bit profile corresponding to the command to be performed, either here, for a writing by the front end, FEC, bit 10, received by LES on channel d101, which ~ L ~ 735 ~ 6 constitutes the request for occupancy in writing by the front-end, FOC. The ; front then activates the CMD line, connected to f1, which controls the BCE block.
If the BCE block was in the SIL state, it then goes into the state FEC, writing from the front. otherwise it does not change state. Indeed during of the FOC commands, the central unit may be performing a reading or writing this silo: the front end must then, after having issued a FOC command read the state of the rocker block ~ CE to know if it is passed in the state FEC, It will have to read the state of the silo.
To read the state of the silo, the front end must execute an instruction tion of its program. This instruction must specify to which coupler this read status request is addressed and must also read this status.
This SB takes place in two stages:
a - the front end positions the binary profile on 185 lines d8 ~ d15 da bmf-Z
corresponding to the coupler number of the sllo, then activates the wire f6 received by LVC logic, which at this moment has been reduced, by the number decoder DNC coupler which compares the binary profile collected and the code of the number of the couplaur c3blé on the circuit, in order to inform the said logic of a team number valenca. If there is equivalence, the LVC logic returns SYN on 1B
wire f5 at ~ l on wire f7. The coupler is now ready to receive the request to read status.
b - 18 front then activates the SR signal on wire f10, this signal received by MSF positions this multiplexer on its input A which therefore puts on the lines d8-d15 of the bmf-Z bus the states provided by ECE either, FLE, SIL, CLE, INI, CEC, FEC, and sends SYN to the front end to indicate that the states are ready to be read. The front end can therefore read the FEC state on channel d12 and if this state is equal 3 1 start writing the message in the silo.
To write a word of the message in the silo the front end must execute an instruction of its program ~ This instruction specifies to which coupler addresses this writing, then transfers the data to write to the coupler designated.
The selection of the coupler is done as described more ~ aut ~ a).
~ i ~ i73 ~ i4 ~
To transfer a character, the front end presents the binary profile of the word to be written on channel dO-d15 then activates the DA signal. LnE logic of writing receives by the layer of wire ESF the signal DA which conjugated with FEC
and CV generates a write signal in the silo, EC, and the recognition signal SYN1 birth to LVC logic which in turn will transmit the SYN signal on line f5 towards the front.
The DA signal is also received by the address advance logic.
LAA on the MF wire layer and generates a counting pulse towards the RAD address register of the silo.
The front end psut then on reception of the signal SY ~ I tf5 ~ transfer the next word, and so on until the last word of the message, After that the last word has been transferred the front end must send an order to coupler to warn him that the writing is finished.
The front end will then have to execute an instruction in its program which similar to the sending in the order ~ FOC) will send this time the Cnmmande FFE, ~ in writing from the front. This command will pass the ECE toggle block from the FEC state to the CLE silo state in llre via the central, 2 - Reading of the silo by the central - (CLE) -This operation is identical to that described in chapter A ~ Transmission of a message from the exchange to a front end, paragraph 2 ~
The following remarks are deduced from the operation set out above.
touts:
- each passage of the silo from one state to another means that a new operation (write or read) will start, Any operation will start address zero. Consequently, each change in the effective state of the silo is accompanied by a reset to ~ ero of the address of the silo ~ The mini-processor front has 1 ~ possibility to read again what he wrote in the front silo to write a new message if desired or to finish a message sn course, then ask the central processor to read later. For this purpose the front end issues the FZA level 1 command as many times as it wishes channel d131, which resets the addressing of the memory lines of the silo without ~ 3 ~ 16 modify the state of the rocker block ~ CE. The FZA order must be issued before each reading or each new writing of a message ~
- the only executable orders in a given state of the silo are those that correspond to the normal sequence of a sequence of use of the silo, said sequence, controlled by the state logic of the silo, being itself function of a logical succession of orders entering into the state logic of the silo and indications of states coming out of said logic ~ It follows that one of the interlocutors ~ central or frontal) cannot disturb the other except by sending, following a normal procedure, an erroneous message, none control is not done at the silo level on the content of messages.
- if one of the interlocutors ~ frontal or central) issues an aberrant order or does not issue the order or indication to ensure the normal sequence of change of state of the silo there may be blockage. The other contact is warned of the disturbance by the fact that 19 silo remains in its current state.
Example: 1E central requests occupation ~ n writing of the silo, by transmission of the COC order, and obtains it. The silo is in the CEC state, writing the silo by the central, If the central fails to send the indication CFE, end writing, the silo is blocked in the CEC state without the front end nothing and without being informed otherwise than by knowledge 2n prolongs this state ~
- in the case where several orders are issued simultaneously by the central and by the front end, the highest priority acceptable orders are executed.
Example 1: the front end transmits simultaneously - FFL - ~ in reading ~ FOC - write occupancy request The state loqique, after a transitory pass by the SIL state, free silo, will be placed in the FEC state, writing from the front-end.
Example 2: The front end issues the same orders as in the previous example but, at the same time, the central office issues the COC order, occupancy request in writing. State logic, after a transient transition through the silo state free will be placed in the CEC state, writing by the central. The FOC order, less priority than COC, has not been executed.
3 ~
In figure 3 the central coupler of CCD dialogue and the coupler dialogue front associates CFD1 - making the object of the invention cont-felt in strong lines, CCD being integrated into the central processor PC and CFD
being integrated into the mini ~ MPF front processor. The CCD has three logics coupling LC1, LC2, LC3 and a central microprocessor MPC, said logic being interconnected and connected to the central MPC microprocessor.
The logic LC1 is connected to the central memory MC, or mass memory, by through a tMAC memory access controller) and a bus direct access tbad ~. The central processor MAC is also connected to the local memory or bank B0 of said central processor. The main memory ~ - w carries the banks B1 to E3 constituting a so-called extended memory ME to possibility of extension ~ The volume of this bank Fouvant reaching 25 KD. the maximum volume of banks B0 to B3 of the central processing unit UC is 1D24 KB.
At the CPU central unit messages from ~ rontaux mini-processors are introduced into banks by means of a list tuurnant input information and messages to transmit to front-facing mlni-prucessors are withdrawn from banks ; a rotating list of output information, said rotating lists being located in any bank. The rotating list of information input input receives, sent by the micro-process on the address called ~ dep ~ t designated by the first of the words constituting the reception of a message, ; only the information of said message is then stored in the bank.
The characteristics of the incoming msssags, storage indication, type of message, number of the sending front end and number of words constituting message information; are taken into account by the micro ~ processor of the CCD which is responsible for managing the rotating lists, updated day, and bank storage of the exact number of mDts of information constituting the incoming message ~ This storage is carried out in a bank of the central memory MC through, on the one hand, the logic of coupling LC1 and LC3 controlled by the micro-prucessor MPC, and on the other hand, ~ 7 ~
MAC st of the direct access bus ba ~.
The MPC microprocessor collects from the rotating list of exit information, the first address designated by the pointer to reading of said list. This address2, transmitted by LC1 logic and the bus bad, in memory allows to locate the corresponding stored message and take it from said memory in order to transmit it to the receiving front end via the microprocessor, via LC1 and LC3 logic.
The updating of the revolving lists is carried out on other ~ anointings, by 1B micro-processor, this one recsvant or transmsttant 1BS
ordrss or states the logic of the csntral processor PC via in LC2 logic and a bmx multiplex bus. The logic of the processor ; csntral is also in connection with the MAC bank access controller memories.
The LC3 coupling logic is rellse to the -Frontal coupler CFD1 dialogue via the bus ~ siLD bsa1.
The configuration of the logic diagram of the central dialogue coupler tCC0) is given by ~ igures 4, 5 and 6 which respectively represent LC1 coupling logic, LC2 st 1B coupling logic micro-process central MPC, the LC3 coupling logic.
The LC1 coupling logic detailed in Figure 4 has access to the banks memories via the bad direct access bus. This goal includes, on the one hand, dss addresses or data links tH ~. on the other hand, command and signaling connections (I, J, Ki L ~ constituting a channel semaphore, connected to the tMAC ~ memory access control. H bonds have 20 ~ they including 16, tDMA O to 15), connected to a transceiver ER1 and 4, tDMX 12 to 15 ~, connected to an ER2 transceiver. Connections I st J, each have 4 wires and are respectively connected to ER3, ER4 transceivers. The K and L bonds have respectively 4 and 3 ~ they are connected to the CAD logic for direct bus control.
Incoming data from a memory bank is received On 1 ~ H bus and trancmisss by ER1 in a data reading register ~ 19 -9L ~ 73 ~ 6 LDM memory, said register accessing the microprocessor MPC by the links sounds V orisntées in the direction LC1 towards MPC. U links from MPC
are distributed over three registers, namely the RDE register. register of data to write, RAB, low address registers, and RAH, address register high. This distribution is as follows: 16 wires, (rO to 15), on RDE, 15 sons, ~ rO to 14), on RAB and 6 sons, tr10 to 15), on RAH.
The RDE register includes 15 output wires, ~ DB D to DB 15) connected to inputs A of MX1 multiplexers, said wires serving as support to the data of the message to be written in the addressed memory bank. The RAB registrs have 15 output wires, (MA O to MA 15 ~ connected to inputs B
of a multiplexer MX1 and to the logic of coupling LC2 by the Q links.
address register high RAH comoorte 6 output wires distributed on a MX2 multiplexer, on a LEL write and read logic and on a LOB bank occupation logic; this distribution is made as follows: 4 high address fil5, tDMX 12 to DMX 15), connected to inputs B of a multi-plexaur MX2, 2 code wires of bank number tPAG O and PAG 1 ~, connected on the one hand, to the LEL write and read loglque, on the other hand. to the logic of occupation of LOB bank.
Lss four inputs A of the MX2 multiplexer are connected to the ground ~ The MX1 multiplexer co ~ carries a 16-wire output connected to the inputs of the transmitter ~ receiver ER1, said wires making it possible to transmit ~ by the H connections of the bad bus, the low address, i.e. the address of a line of the memory then the data of the message to register in memory bank, children DMA O to DMA 15. The MX2 multiplexer has a 4-wire output connected to the inputs of the transmitter-receiver on ER2, said wires making it possible to transmit by the H links of said bus, the high address designating the memory bank and a memory block in said bank, wires DMX 12 to DMX 15. The wires DMX 14 and ; DMX 15 H connections are extended, through ER2 on d8 inputs LEL logic, the ~ they DMX 12 and DMX 13 being extended on the inputs of a RDF fault registers whose output wires d5 to d7 and DAMD are connected to the LC2 coupling logic via the P links.

~ 735 ~ 6 The bldirectional J connections connected to the transmitter ~ ur ~ r ~ receiver ER4 are extended in unidirectional links in both directions between the ER4 transceiver and the LOB bank occupation logic CL link and BO link connect LOC logic to control logic CAD of the bad direct access bus. CAD logic is linked to a generator GSn memory signals via SEL, SOT and LOAD links. The SEL link is also presented on 185 E ~, ER2 and ER3 ~ CAD transceivers connected to ER3 by a DMA 16 wire and to ER4 by an SBZ wire, An EOT wire connects the GSM generator with LEL and CAD logic. LEL logic is linked to registrs RDF by a CANS Pil derived from the LDM register, and by a WT wire, the latter being derived on input B of multiplexer MX1 and on one input of generator GSM. Said generator is in connection with the multiplexers MX1 and MX2 by an ADD wire.
The ER3 transceiver is connected to the LEL logic by an ANS wire, The micro ~ MPC processor reprasented fi ~ ure 5 is connected to gold ~ donkeys of Figure 4 ~ listed below:
- RDF and CAD, via the m GO thread, - RAC, by the wires m LAR and m IAR, ~ RAH, by the wire m MElK
- RDE3 by wire m LDA
- LEL, by wire m LDA
The logic of coupla ~ e LC2 represented fi ~ ure 6 is connected ~ to the LC1 coupling logic via P and Q links and has coupling logic LC3 by the links G, The wires MA O to MA 5 of the links Q are connected to inputs 1 of a multiplexer MX3 and the wires MA 6 to MA 14 of said links are rell at the entr ~ es 3 of a multiplex on MX4. The six sons connected to the input O of the MX3 multiplexer are connected to ground.
The wires d5 to d9 of the links P are r ~ linked to the inputs 2 of the multiplexer MX4 as well as the inputs d10 to 14 of the G links, A device of "Chlen de Garde Timer" TCG receives the OAMB wire coming from said ~ 73 ~ 416 liaLsons P as well as two d5 and d6 leads d and a BS wire from the LSO silo state logic located in the neck log LC3 plags. The TCG device is connected to the LCI logic by a link SITO ~ The wire d5 is derived from an input O of the mu1tiplexer MX3.
The central processor multiplex bus ~ ur bmx includes:
a ~ 16 wires of data DO to D15 distributed as follows:
; - DO to DS wires connected to the MX3 multiplexer - wires D 6 to D 15 connected to the MX4 multiplier - wires D 6 to D 15 connected to a number decoding logic coupler ; - wires D 4 to D 9 connected to a state logic of the LEF waiting wires ~ - DD to D 3 wires connected to a central LCI intrusion logic ; b - instruction or command wires such as:
- ADRS, HW, DR, SR, DA, SYN linked to a decodag log of the LDC coupler number - ATN, RACK, TACK linked to LCI logic ~ a SCLR wire to power up the RDF fault register FIG. 4, the PMC microprocessor in FIG. 5, and the LCI logic, The LDC logic is connected to the MX4 multiplexer by 9 wires links allowing the transfer of the coded number of the coupler, and by the SYN1 and SYN2 son. It is connected to the MX3 multiplexer by the SYN3 wire.
The son d 08 and d 09 of the lo ~ ique LDI are connected to the son d8 and d9 of inputs 2 of the MX4 multiplexer. Said LDI logic is also connected, on the one hand, to the micro ~ MPC processor by the INI, DEF, m DME and m DMS, on the other hand, to the logic LSO by the wire TOB, BSB and RESET, said wire Reset being derived on RDF, figure 4.
The wires d12 to d15 connect the LEF logic to the inputs 1 of the multi-MX4 plexer. LDC logic and LCI logic are linked together by a RIT wire and a STCO wire, said STCO wire also being derived on the LEF st LDI logic.

~ 7354 & ~
The logic L ~ F is connected to the microprocessor MPC by the wires BSD, FOD and F1DJ as well as by the wires m MBS, m FOU and m F1U.
TGC logic is also linked to the central microprocess MPC by the wires m DME and m DMS. LCI logic is connected to MPC by wire m MED.
Figure 5 includes the MPC microprocessor and the logic of LC3 coupling.
The data and address wires r O to r 15 coming out of the micro ~
MPC processor are connected to CSA and CSB coupling devices, said 1D devices being connected respectively to the bus-silo bs1-a and bs1-b by the REP son, pO to p15, VAL, LEC and STR.
~ four sons r11 to r15 are derived on an RFA register of num ~ ro front end called whose outlets, wires d10 3 d 14, being connected on the one hand, has the logic of LC2 coupling, G links, and, on the other hand, to inputs A
an MX5 multiplexer whose inputs B are connected to wires r12 to r15. In output of multiplexer MX5, wires r11 to r15 are connected to CSA couplings and CSB. The RFA registrs is connected to the two couplings by a SEL wire derived in a SELA fll connected to the CSA coupling and a 1! SELB it connected to the CSB coupling via an inverter.
LBS data from a front end received by a CSA or CS9 coupler are recorded in an LDF register for reading front-end data, said register being connected to the MPC microprocessor and to the CSA and CSB couplers by the read data transmitting wires s0 to s15.
CSA and CSB couplings have a REPA wire and REPB linked in common to the LDF register and to a silo status logics LSO, said logic being linked to LDI logic, FIG. 6, by links BSB, TOBJ and RAZ. The SCLR wire arriving on LSO comes from the multiplexer bus bmx of figure 6.
A STR link connects in parallel the ~ CSA and CSB couplings to the LSO logic.

~ 1 ~ 735 ~
The microprocessor is directly linked to the couplings C5A and CSB by the m VAL and m LEC wires, the m VAL wire also being connected to the MX5 multiplexer, The microprocessor is also connected to the RFA regulation by the wire FM and to the logic LSO by the Wire mBS.
The central dialogue coupler, Figures 4, 5 and 6, - Works from the following way:
I - TRANSFER OF INFORMATION BETWEEN THE CCD AND A MEMORY BAN ~ EU -LC1 coupling logic, Figure 4) A - Case of a writing -The format of the address presented to the memory bank by the CCD
consists of the following lesson:
high address low address N ~ of N ~ of N ~ of memory box memory bank N 0 ~ ~ Ul ~ ': t ~ r ~ ~ ~ O ~ ~
: 'XXXX
bit 218 217 216 215 ~ 14 21 2 ~ W
This address is that of a memory box in which will be entered a message received from the CFD dialogue front coupler. In writing W
= O and sn reading W = 1 ~
The message having been deposited in the microprocessor MP ~ by the logic LC3 -Figure 5, the microprocessor cnarge the bits of the lines of low weight DMAO to DMA14 in the low address register RAa in him applying the micro command L LAR, then load the bits of the weight lines strong, DMX 12 to DMX 15, in the RAH high address register by applying it the micro-command m MDK, figure 4 ~ RAH also records by Fils r 10 and r 11 the two weights of the code of the bank number m ~ moire where is located this adress ~.
After loading the address and bank code, the micro-processor loads the data to be written in the RDE register by applying it the m LDA micro-control. Said micro-command is also applied to the ~ 73 ~ 46 LEI write and read logic which generates bit 1 ~ = O of the address on the WT wire. This signal, applied to input C of MX1 means that the coupler on central will operate a data transfer to write to memory banks. Lsdit signal W = O also has the RDF fault register of said transfer as well as the generator of GSM memory signals which deliver a LOADO signal ds prsssntation of addresses or ds given on the CAD logic and on the transmitter-ER3y concepts The transmission is now ready to go to the bank recipient memories as soon as they are ready. LB micro-processor a micro-controller m GO which initializes the register as soon as RDF is needed for 1B
future memory access J lsdii register being supplied by a SCLR command from the central processor by 1B multiplsx bus on bmx, figure 6.
The m GO micro-commands are stored in the control unit dirsct CAD access.
By 1BS wires MX ~ Z and the ER4 transceiver, the used logic pation of banks LOB constantly reads the state of occupancy in four banks, this one presenting lsur num ~ ro in turn through the intermsdlaire from the MAC as soon as it's available.
LOB logic compares the coded bank number from the RAH registers with the number of the available bank. If there is an analogy, the LOB logic signals this to CAD logic by 1B wire BL, free banks, o ~ by 1B fii BO, bank 0, if it is the local memory of the central processor.
The CAD logic then transmits to the MAC some occupants of said occupations bank by sending a potentisl on 1B XREQ wire.
In 1BS sixty nanoseconds that follow, the MAC responds sn using a 3D nanosecond pulse on 1B wire THAT L links, said impulse signifying that the XREQ request has been taken into account. This impulse are used to position a rocker in the CAD logic and possibly in other devices such as bands magnetic, discs, stc ... having direct access to memory banks. LB

~ 735 ~ i central coupler having made a requ8te, its litigation rocker is set to 1 ~
60 nanoseconds later the MAC sends a 120 nanosecond TPC pulse which is received by the RCP wire of the L links, in the CAD logic ~ The rocker of litigation being at 1, the CAD logic does not return the TPC impulse on the TPC wire from K links to other direct memory access devices, the central dialogue coupler being considered a priority because that the dispute head is not set to state 0. As soon as the bus bad direct access to memory banks is free, the MAC sends an impulse of 60 nanosacondes which is received in CAD by the SOT wire. This signal indicates ; 10 that a transfer operation can be carried out by the CCD. Said signal arms a selection flip-flop in the CAD logic which, by the SOT wires and SEL starts the GSM signal generator and 9 by the SBZ wire, unlocks ER4 transceiver which transmits to the MAC and all other devices risk with direct memory access, bank occupation information taken.
The CAD logic presents a state O on the DMA 16 wire of the transmitter-ER3 receiver to notify the bank that a write will be made.
The GSM generator activates the LOAD and ADD wires, the impulse signal LOAD transmitted by the ER3 transceiver notifying the bank of the ~ 2D presence of an address on the H link. Simultaneously the ADD signal ; unlocks inputs B of multiplexers MX1 and MX2 in order to transmit bank number and high and low addresses. The address is transmitted on the H connections of the bad bus, to the addressing of the memory, by the transmitters-ER1 and ER2 receptors. The GSM generator generates a second pulse signal on 1B wire LOADD to ER3 which warns the bank of the imminent reception Datas. Simultaneously G ~ M suppresses the ADD signal, which causes the bloca ~ e of inputs B and unlocking of inputs A of the multiplexers MX1 and MX2. The data of the RDE register are then transmitted to the memory via MX1 and ER1 and MX2 and ER2, Note: the inputs A of MX2 being 3 mass, this only generates bits O on the ~ they DMX 12 to 15.

~ 73,546 Sixty dlx nanoseconds after the data transfer, the GSM generator emits a new pulse of 70 nanoseconds on the EOT wire to notify the MAC of the end of the transfer and reset the LEL logic and CAD, CAD logic removes the potential of SEL and SBZ wires, thus ER1 to ER4 transceivers to position themselves as receivers.
B - Case of a reading In the case of a reading, the data is provided by the bank memory on the H connections of the bad bus. It must be registered in the LDM memory data read register, the RDE write register not being solicited.
The loading of memory addresses in the RAB and RAH registers is carried out as in the case of a writing as well as the emission of address which precedes the reception of the data in the LCM register, the addresses high and oasse being loaded under the controlB of the commands m M ~ K then m ~ AR of the MPC microprocessor. LEL writing logic not receiving write command m LDA of the micro ~ processor, said logic operates request to read to memory. this read request is dlf ~ erenciant of a writing request by the fact that the LEL logic generates the signal W = 1 on the multiplexer MX1 and that the signal EOT, end of transmission-; 20 sion ~ sst transmitted immediately after the LOAD signal. which meant to the remembers the presence of the address on link H, the CAD logic suppresses then the command SEL on the ~ mettsurs-receivers which passes ~ t in pDsition of reception ~
When LOAD is received, the memory bank returns the ANS signal which is rs ~ u in the LEL logic and indicates that said bank has the give on the H connections. This information includes the data properly said having been presented on lss son DMA O to DMA 15 of the H bonds, any memory and parity dice designated respectively by the DMX 12 and DMX 13 wires and the bank code number presented on the wires DMX 14 and DMX 15. This number is compared with that contained in LEL and from RAH tPAG - 01 ~, If the comparison is correct, the LEL logic ~ 73 ~
delivers the CANS signal allowing transfer of information from the register LDM in the micro-processor MPC via the V links. The CANS signal is ; also applied to the RDF fault register to which any reports have been made faults by lss wires DMX 12 and DMX 13. The indications of faults are transferred to LC ~ logic by P links.
II - TRAN ~ FERT OF STATES AND ORDERS BETWEEN THE CCD AND THE CENTRAL PROCESSOR
LCZ coupling logic, figures 6, is connected to the processor central by the bmx multiplsxer bus. Said bus transmits vsrs LC2 commands from the central processor while LC2 transmits information other than data as well as states resulting from commands received, 12 said states and commands concerning the situations of the rotating lists memory, i.e. the state of libsrté or ds non liberty dss files of incoming and outgoing msssagss.
After transferring a message to a memory bank via the mediates the LC1 logic, the MPC microprocessor gives the order 3 the logic LCI interruptions centrals of interrcmprs 1B process on central, said ordrs stant signified on wire MEO. LCI logic requests the interruption to central processor sn having a signal on the ATN wire, said processor acknowledging receipt of said signal on 1B RACK wire to LCI logic.
b acknowledgment of receipt taking the LCI logic, it becomes a priority and, therefore, does not transmit any signal on the ~ il TACK ~ When the RACK signal is received, the LCI logic generates a signal RIT on the LDC logic for decoding the number of the coupler on the multiplier bus bmx, lsdit coupler being the assembly of figure 6 representing the logic LC2 coupling.
LCI logic can receive commands from the central processor masking or unmasking of the interruption presented on the wires DO to D3. LOC logic selected, by the SYN1 and SYNZ wires, the position input 0 of the multiplex on NX4 which transmits the number w of the coupler on the central processor by wires D6 to D15. The central processor may now taking identification of the coupler which had requested the interruption and treating - ~ 8 -~ 35 ~ 6 this interruption.
The central processor and the central microprocessor work both on incoming and outgoing mPssage queues. To avoid conflicts in the handling of pointers in these queues, when the central processzur handles a list, it alerts the micro-processor and vice versa the central processor is warned of a manipulation list made by 18 microprocessor by the logic ~ anal LC1 and the bad bus. The LEF queue status logic is used for this purpose9 of intermediary between the central processor PC and the central microprocessor MPC. The exchange of information between PC, LEF and MPC is as follows:
- reception in LEF of a status bit 1 presented by PC on wire D4:
means that the central processor frees the queue of incoming messages; the LEF logic warns the microprocessor by the FODJ wire queue O
available, - reception in LEF of a bit 1 presented by PC on wire D5: means that the central processor requests the occupation in the fila of incoming messages;
if the microprocessor does not handle said -file, the LEF logic presents a state 1 on the ~ it d12 da the input position 1 of the multiplexer MX4, meaning the indication "queue of incoming messages available.
- reception in LEF of a bit 1 presented by PC on wire D6: means that the central processor frees the queue of outgoing messages using LEF logic warns the microprocessor by the F1D wire, f ~ the waiting 1 available, - reception in LEF of a bit 1 presented by PC on wire D7: means that the process on central requests the occupation of the queue of outgoing messages if the microprocessor does not handle said queue, the LEF logic presents a state 1 on the wire d14 of the input position 1 of the multiplexer MX4, meaning the indication "queue of outgoing messages available.
The microprocessor uses LEF logic through the FOU wire or m F1U depending on whether it requests occupancy of the incoming message queue or that of outgoing messages, the lo ~ ique LEF responding to it with a command On the bare F1D FOD wire indicating the availability of the requested queue.
~ 7354 ~, The central processor has the possibility when it decides that a front mini-processor has failed, disconnect the bus-silo from this calculator and connect the ~ us-silo of the mini-processor of sscours. A cst eff9t 18 central procssseur presents a state 1 on wire D9 of the logic LEF which warns the micro-procssseur MPC by the wire BS ~ not to trans-put messages to the front end up out of order. Through the m MBS wire, the micro-processsur interrogates the LEF logioue on the bus disconnection state with said frontal.
After troubleshooting the front end, PC has a state 1 on wire D8, thus indicating the end of the emergency switching.
When the central processor presents a command on LEF, for example a wire D 4 to D g, it presents by the wires D 6 to D 15 the number of the coupler on the LDC decoding logic of said number and generates the ADRS signal. To the reception of this signal, the LDC logic compares the number of the coupler received with the interns c3blé number. If there is identity, it sends a SYN signal to the central processor. Upon receipt of SYN ~ the central processor sends SR
which, combined with the coupler number, makes it possible to select the position input 1 of MX4 by wires SYN1 and SYN2 in order to send to the process central location indication of availability of the queue of incoming messages or that of outgoing messages. The LEF lngiqus can also pay for central processor indication of a microprocessor failure, bit 1 on the wire d14, or indicate the connection of the bus-silo, bit 1 on wire d15.
Reading by the central processor of a word address intended to be registered in a memory bank -This address is that of the lower part of the last memory word transferred or being transferred by the LC1 coupling loglqus. She is registered in the low address register RAE of said logic and presented by the wires MA0 to MA14 of the connections ~ on the input position 3 of the MX4 multiplexer, and on the input position 1 of the MX3 multiplexer.
The instruction which identifies the coupler is executed as before.

~ 735 ~
On reception of the SYN signal, 1B central processor sends the DR signal which allows the LDC logic to simultaneously select the input position 1 of the MX3 multiplexer and input position 3 of the multi-MX4 plexer, to transfer the lower part of the address to the processor central.
- Reading by the central processor of the front end number called -Operation is identical to the previous case with the address of the couplsur is received in the LDC logic in association with the SR signal, this ; which allows said logic to select the input position 2 of MX4 and of transmits by the links G of the logic of coupling LC3, figure 5, the front-end number contained in the called front-end number register tRFA) ~
Sending of the commands to the coupler by writing on the central process . a mmot in 16 bits -: LCI interrupt logic receives st executes commands masking or unmasking of the interruption, said commands being shown on DD 3 D3 wires.
The commands received by the LEF software have been listed previously during the exchange of information carried out by said logic between the central processor and the microprocessor c ~ ntral ~
The central processor can send simultaneously to the coupler on sixteen different commands in the form of 1 ~ bit word writers.
In this case the central processor performs as before addressing the coupler and, upon reception of the SYN signal, returns the slgnal DA which is received by the decoding logic of the coupling number on LDC. The LDC logic then passes to the LCI, LEF and LDI logics the STC0 signal which memorizes the reception of the commands in said logics, : - Reading of faults by the central processor ~
The readings procedure is analogous to that seen previously.
Faults allocated to the memory bank have been recorded in the RDF fault register, Figure 4, and are s ~ gnalées to the processor ~ L ~ 735 ~ 6 central in reading position by the following instructions:
- memory fault: bit 1 presented on position O of MX3 by wire d5 P bonds - parity fault: bit 1 presented on position 2 of MX4 by wire d6 - memory failure: bit 1 presented on position 2 of MX4 by wire d7.
Other faults may have been recorded in the frontal called RFA, figure 5, and are then presented by the links G
at the input 2 positions of the multiplex on MX4. They are designated by the following instructions:
~ fault in the procedure for sending a message:
bit 1 on the wire d ~
- fault in the procedure for receiving a message:
bit 1 on Wire d9 - identification number of the faulty front end:
bits on wires d10 to d14 - bus-silo inoperative: bit 1 on wire d15.
- Logic in initialization faults Lt) I -This logic includes a flip-flop upon initialization request which, when the central dialogue coupler is switched on, is automatically ; 20 only positioned at 1. Informed of this state by the INI wire, the micro-program of the microprocessor turns on the state test of this rocker until that the central procssseur gives to O said rocker by presenting a command received on 1B wire D 12. This is the command to start the dialogue.
The central processor can stop the dialogue, in the case of the passage of the bus-silo on mini front-end backup for example, by presenting a command on the wire D 11 which remits the initial request switches state 1.
When 18 central processor MPC, figure 5, is warned of a fault of incoming or outgoing message caté bus-silo, it prevents the LOI logic by the wire m DME or m DMS. LDI logic memorizes the fault and transmits the indication to the central processor by wire d 08 or d 09, ~ 32 -~ 73 ~ i46 as appropriate and blocks the microprocessor by presenting a command on the ~ it DEF.
The central dialogue coupler then waits for three possible commands of the central processor:
a - restart order - a status command 1 received on wire D 10 e- ~ ace the dice ~ aut memorized in the LDI logic which removes 18 blocking of the DEF microprocessor b - resumption of the current sequence - by setting the D 12 wire to 1, i.e.
reception of the bit profile: 1 on D 10, 0 on D 11, 1 on D 12.
c ~ reset - by setting the D 11 wire to 1, i.e. receiving the bit profile 1 on D 10, 1 on D 11 and O on D 12.
- Operation of the TCG timing device - t Watchdog ~ -When the MPC microprocessor requests access to memory for send an outgoing or incoming message there ma: there is a potential on the wire m DMS or m DME until it has obtained satisfaction. If the maximum time provided by the timer the TCG device generates the signal SITO on the central LCI interrupt logic which performs the procedure central processor interruption as seen previously.
. Likewise. the LSO silo state logic, figure 5, m3 contains a potential on TCG's ~ il BS ~ as long as the ~ silo bus remains unavailable.
As before, if the guard period has elapsed, an inter-central processor failure.
Finally the bad direct access bus, Figure 4, ~ e should not be taken beyond a certain time by the central dialogue coupler for the transmission of a message. To this effect, upon the memory response. the register of faults ~ RDF is warned of this response by the CANS signal and activates the ~ il D ~ Ma linked to the TCG timer which, as before, will order the interruption if the time limit has elapsed.
III - SAMPLE OF INFORMATION BETWEEN THE CCD AND THE DUS-SILO bsa or bsb tfigure ~) Communication is established in two stages between the logic of ~ L ~ 73546 couplaee LC3 and 18 front dialogue coupler ~ CFD):
a - addressing of the bus-silo chosen by the central microprocessor MPC then transfer of a command to the front coupler, in its status logic of the LES silo, Figure 2.
b - Data transfer in writing or reading.
Orders or indications that can be transferred to the logics The frontal ones are as follows:
- COC, request writing occupation of the silo; request made by bit transferred by CSA or CSB coupling on wire p4, said bit has been presented by the MPC microprocessor on wire r4 CFE, end of writing by the central coupler ~ OCD ~ I indication given on thread r 5 and p5 - CFL, end of reading by 1B central ~ indication given on wire r 6 and p 6.
When the central microprocessor attempts to occupy pation of the silo of the front coupler of a front mini-processor, said central microprocessor places the called front end number (RFA) by presenting said number on wires r 11 to r 15. The most significant biLt, weight 4, of the address of the front coupler is placed on wire r 15 of the RFA register. The micro-procsssaur MPC generates the signal m FAR which controls the transfer in RFA
Z0 of the wire bit r 15 on the SEL wire and the transfer of the address bits of the wires r 11 to r 14 on input A of the MX5 multiplexer. Weight bit 4 of SEL wire indicates on which half of the 32 front mini-processors, the ; transaction must be completed.
The multiplexer MX5 transmits the bits of weight 2 to 2 of the address of the front coupler, through the selected bus-silo coupler, on the channels p 0 to p 3 of said bus-silo ~ This transmission is controlled by the micro-processor which presents the micro-commands m VAL and m BS respectively on the silo coupler and on the LS0 silo status logic which delivers an impulse signal on the STR wire of the bus-silo via the coupler selected.
The con ~ onction of the VAL and STR signals specifies the transfer of a ~ C ~ 73 ~ 6 command to the front stacker ~ the COC command for example being issued on track p 4 of the bus- ~ silo.
Any sending of a STR signal by the central coupler must be necessarily followed by receipt of an impulse signal of REP responses after a known time delay. If the CSA or CS ~ coupler selected does not not receive the REP signal, the LSO logic delivers on the LOI logic, ~ igure 69 TOB information, silo response p3s, or BSBJ silo not available, according to the logical state of the bit read by the CSA or CSB coupler on channel p 15 of the multiplexer bus.
When the COC signal is received, request to occupy the silo in writing by the central coupler, the LES state logic of the front coupler responds with the indication CEC, silD occupied in writing by the central, in presenting a logical level 1 on the channel p 9.
This CEC indication is received in the LOF register, reading of data from the frontalO then transmitted to the microprocessor MPC by said register unlocked by an order presented on the REPA thread or REPB by the CSA or CSB coupler having received the REP response signal.
On reception of the CEC signal, the micro-prcessor MPC presents a given on its output wires r O to r 15, then activates the wire m BS of the LSO silo state logic which in turn emits a pick-up pulse STR account to the front coupler.
Upon receipt of the REP response signal from the coupler front and acknowledging receipt of the STR signal in said coupler, the data to write to the silo of said front coupler is emitted through the dlsposi-tif of coupling CSA or CSEl of the central couplerJ on the channels p O ~ p 15 of bus-silo.
MPC microprocessor does not know the response signal st renews the command in the write cycle after timeout.
The microprocessor proceeds in analogous fashion for transmission.
successive of each data of the message.

1 ~ 73 ~ i ~ 6 The MPC microprocessor knows it needs to read the silo when it receives a logic level 1 emitted by the state logic of the silo of the front coupler on channel p 8, signal CLE. The microprocessor then issues the micro-commands m LEC and m BS which respectively generate the LEC and STR signals. Upon receipt of the REP response signal, the CSA coupler or CSB unlocks the LDF front-end data read register and the data, received on channels p O to p 15, is introduced into the micro-process sister. The latter, as in the case of a writing, has no knowledge of the response signal and to read each data item renews the command 1 ~ read after delay.
'~.
.
~ 3B -

Claims (23)

The embodiments of the invention about which a exclusive right of property or lien is claimed, are defined as follows: 1. Articulation and management system for central telecommunications comprising, on the one hand, mini-processors front-ends managing each one, in asynchronous mode and autonomously, part of the operations necessary for processing and communications service, and on the other hand, a central processing unit carrying a central processor associated with a central memory, a maintenance processor associated with a maintenance memory, said processors each also working in asynchronous mode and independently, the central processor orchestrating the activity mini-processors and the maintenance processor controlling the normal progress of the tasks of said mini-processors, charac-terrified by the fact that the exchanges of messages between the mini-front processors and the two CPUs are carried out via pairs of couplers (CFD1-CCD1, CFD2-CCD2) each connected to the ends of two buses-silo (bs1, bs2) each coupler of the same pair comprising a central dialogue coupler (CCD) integrated into a processor the central unit and a built-in front dialogue module (CFD) a front mini-processor, a bus-silo being split in two identical bus lines from the output of the central dialogue coupler, each bus line being made up of a pair of traveling wires from cabinet to cabinet and to which are connected as many front-end derivations, information exchange between a central processor and front end mini-processors being transmitted in the form of messages of reciprocal variable lengths-between the central dialogue coupler (CCD) and the coupler dialogue front (CFD) on said bus-silo so that the frontal cry of dialogue carries out said exchanges by mode programmed verbatim at the front mini-processors, and that the central dialogue coupler (CCD) performs said exchanges information by direct memory access at processor level central therefore without disturbing the progress of its program, the coupler to coupler exchanges being supervised by the coupler central dialogue independently and asynchronously with respect to the central processor. 2. System of articulation and management according to the resale dication 1, by which the central dialogue coupler performs the exchange of information by direct access to the central memory (MC) at the central processor, said central memory comprising a local memory (ML) (BO bank) associated with an extended memory (ME) (banks B1, B2, B3) via an access controller (MAC) to two rotating lists of information located in any bank the rotating information list of entries receiving the deposit address designated by the first word of a message received from a front end, the rotating list of exit information providing the address where the message to be transmitted to a memory is stored in memory front, characterized in that the central coupler has a microprocessor in relation with three coupling logics, a first coupling logic (LC1) connected to the extended banks and to said controller access (MAC) via a direct access bus (bad), one second coupling logic (LC2) linked to the central processor (PC) and the controller access (MAC) via a multiplexer bus (bmx), a third coupling logic (LC3) connected to the front dialogue coupler (CFD) of the front mini-processor via a bus-silo (bsa), the message coming from a front mini-processor being routed in the micro-process via said third coupling logic (LC3), said microprocessor request said second coupling logic (LC2) which alerts the processor central to handling a list from the microprocessor, the message retrieved from a memory bank by the central processor being routed in the microprocessor via said first coupling logic (LC1) then transmitted to the front end via said third coupling logic (LC3). 3 / articulation and management system according to claim 1, character-laughed at by the fact that said front coupler includes a silo (SLO) whose outputs are connected on the central dialogue coupler (CCD) side to a logic of positioning channels (LPV), bidirectional fifteen in number (pO
at p15) from the bus-silo and front side to an output multiplexer (MSF), the inputs of said silo being connected by input positions (A) of a multi-input plexer (MES) to said channel positioning logic (LPV) and by input positions (B) of said input multiplexer (MES) to channels (dO to d15) bidirectional of a front-end multiplexer bus (bmf), the silo states being communicated to the central coupler or to the front end by a silo state logic (LES) according to the orders received by it and from the central processor or the front mini-processor.
4 / articulation and management system according to claim 3, charac-terrified by the fact that the silo state logic (LES) is linked go. to tracks (p 4, p 5 and p 6) of the silo bus via the channel positioning logic (LPV), on the other hand, to channels (p 8, p 9) of said bus-silo via an output multiplexer to central (MSC) said silo state logic (LES) also being linked to outgoing channels (d8, d9, d10, d12, d14) of the multiplexer bus (bmf) of the front mini-processor via an output multiplexer to front (MSF), the silo having its outputs in connection with said multiplexer and with the channel positioning logic (LPV) which includes a block of flip-flops (? CE) whose inputs receive orders or indications from the central coupler by a logic level presented on incoming channels (p 4, p 5, p 6) and whose outputs deliver on outgoing channels (d8, d9, d10, d12, d14) a logic level giving indications on the free state of the silo or on its reading or writing socket by the central coupler of dialogue or by the mini-processor. so that, the silo having been loaded by a message sent by the front mini-processor, the state logic of the silo informs the central coupler by a first signal (CLE) applied to a outgoing channel (p 8) that it can read the silo, said central indicating, after reading the message contained in the silo. the end of reading by a second singal (CFL) applies the logic on an incoming channel (p 6) silo states (LES) from the state indicated by said first signal (CLE) in the free silo state (SIL), said state being signified centrally by the deletion of said first signal (CLE) and at the front end by presentation of the free silo signal (SIL) on an outgoing channel (dB), the central coupler requesting occupation of the writing silo by presenting a third signal (COC) on an incoming channel (p 4), the state logic of the silo (LES) passing a during the free silo state (SIL) to the occupied silo state in writing by the central, said state being confirmed to the central on a channel outbound (p 9) and signaled to the front end on an outbound lane (d10) central unit presenting after writing a fine writing signal by the central unit (CFE) said signal (CFE) received on an incoming channel (p 5) passing the silo state logic (LES) of the silo state occupied in writing by the central in the state of reading the silo by the frontal signified by said frontal by an outgoing channel (d 14). 5 / articulation and management system according to claim 4, character-laughed at the fact that the front dialogue coupler has logic interrupt (LI) to interrupt the front mini-processor for any work of it other than reading the silo, said logic being connected to an incoming channel (p 6) transmitting the second signal (CFL) and at the outputs of the silo state logic (LES) emitters of the liter silo (SIL) and (FLE) signals (reading of the silo by the front end) so that an interruption of the front end is generated by the logic either after the central station has read the silo, or before reading said silo by the front end on the other hand. incoming paths (d8, d9) also being connected to the interrupt logic by wires (d 081, d 091) in order to allow the front end to possibly carry out a masking, then unmasking the interruption in progress. 6 / articulation and management system according to claim 5, character-laughed at by the fact that the outputs of the silo state logic by which The indications of states are delivered by the signals reading the silo by the front end (FLE) free silo (SIL), first signal (CLE), busy writing silo by the central (CEC) skips the silo by the front (FEC), are connected to input positions (A) of the output multiplexer (MSF) of the incoming channels (d 8 to d 15) being connected to a coupler number decoder (CNC) one output (CD) of said decoder being connected to a validation logic of the coupler (LVC), said logic being connected to the multiplexer (MSF) by a wire (SYN 4) and to the bus (bmf) of the front mini-processor by an input wire (ADRS) and by output wires (SYN and HW) an input wire (SR) connecting said multiplexer to said bus so that a reading of the silo by the mini front processor is preceded by an identification of the front coupler by said mini-processor, the latter having the corresponding binary profile corresponding to the number, of the front coupler on the said incoming channels (d8 to d15) then activating the input wire (ADRS) of said logic for validating the coupler (LVC) which is notified by the decoder (DNC) (CD wire) that there is equivalence between the coupler number bit profile received in the decoder and bit profile of said wired number on internal circuits said decoder, the coupler validation logic (LVC) warning the front end and the equivalence silo state logic (LES) by activating wires (SYN) and (HW-CV) and the front panel activating the input wire (SR) of the multi-output plexer (MSF) which unlocks its input positions (A) by which the current state of the silo is transmitted to the front mini-processor. 7 / Articulation and management system according to claim 6, in which on the one hand, the validation of the silo by the central is indicated in the silo state logic (LES) by a wire (SV) of the silo state logic (LES) and secondly the validation of the number of the front coupler by the front mini-processor is indicated to the silo state logic (LES) by the thread (CV) of the coupler validation logic (LVC), characterized by the fact that the positions (A and B) of the input multiplexer (MES) of the silo, on which the incoming channels (dO to d15) are connected are unlocked linked respectively by the silo signals occupied in writing by the central (CEC) and writing of the silo by the front end (FEC), of the state logic of the silo (LES) the outputs of the silo being connected to input positions (B) of the output multiplexer (MSF) unlocked by reception, on a wire (DR) of the multiplexer bus, of a signal presented by the front end, said silo being associated on the one hand with a writing logic (LOE) linked to the state logic of the silo by the wires carrying the silo signals occupied in writing by the central (CEC) and writing of the silo by the front end (FEC) to control wires (LEC, VAL, STR) from the silo bus (bs1) and to a control wire (DA) from the bus multiplexer (bmf) and wires (SV and CV) for validation of the silo and coupler, said silo being associated, on the other hand, with a logic in advance address (LAA) via a line address register (RAD) silo memories, the reset input of said register being connected to a zero address wire (ADO) from the silo state logic (LES), the writing and address advance logics being linked to the son's control (VAL, LEC, STR) of the bus-silo and to said wires (DR, DA) of the bus multiplexer, to the wires carrying the signals (CEC and FEC) of the logic status of the silo (LES), to the wires carrying the validation signals from the silo (SV) and the coupler (CV), the address advance logic being further connected to the wires carrying the signals (CLE and FLE) of the state logic of the silo (LES) so that, on the one hand, writing data from the central coupler on a memory line of the silo is effective by means of a impulse command delivered by the writing logic (LOE) under the effect non-read (LEC), non-validation (VAL) conjugate state signals, validated silo (SV) writing by the central office (CEC) and acknowledgment impulse of the data (STR), the addressing of a following line of memory to register it the following data being carried out by the register (RAD) under the effect of a impulse command presented to said register by the advance logic address (LAA) under the effect of the combined states (VAL, SV, CEC) and the impulse taking into account the data (STR) and that on the other hand, writing data from the front mini-processor is produced by the writing logic (LOE) under the effect of the signals of the conjugate writing states by the front end (FEC) validated coupler (CV) and impulse control data available (DA) the successive addressing of the memory lines of the silo for a reading by the front mini-processor being carried out by means of the address advance logic (LAA) under the effect of the signals of the conjunct states fords: front reading (FLE), validated coupler (CV), data available (DA), each sequence of reading or writing from the silo preceded by a discount to zero of the address register (RAD) by a pulse presented on a wire (ADO) by the silo state logic (LES). 8 / articulation and management system according to claim 7, comprising an OR (VS) port with three inputs, a first input of which is connected, on the other hand, to a positive polarity through a resistor, on the other hand, side central processor, to a working contact of a bus connection relay-silo, said contact being earthed, the second and third inputs being connected to the bus (bmf) of the front mini-processor by wires (CLO) and (SCL) the output of said door (VS) being connected to the state logic of the silo (LES) and to the outgoing track (d 15) by a wire (INI) so that a lock command is issued by said door on the status logic of the silo when the front coupler is not connected to the central coupler (connection relay at rest) or when the mini-processor is not powered (logic level on CLO wire) or when the front coupler is not plugged into the chassis of the front mini-processor (SCL wire) said locking command prohibiting any reading or writing of the silo and being signaled to the front mini-processor by the channel (D 15). 9 / Articulation and management system according to claim 2, in which the central dialogue coupler comprises a first logic of coupling (LC1) connected to the central memory (MC) via a bus direct access (bad) and a memory access controller (MAC) characterized by the fact that said logic comprises on the one hand, a first part transmitter of addresses and data between a microprocessor (MPC) of said central coupler and a memory bank by direct access links (H) to said bank addressed and, on the other hand, a second party transmitting Signals of orders and states on links (I, J, K, L) connected to the control their access to memory (MAC) said links constituting a channel semaphore for transferring said signals previously to signals address and data relating to a memory bank to ensure prior to the availability of said bank as well as the availability availability of direct access links (H) to said bank. 10 / Articulation and management system according to claim 9, character-laughed at by the fact that the first part of the first logic (LC1) contains three writing registers connected in parallel, by their inputs, to output wires (rO to r15, U links) of the microprocessor (MPC) said write registers including a data write register (RDE) comprising input wires (rO to r15) and a control wire (m LDA) a low address register (RAB) with input wires (rO to r14) and at minus a control wire (m LAR) a high address register (RAH) comprising input wires (rO to r14) and a control wire (m MBK) the wires of control of said registers also being connected to the microprocessor, the data write (RDE) and low address (RAB) registers outputs being respectively connected to the input positions (A and B) of a multi-plexer (MX1) and the outputs of the high address register (RAH) being connected at the input positions (B) of a multiplexer (MX2) whose positions input (A) are connected to ground, the outputs of said multiplexers (MX1 and MX2) being connected to the transmit inputs of transceivers (ER1 and ER2) whose grouped outputs form direct access links (H) of the bus (bad) said multiplexers and transceivers being locked (AOD and SEL wires) under the control of the second part of the first logic (LC1) so that the microprocessor loads into the low address register (RAB) the number of the memory box intended for save the data, then load in the high address register (RAH) the number of the memory block and of the memory bank, the data to be written being then loaded into the data write register (RDE) said loads taking place under the control of the microprocessor by application of micro-successive commands on said wires (m LAR, m MBK and m LDA) said wires registers unloading their content on access links (H) direct to memory only after the second part of the first logic (LC1) was able to check the availability of said memory as well as that of direct access bus (bad). 11 / articulation and management system according to claim 10, charac-terrified by the fact that the first part of the first logic has also a data read register (LDM) from the bank addressed memory, said register being connected between the transceiver (ER1) and the microprocessor (MPC) by data transmitting channels (son DMA O to 15), the second part of the first logic (LC1) comprising a write and read logic (LEL) connected on the one hand to the microprocessor (MPC) (control wire m LDA) on the other hand at an input position (B) of the multiplexer (MX1) wire WT) for writing or reading indication, so that, the micro-processor (MPC) having a micro-control on the wire (m LDA) the write and read logic (LEL) generates a status signal O on the wire (WT) said signal signifying to the memory bank when it is addressed, that it is requested for a writing, whereas the non reception of the micro-command allows the write and read logic (LEL) to generate on the wire (WT) a status signal 1 signifying to the memory bank that it is requested for a reading. 12 / Articulation and management system according to claim 11, character-laughed at by the fact that the second part of the first logic (LC1) contains a signal generator (GSM) connected to the writing and reading logic (LEL) (WT wire), said generator being connected to the transceivers (ER1 to ER3) (SEL wire) to a direct access control logic (CAD) (wires LOAD, SEL, SOT) and to the multiplexers (MX1, MX2) (ADD wire), the transmitter-receiver (ER3) being connected to the links (I) transmitting signals from address or data presentation, a logic (CAD) being connected to a transceiver (ER4) (SBZ wire) connected to the receiving lines (J) memory bank numbers available a logic (LOB) for occupation of banks related to the address register (RAH) (PAG son) whose it receives the coded number of the bank to be addressed, with the transceiver (ER4) and with logic (CAD) so that the write signal presented by writing and reading logic (LEL) (level O on WT wire) activates the generator (GSM) which charges the transceiver (ER3) a sampling signal for an imminent emission of said signal on the links (I). said broadcast signifying to the access controller memory (MAC) that an address presentation is in progress, banks available presenting turn 3 turn their number to the logic (LOB) said logic signaling to logic (CAD) the conformity between the bank number received from the register (RAH) and one of the bank numbers sent by the memory access controller (MAC) on links (J) logic (CAD) then transmitting to the controller (MAC) a request for occupancy of said bank by links (K) said controller (MAC) acknowledging receipt of the occupancy request, taking the logic (CAD) and signaling it availability of the direct access bus (bad) by pulse transmission successive presented on links (L) logic (CAD) positioning the transceiver (ER4) as a transmitter and the latter transmitting to the controller (MAC) the bank number correctly analyzed by logic (LOB) said logic (CAD) starting the signal generator (GSM) (SOT, SEL wires) which positions the transceivers as transmitters (ER1 to ER3) and control by wire (ADD) successively the positions (B) then (A) of multiplexers (MX1 and MX2) to transfer the high address and low, then data on the links (H) of the bus (bad) while, when a read signal is presented on the write and read (LEL) (level 1 on WT wire) the controller (MAC) of reception of the address acknowledges receipt to the logic (CAD) which deletes the order from positioning as a transmitter on the transceivers (ER1 to ER3) which move to the receiving position to receive data from the memory bank requested for reading. 13 / articulation and management system according to claim 12, charac-terrified by the fact that the transceiver (ER2) is connected. on the one hand, to write and read logic (LEL) by input data wires (DMX) and on the other hand, to a fault register (RDF) by wires of input data (DMX 12-13) and by a control wire (CANS) said wire state command also linked to the read register (LDM) whose data output are routed to the microprocessor by wires (DMA 0 to 15) the write and read logic (LEL) being connected to the transceiver (ER3) by a control wire (ANS) the register (RDF) being connected by wires (P) to the second output coupling logic (LC2) as the bank, requested for reading, presents an acknowledgment signal to the write and read logic (LEL) via the transmitter-receiver (ER3) positioned as a receiver, said bank simultaneously presenting its reading information on the links (H) said information including first the data of the memory line having been addressed said data being received in the register (LDM) secondly of possible memory and parity faults recorded in the register (RDF) third-the bank code number stored in the writing and reading (LEL) said number then being compared by said logic with that from the registry (RAH) so that, if there is compliance, the logic of writing and reading (LEL) delivers an impulse command on the wire (CANS) for transferring data from the register respectively (LDM) in the microprocessor and the registry fault indications (RDF) in the second logic (LC2). 14 / Articulation and management system according to claim 13, character-laughed at by the fact that the second coupling logic (LC2) is linked to the process central source via a multiplexer bus (bmx) to the first coupling logic (LC1) by links (P, Q) coming respectively from the register of faults (RDF) and the low address register (RAB), said links being distributed on a time delay device (TCG) and on positions inputs of a pair of multiplexers (MX3 and MX4) whose outputs are connected to the bi-directional tracks (00 to 015) of the bus (bmx) said tracks being distributed on a central interrupt logic (LCI) realizing central processor interruptions at the request of the central microprocessor, on a logic (LOC) for decoding the coupler number that constitutes the second coupling logic (LC2) on a queue state logic (LEF) waiting to coordinate handling by the central processor and by the microprocessor (MPC) queues of incoming messages and outgoing from central memory (MC) on a fault logic and initialization (LDI) said logic performing the retransmission, towards the central coupler, faults of incoming and outgoing messages on the bus-silo side towards the front. 15 / articulation and management system according to claim 14, characterized by the fact that the central interrupt logic (LCI) is connected to the microprocessor (MPC) by a control wire (m MEO) to the coupler the central processor by interrupt control wires (ATN, RACK, TACK) and by control wires for masking and unmasking the interrup-tion (00 to 3) to logic (LDC) by a wire recognizing the interrupt-tion (RIT) the logic (LDC) being connected to the input positions 0 of the multi-plexer (MX4) by wires marking the cable identification number of the second logic (LC2) of the wires (SYN1, SYN2) for selecting positions 0 to 3 of the multiplexer (MX4) connecting the logic (LDC) to said multiplexer, from so that after you transfer a message to a memory bank, the central microprocessor gives an interrupt order to the logic (LCI by a wire m MEO) said logic transmitting the interrupt request to the central processor by a wire (ATN) which acknowledges receipt by a wire (RACK) by taking the logic (LCI) which warns the logic (LDC) of the central processor interrupt, said logic selecting the input position 0 of the multiplexer (MX4 by the SYN1 wires, SYN2) and transmitting the identification number to the central processor second logic (LC2), said processor being able to delay the request interrupt formulated by logic (LCI) by presenting a command masking and then unmasking on the corresponding wires (D 0 to D 3). 16 / articulation and management system according to claim 15, character-laughed at by the fact that the queue status logic (LEF) and the coupler number decoding logic (LDC) are connected respectively to the central processor by channels (D 6 to D 15) and (D 4 to D 9) of the multi-bus plexer (bmx) logic (LEF) being connected, on the one hand. to positions input 1 of the multiplexer (MX4) by the wires d (12, 13, 15), on the other hand, to the central microprocessor by the wires (F0D, F1D, F0U, F1U, BSD) the logic (LDC) being connected to the memory access controller (MAC) by wires (ADRS, DR, SR, DA, SYN) so that when the central processor presents a command on the logic (LEF) by one of the channels (D 4 to D 9) there simultaneously presents the coupler number "that is to say the second logic (LC2) for coupling the bus (bmx) to the logic (LDC) by the channels (D
6 to D 15) said logic (LDC) comparing said received number and the number internal wired then, if there is compliance, sending the signal (SYN) to the processor central which acknowledges receipt by wire (SR) said signal combined with number of the coupler allowing the logic (LDC) to select the position input 1 of the multiplexer (MX4) so that. when logic (LEF) receives from the central processor a request to occupy the message list incoming messages or the outgoing message list, if the microprocessor does not not manipulate said list logic (LEF) is warned by the wire (m F0U
or m F1U) and signals it to the central processor (PC) by the wire (d 12 or d 14) whereas when (PC) releases the queue of incoming messages or that of outgoing messages, the logic (LEF) is warned by the wire (D4 or D6) and the signal to the microprocessor by the wire (F0D or F10) the micro-processor can then request the occupation of the queue of incoming messages or that of outgoing messages by presenting a signal on the wire (m F0U or m F1U) the exchanges of signals being carried out by a logic level 1 presented on the designated wires, the central processor having the possibility when a front mini-processor is in trouble, of warn the logic (LEF) by the wire (D9) said logic signaling to the micro-processor by wire (BSD) to stop the transmission of messages to the front faulty, the end of emergency switching is signaled to logic (LEF) by wire (D8). 17 / articulation and management system according to claim 14, charac-terrified by the fact that the fault and initialization logic (LDI) is connected to the channels (D 10 to D 12) of the bus (bmx) of the central processor, to input positions (2) of the multiplexer (MX4) through the wires (d08, d09) to central microprocessor (MPC) by wires (DEF, INI, m DME, m DMS) said logic (LDI) including an initialization request toggle which, when power on the central dialogue coupler places a level signal logic 1 on the wire (INI) so that the micro-program of the micro-processor, turns on the state test of this flip-flop until the processor central returns to state D said tilted by presenting a command on the wire (D 12) said command allowing the start of the dialogue said processor stopping the dialogue (in the case of passage of the bus-silo on the mini-processor ) by presenting a command on the wire (D 11) which sets up the initialization request toggle at state 1, the microprocessor (MPC) warning logic (LDI) by one of the children (m DME or m DMS) when it is warned of an incoming or outgoing message fault on the bus-silo side, said logic transmitting the indication of the fault to the central processor by a wire (d 08 or d 09) and blocking the microprocessor by a command presented on the wire (DEF). 18 / Articulation and management system according to claims 16 and 17, characterized by the fact that the timing device (TCG) is in connection with the outputs of the fault register (RDF) by the wires (d 5 to d 7), and (DAMB) with the central wire interrupt logic (SITO) with a silo state logic (LSO) by the wire (BSB) and with the microprocessor by wires (m DME and m DMS) the wire (d 5) being connected to input position 0 of the multiplexer (MX3) and the wires (d 6 and d 7) being connected to the input position (2) of the multi-plexer (MX4) faults allocated to the memory bank and saved entered in the fault register (RDF) being signaled to the process central threader (d 5 to d 7) indicating respectively a memory fault, a parity fault or a memory failure, the microprocessor (MPC) having a potential on a wire (m DME or m DMS) when it requests memory access to run an incoming or outgoing message and now said potential so much that he did not obtain satisfaction, so that after sale the time provided by the timer device (TCG) delivers a signal on the wire (SITO) to the logic (LCI) which order the interruption of the central processor said interruption also being performed under the control of the state logic of the silo (LSO) which maintains a potential on the wire (BSB) of (TCG) as long as the bus-silo remains unavailable, said interruption may.
still to be performed under the control of the fault register (RDF) which maintains a potential on the wire (DAMB) as long as the bus direct access (bad) is busy. 19. Management and articulation system according to the vendications 16 or 17, characterized in that the exits from the low address register (RAB) consisting of wires (MAO to MA14) are connected to input positions 1 of the multiplexer (MX3) and 3 of the multiplexer (MX4) so that a word address intended to be written to a memory bank, is read by the processor central on the wires (D) of the multiplexer bus (bmx). 20. Management and articulation system according to the resale dication 17, characterized in that the third logic (LC3) comprises in association with the microprocessor (MPC) a pair of couplers (CSA and CSB) respectively connected to the bus-silo (bsl-a) and (bsl-b), by unidirectional control wires (REP, VAL, LEC, STR) and through data channels (p 0 to p 15) bi-directional, said couplers being connected in parallel to the microprocessor outputs by the wires (r 0 to r 15) including the five last (r 11 to r 15) reserved for addressing a front coupler, are derivatives on the entries of a called front number register (RFA) the first four outputs from the register which correspond to the inputs (r 11 to r 14) being connected to the input positions (A) of a multiplexer (MX5) the fifth output of the register which corresponds to the input (r 15) being connected to a selection wire (SEL) said wire being connected to the wires (SELA and SELB) one directly connected to the coupler (CSA) and the other to the coupler (CSB) at through an inverter, the inputs (B) of the multiplexer (MX5) being connected to the wires (r 12 to r 15) and the outputs of said multiplexer being connected to corresponding inputs (r) of couplers (CSA and CSB) the register (RFA) being connected to the microprocessor by a control wire (m FAR) the control (m VAL) of the microprocessor being connected to the couplers (CSA and CSB) and said couplers being respectively connected to a state logic of the silo (LSO) by wires (REPA and REPB) and by wire (STR) logic (LSO) being connected to the microprocessor by the wire (m BS) the microprocessor (MPC) entering in the register (RFA) the number of the front coupler called, the most significant bit 0 or 1 of the address of said front end being presented on the wire (r 15) then upon reception by the register (RFA) of the transfer signal emitted by (MPC) on the wire (m FAR) transmitted on the wire (SEL) in order to select-the coupler (CSA or CSB) connected to the bus-silo serve the coupler front end requested, the multiplexer (MX5) transmitting on an order from (MPC) bits 2 to 2 of the address of the front coupler are received on the wire (m VAL) on the channels (p0 to p3 of the selected bus-silo (MPC) simultaneously alerting the logic (LSO) by the wire (m BS) which generates a command taken into account (STR) said command being transmitted to the front end by the coupler (CSA or CSB) selected which also issues an impulse command the validation on the wire (VAL) the conjunction of the signals (VAL and STR) specifying to the front coupler the transfer of a command issued by the microprocessor on the wires (r 4 and p 4, or r 5 and p 5 or r 6 and p 6) depending on whether it is a request to write the third signal silo (COC), end of writing (CFE signal) or end of reading (CFL signal) carried out by 18 central couplers, 21 / management and articulation system according to claim 20, charac-terrified by the fact that a register (LDF) for reading front-end data is connected to the couplers (CSA and CSB) and to the microprocessor (MPC) by the wires (s0 to s 15) transmitters of read data, said register being also connected to said couplers by a common response wire to the wires (REPA and REPB) the front coupler delivering in response to the request for use pation from the central office, a signal received on the channel (p 9) indicating the occupation of the writing silo by the central office (CEC) said signal (CEC) being accompanied by a response signal (REP) received on the corresponding wire said response signal unlocking the register (LDF) which retransmits the signal (CEC) to the microprocessor so that it transmits data on the channels (p 0 to p 15) of the silo bus by the wires (r 0 to r 15) and the coupler selected. 22 / Management and articulation system according to claims 20 and 21, characterized by the fact that the couplers (CSA and CSB) are connected to the micro-central processor by a wire (m LEC) said microprocessor being notified that it must read the silo of the front coupler by a signal received on channel (p 8) said microprocessor then transmitting simultaneously a read order on the wire (m LEC) of the selected coupler which generates the signal (LEC) and an order to take into account on the logic wire (m BS) (LSO) which generates the signal (STR) so that the data from the silo transmitted on the channels (p 0 to p 15) is received in the microprocessor by means of register diary (LDF) unlocked upon receipt of the response signal. 23 / Management and articulation system according to claim 20, charac-terrified by the fact that the outputs (d 10 to d 14) of the number register (RFA) of the called front end are connected to the input 2 positions of the multiplexer (MX4) of the second logic (LC2) so that the number of the called front end can be read by the central processor at the latter's request.