CA1112324A - Intelligent input-output interface control unit for input-output subsystem - Google Patents

Abstract

Abstract of the Disclosure An intelligent Input-Output Interface Control unit, des-ignated as a Line control Processor, which serves as a cont-rol channel for data-transfers between a main data process-ing system and a plurality of different peripheral devices.
The Line Control Processor operates on a standard communica-tions and control discipline which makes the eccentricities of various peripheral units transparent to the Main System.
Once initiated, the Line Control Processor can execute the data-transfer instructions within the overall system so as to relieve the central processor of involvement in these tasks. Message-block length data buffer memories are pro-vided within the Line Control Processor to permit data-transfers to and from the peripheral device, at the speed suitable to the peripheral device; and also to permit data-transfers between the Line Control Processor and the Main Memory at the high transfer speeds permitted by Main Memory.
Each Line Control Processor is provided with capabilities of handling the idiosyncracies of the peripheral device to which it is dedicated while it provides status control information to the Main System and helps serve as a building block to facilitate expansion of peripheral devices within a data processing system on a simple economic basis. The message-block length buffer memories prevent access errors since complete record length message transfers can occur in any given data-transfer cycle, barring any emergency interrup-tions.

Description

' ' Cross ReEerence to ~elated~ cation~
, . . . _ . ~ , The ~ollowing commonl~ assigned, concurrently ~iled patent applications are related to the su~ect matter of this application:
Serial No. 28~,4S8r ~iled Septembex S, 1977, ~ox Modular Block Unit for Input-output Subsystem.
~odular Processor-Controllers ~or an Input~Output 5ubsystem~ Serial No. 286,459 ~ d Septem~er 4~1~77, for Input-Output Subsystem ~or Digital Data Processi~g System~
and United States Patent No. 4,106,092 G~ugust 8~1978 ~ox Interface System Providing Interface~ to Centr~l Processing Unit.
Field o~ the Invention . This in~ention relates to digital computi~g and~ox data processing systems and is conc~rned with ~he means and methods - of contxolling the transfer o~ da~a ~e~ween a ~ariety o~
di~fexent periphe~al devices and the main memor~-o~ a centr~l I processiny unit or m~in system~ Basically the s~stem involves -~aking the load o~f o~ the processing unit and distributing it among a ~axiety of Intelligent I~O IntPr~ace units whie~
¦ can work independently-o~ ~he central prccessor in handling data trans~er operations.
The invention described herein relates to an e~icient inlpl~mentatiOn Q~ an Intellig~nt IfO Inter~ace unit which i ~ may ~e designated as a hine Con~rol Processor and which provides the intelligence capability of processing and ~ ~ co~trolling data transers between periphercll d~ices and : I the Main System~
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; : ~ -2 ~ackgroun~l o~ the I~vellt:ion The general configuratiorl of a data processillg system typically comprises a processor or proeessors, a main rnemory, and a pluralit-s~ of ~arious ty~es of peripheral de~ices or terminals (sornetimes cal].ed I/0 unit;s), ~hich more specifically may be card readers, magnetic tape units, card punches, printars, disk files, supervisory terminals, and so on. The optimum s~stems generally invol~e t~le configuration wherein the peripheral devices are handled by independent interface control units so that the processor i3 free to access and process data contained in the main memory. In conf.igurations having separate cvntrol mealls ~or the peripheral input-output devices, lt is possible to ha~e parallel or concurrent processing occurring at the sclme ti.~lle that i.nput-output (I/0~ operations occur. ~lese co~current ;~ processing IJ0 operations OGCur within the ~arne program which operates through one of the processors, and which also initiates all input-output operations. In ad~ition the prograrn ~nust have some means of determining ~hen the I/0 operations are inactive or have been completed.
As an example, if a program calls for a file of data to be loaded into the main memory, it must be able to determi.ne ~ ~ when tha-t operatiorl has been completed before it can go allead 'J ~ to make ~se of the data. Thus~ an input-output operatio.rl is initiated or started br the program~ as by some -type of '7initiate instruction" which pro~ides 7 typically, an address ; pointing to an "I/0 descriptor~' which i.s stored i~ the main :~ :
memor~ li5 descriptor identifies the perip~eral de~rice from ~hich data is to b~ recei~ed and~or tral~s~itted~ it : ~ .

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identifies the type of operation such as a '~Read" or a "Write", and ~lso identifies the field o~ main memory locations to bc used in the input-output operation.
Generally this I/0 descriptor is traIlsferred to a con-trol means ~I/0 control means) to control the transfer o~ data between the peripheral terminal device and the main memor~.
When the input-output c;peration is "comple*e", such as ; by the transfer of the data from the peripheral u:nit to the main memory to load the main memory~ then there is a need for some type of a completion statement, which is typical].y referred to as a 'rResult Descriptor". Usually this is transferred from the I/0 control means to so~e specific location in main memory know~ to the progra~ being used.
Typically, the Result Descriptor includes information identifying the p~rtic~lar peripheral terminal de~ic,e and further includes information as to the result o~ or the status of that particular input-output operation, -- thusy to provide information as to whether the transfer was complete and correct, or whether any exception conditions ocourred or whether any errors occurred OT' any other peculiar situations arose in re~ard to the tra~saction invol~i~lg that particular peripheral terminal devi.ce.
ThU5~ when a program initiates an input-output ope.ration, the program must haYe some means to determine when ths input-,~
output operation has been completed. A standard technique in this respect is for the program to ha~e instructions to .. ~
interrogate the Result Descriptors perioclically~ to dete-mine ~: :
wh~n and if a particular input-output operation has been .
completed~ ~0~7eYer, it is much ,simpler if the input-output :i .

con-trol means indica-tcs whetl the transfer operation is .~inished. In accomplishing this, it i.5 usually necessary to interrupt whatever operation the processor has underway, and force it to examine the Result Descriptors and to take appropriate action. This s-topping or interruption of the processor' 5 activities is generally designa-ted as an "Interrupt"~
I~us, when an interrupt occurs, the processor must stop :the program it is working on9 it must ~ake a f:ixed notation of what point in the program execution it was int;errupted and it must then store the contents of cer-tain registers and control flip-flops so it can ha~re information as to where i.t should return in the program a~'ter the completion of the interrupt cycle; alld then the processor must transfer its attention and op~ration to the program designed to handle and service the Interrllpt condition.
Cert~in systems such as the system described herein, have a program for servicing "Interrupt'l conditions, which ;
program i.s someti.mes referred to as MCP or a niaster control program. This program must keep a record of current input-output operations and associate the particular Interrupt with the particlllar input output operatlon that causecl it.
`~ The~ it ~ust anal~ze the results of this Interrupt cycle to s , ~ : see if any unusual circumstances or exceptions occurred or if an error conclition was repor-ted, so that corrective and .~ ~
appropriate action may:be taken. '~he Interrupt program '~ ~ must take.the res~ts o~ the inpilt output operation and malc~ them ~vailable to the program that initiated the inRut , j ~' ~ output operation and then fur-t,her determine if oth~r input-~(, ; : , , ~ 5 -~
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output op~rati,ons are waiting to be initiated and, if 50, to t~ke aCtiOII to initiate other needfu'l .input o~tput operati.ons.
In ~any of -the prior and present, sys~terD. co.nfigurat:ions, many call.s or request for memory access would come in to get memory ser~ice, but because of the ~.ir~ited bandpass and time available for Yarious peripheral units~ ma1ly I/0 -tran~fers would be incomplete and cause "access errors".
A150 many o* the prior art system configurations provided only one or two communication paths or channels to a multitu~e number of peripheral terminal units so that I/0 transfers of a particular peripheral terminal unit had to wait their ' turn ln sharing access and u~e o:f a corl~nunications bus. r~his i.ntroduced congestion ancl ~elay into the system~ It also made dlfficulties in system.s in~olving multi-progran~ling sin~e efforts are made to match a job ~a'Jing hea~y input-' output require~ents with another job that is "processor-bo~nd" and which has only limited input-output rs~uirements.
. Many of the present da~ data processing sys-tems have a single con~unication path or a limited nu~ber of con~unication paths between t}1e central processing unit and the peripheraL
units. Generally within the co~unication path there is one ~ or more "input-output control" means~ ~nen an input-output ,~: , path is requested by a processor, the path will only general:Ly ~ , 25 become available ~hen: the per1pheral unit is not initiating ,, : a transfer operation; the peripher~l unit i5 not busy in a . . : :
:' ~ransfer or other opera-ti.on with the input-output control ~: ~ means; the peripher~l unit or its input-outpllt corltrol mean~
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is not busy with other operations.

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The data-transfer rate of the input-output control ~eans is t of co~lrse~ a limiting factor in the operatio~ of the system since the o~ten slow transfer rate of c.ertain peripheral units (which are passed through the input-output control means) wi~l u~ecessarily tie up the processor and me~ory activ.it~ to the low speed of the peripheral -termi.nal unit.
T~us, ~any data processing systerns have cvme tv be provided with a plurality of input-outpu-t control means which include buf~ers, to permit a particular peripheral or group of peripherals to communicate with the main system.
~hen there ~re a plurality of input-oulput control means (through w~lich pass the communication chan:nels to i~ndividual . peripheral units or groups of such units) some prior art systems have used the method of operating -the da.ta transfer operation in a sequential fashion so tlla.t the various input-output control means take turns in se~vin~ the peripherals which are associated with the~.
A difficulty arises here in that certain peripheral units and thei.r associated input output cvntrol ~leans are busier tha.n othersy and certain of the channels involved actually need more communications-time than -they are ge-tti.ng.
.~ ~ A "cha~lel" may be looked at as a cornmunication path betwee : the ~aln system, through the input-output control means, over to the pcripheral unit. I~lUS, there ca-~l occur ., :
situations ~here oerta.in GhanrAels are "short changed" to the . extent that a great n~lber o~ "access errors" ~ill be ; de~eloped~ Access errors involve the situation where the .~ data bytes being transferr9d through tlle input--output control ' ' ' . ~ _ r;~ r~

means do not comprise complete rnessage l~nits but consist only of non-usable fractions of ~lessage uni-tsO As ,a result of this, -the central processin~ uni-t would not be getting or Iransferri..ng use.ful info-rmation and would have to become g fixated on continually requesting the same input~output operations over and o~er again. Thus, when the peripheral u~its are placed in a situation where they are unable to send or recei~e an entire messa~e unit or record, then the likelihood of acsess errors occurs which leads to uncompleted c,vcles in regard to a particular channel and no successfui completion of transfer of the required infor~lational data.
It is desired that the rnaxirnum transfer of data, occur through the mentio~ed plurali,ty of input-output control means,and wit~lOUt such access errors which lead -to incompLete cycles of data transfer (~hich are unusable, and the time period of which is wasted and of no use 9 thus tying up ,' val~lable processor time).
' Thus, in s7lch a system configuration, problems arise ,, in regard to how much time should be alloca-ted to each of ,, 20 the indiv:idual channels for data transfer operations and the ~urther pro'blem of whieh channels should be given priority status o~er the other channels~
" Now~ in data processing systems where multitudes o~
pe~ipheral units are inYolved (many of which are at ~25 differently located installation sites) i-t is necessary to h~e groupings o~` input-07ltput control means to handle the varietr ~f Fsriphei~al uni~s a-t ~,ach given site. Thus~ the .
pri~rity probl~ms invol~e not only th~ priority to be ~`` given as to the competition amvng peripheral 7lnits at one .~ `. ' - .
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local given site ? but also invol~e t~i~e priority prob~ems of priori.ty allocation as bet~een the different loca~ionaï sites, each of which ha~e their own input-outpu-t con-trol means.
Summary of th~s In~erltion The present invention in~ol~es a digital data processing system for the control and handling of i~p-u-t-output operations (data transfers) 3iS between a plurality of variows types of periphera]. units and a central Main System (Processor and Main Memory). Two types of I/O Subsystems are provided for ~0 communication to the central Main Sy~te~l.
~ One I/O Subsystem is a sys.tem wherein a type of i~.t~ll.igent interface control unit, desi~slated as a ~'Line Control Processox" (~CP), is used~ and wherein each LCP, wlLile performi~lg the same basic fu:nctions, is specifically oriented to control and handle data tr~nsfers to and from speclfic type of peripheral terminal unit. ~or example, a hasic LCP would be adapted for each speci~ic i.nstance to han~le a card reader, a disk unit, a tr~in printer, or other special type of peripheral unit. The LCP's are placed in groups, typical~y, of elght uni.ts, to form an LCP Base ~lodule.
Then each o~ the Base Module.s are grouped in a set of three to form an lCP Cabinet Unit. A plurality of such LC~
Cabinet Units may be used to consti.tute the first I/O
Subsystem.
3 ~ 25 Aniother I/O Subsystem is pro~ided ~or those types of 3 ~ peripheral termi~al Imits for which no specific ~ine Control ~ Processors (LCP) ha~e been developed. This iecon~ I/O
, ~! : Suibsystem lS organized so -that a Cen-traI Co~trol un:i-t is provided to contro~ the pathiing .rom the Central Processor : ' . .
~, _ g _ : ~ ' and Main Memor~ to selected input-output channels which pro~ide a data path to indi~idual peripheral mits. These individual channels will each ha~e t~eir own memory ~uffer and connect through the Centxal C:ontrol un.it over to the Main Systamc In the I~O Subsystàm using ~he ~ine Control Processors, ~he Main Sys~em Cof Processor and Main Memory~ is also pro~
~ided with a ~nit call~d an Input~Output Translator unit (IOT~ which ~ecomes part o~ the Main Sy~tem and provides an.
inter~ace ~etween the Main Sy~tem and another distribution-control interface designated as "Distribution Card Unit"
which handles a Base ~odule, Ca group of Line Control PLO-cessors~ and which connects a s21ected individual Line Control Processo~ into the LCP I~O Subsystem.
Th~3 . Lin~ Con~rol Processor ' s ~LCP ' s~ are organi~ed in groups of eight called the ~CP Base Module each of which h~s a single "Distribution Card Unit" which pxovides the inter~ace ~etween the Input~Output Translatorl IOT, o~ the Main System and the ei~ht ~CP's of any gi~.en Base Module~
E~ch base Module also carries ~ Maintenance Card unit which can pxovide all maintenance and checkin~ ~unctions for the group of eight LCP's o~ the Base ModuleO Each Base Module is also pro~.ided with o~e common "Termination Card Unit"
~hich pro~ides commo~ clocking ~unctions for all the LCP's of the group and also provides prop~r termi~ations ~or the ~ransmission lines ~hich connec~ the ~arious LCP's~ the Dis-tribu~ion Card, and the~Maintenance Card of tha~ particular B~se Module~
The IOT o the Main System works in a uni~ue relation-~ .
¦ 30 ship with ~he Distribution Card Unit of the Base Module of . the LCP's in the LCP I~O
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~ubsy~-tem, se~n~ to setup data-trans~e~s between ~he peripheral units and the Maln Memory in a fashion that does not burden the Central Processor and which permits concurrent data-transfer operations to occur between any number of peripheral units and the Main Memor~. This is facilitated by the use of a xecord-length buffer memory in each LCP. The data-transfer cycle is accomplished using complete data message-blocks which ~hus prevént 'laccess errors" from occuring. .
: ' The embodiment of the invention described herein provides a system which helps alleviate certain problems inherent in prior art systems. By providing a separate channel from the : Main System to each peripheral unit, there is no need for :~
data transfers (between a particular peripheral unit and the Main System) to have to wait for the use of a shared communi-cation channel, since each individual peripheral uni.t is provided with its own channel, and thus each o the plurallty of peripheral units can simultaneously and concurrently consummG;e input operations wi~hout any further requirements from the processor or without interference to processor operations. The input-output data-transfer control means in the Subsystem is provided by an individual "Line Control Processor" (LCP) for each peripheral unit. The "Line Control Processors" accept input-output commands from the Main ~; Memory ~via ~he I~O Translator unit) and they execute these , :
commands independently of the main processor, so that input-: output control operations are performed in parallel with and , : asynchronously with processing.

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! 3 ~ memox~ control unàt 10c~FIG.lA~ xe~ulates the ~low of data betw~en the Main Memor~, ~he Cen~ral Processor and the I~O Subs~stem~ It ~llo~s ea~h of the system components to h~e access to Main Memox~ on a priority basis, ~iving the highes-t priority to the I~O Su~system. Since the memory control opexates indep~ndently o~ the Processor~ the Pro~
cessor is fxee ~o p~r~oxm memor~-independent-~unctions at the same time that memory accesses are being gxanted to the ~0 Subsystem.
lQ The ~ine Control Processo~s are each pro~ided with memory buffers which can stoxe an entire message~block or ~ecord-length.o~ data. ~hus, data txansexs between Main Memory and khe Line Control Processor can take place at high speed and constitute a complete message-blo~k in it-sel~.~ Since a complete message-block o~ data is trans~err-ed in any given cycle, the problem o~ access errors is el~
, :.~ iminated so that no urther memory cycle.time is requixed : to complete "incomplete ~ormer da~a trans~er cycles", which ¦: . mi~ht occur absent the recoxd~length ~uf~er O
The Line ~ontrol Pxocessoxs are unctionally the same except that mino~ varia~ions may occur so that they are a~apta~le to work with diexent types o~ peripheral termlnal:units, and,~as such, the LCP~s are "transparent"
the Main 5ys~em.
n certain cases, th~re are peripheral units and data storage de~ices inYol~ed for which no speci~ic Lihe Control Processors ~P~ ha~e ~een developea~ In this case, there is used another input-output oont~ol subsyst:em which can :~ operat~ in p~xallal with the ~irst I~O Subsystem and its ~ ~ 3~ Lne Control Processors UCP).

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,~ The main or central system o~ the described embodi-ment, which may include the Processor, the Main Memory, and the Memor~ Control, i~ ~urnished with a unit called an Input-Output Translator or IOT. The IOT is a special portion of the Processor which, upon receipt: o an I~O descriptor ~rom memory, works in conjunction ~ith the LCP Base Module to establish conneation to the par~icular ~CP 1~ the channel s~ecified by the "Initiate IfO" instruction fxom the pro-~ gx~m. The IOT translates the I/O descriptor into a orm ~Command Descriptor~ recognizable to the LCP ~Line Control Pxocessor], and when connection is established, passes the ; txanslated descxipto~ over to the ~CP ater which the data : j . transmission may begin. During the time that data is being ~ transferre~ ~etween LCP and the Main Syst~m, the IOT~ upon : demand b~ the LCP, requests memory accesses, addresses mem-. oxy, then modi~ies ~nd compa~es the data addresses. The ` ~; IOT controls the routing o~ data between the selected LCP
` :1 and the Main Systemf and it per~orms translation CAscIIf~
.-. EB~DIC¦ of the data i~ so ~equired~ ASCII~EBCDIC re~ers to American Standard Code ~ox Infoxmation Interchange~Extended ¦ Binar~ Coded Decimal Interchange Code~ Upon completion of : an operation~ the IOT accepts Result Descriptor ~R~D~ infor-.
: mation ~xom an ~CP and:then stores the Result Descriptor R~DI in:a prqdetermined location.
The hine Control Pxocessor, CLCP~, is a device which ~ ; upon xeceip~ o~ a CommandDescrip~or ~C~Dl from the Main : ~ : Sys~em ~ia the IO~ establishes a communication path to a selected peripheral unit. Once this path :is a~tabli~,hedr the LCP accepts da~a ~rom or passes da~a ~o, ~h~ peripheral 3P de~ice. Since each LCP has a ~Idata bufer" ~typically 256 ~ ' :
:~ ~13 : ' ' ~ordsl, then da~a can be trans~exred to and ~om ~he peripheral device at the compaxati~el~ low speed rate of the peripheral de~ice; then~ ~hen the ~uffer is ~ull~ the data can be trans~erred to the central Main System at the highest rate pexmitted b~ speed o the M~in Me.mory. Thus~
a unique in-terworking relationship exists ~etween the IOT
~Input-Output Tra~slatorl o~ the Main 5ys~em and the LCP
~hich is the inter~ace control bet~een the pexipheral units and the Main S~stem~ ~urther, a unique working xelationship exists betw~en each LCP and ~he Distri~u~ion Card Unit of its Base Module, which interfaces a giv~n ~CP to the IOT
o~ the Main System.. The Dis~xibution Unit not only provides for in-terconnection of the Main System to a selected LCP
but also regulates priorities among LCP~s ~or access to Main ~emory. .
The.in~ention~ particularly claimed within tha I~O
Subs~stem, descxibed h~rein, is an Intelligent I~O Interface ` ~`
.~ unit designated as a hine ~ontrol Processor which supplies : . the functions mentioned above~
Some o~ the major objecti~es o~ the Line Control ~rocessor I~O Subs~stem may be summarized as follows:

¦ To relieve the Central Processing Unit ~rom getting : ` : .
~ ~nvol~ed in monitoring and controlling data trans~ers be-twaen,the System' 5 Main Memory and a large number of peri-pheral unitsn :~ To increas~ the ra~ o~ data trans~er bet~een a vaxi~ty ; ~ o~ diFferent peripheral unlts all connected to the ~ain S~stem having a Main Memory an~ Processor. Thi~ inoludes .. 30 ` ~ .
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tr~n~fers ~ro~ the ~a~n ~emor~ to an~ indi~idual peripheral ~n th~s s~stem and Yice ~ersa.
To pro~de an Intelligent ItO Interface control unit ~Line Contxol Processorl which trill relie~e the Central Pro-cessor of many burdens and which will be responsive to the needs of various pexipheral units for access to the Main Memory.
To prov;de an Intelligent Interface I~O control unit which can receive an I/O instruction from the Central Processing unit and then independently continue in regard to controlling, monitoring~ and executing this instruction so as to accomplish data transfer between Main System Memory and any specifically desired peripheral unit. This is done asynchronously as the needs and the requirements arise. The interface unit (LCP) also handles the error-checking of all word and message block transmissions in addition to keeping the Main System informed of the status of any data-transfer cycle, as to its completeness, incompleteness, error-status~
The ~ine Control Processor also monitors requests from a peripheral unit for access to Main Memory and informs the Main Systern of "busyness" of the peripheral unit or its unavailability.
To permit easy modular system expansion. The I/O
; ~ Subsystem of the Central Processing unit servicing a plurality of terminal units is setup such that the inter~ace units (Line Control Processor) are organized in .
Base Modules in groups of eight units. Each module has a Distribution Card Unit which interfaces the group of eight Line Control Processors to the Main System via the IOT of ¦ ~ the Main systemO I'he Distribution Unit can ~lUS set 30~
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priorities as between any one of the eight Line Centrol Prooessors in the Base Module. ~urther, when a plurality o~ Base Modules occur in the System ~hen the Distribution Unit Or each Base Module can be given a priority ranking ~designated global priority) as between the priority ra~k granted to any given ~ase Module, wi-thin the ~ull set of - Base Modules. Thus, another object of the I/0 Subsystem involved is to provide arrangements for setting up Global Priority (priority as between Base Modules in the System) and also ~ocal Priority (Priority as to precedence status of each Line Control Processor in the gro~lp of eight Line Control Processors in the Base Module).
' To eliminate l'access errors" so that all the data required at any given time for -the Main System (that is, a , 15 ~essage length block of data) is always transmitted and error-checked in one complete cycle without interruption (except under emergenc~ conditions).
To permit the rapid completion of a data-transfer operation as between the System's Maîn Memory and a gi~en peripheral unit, without interruption or incomplete data~
transfer9 once a communication channel is established (except for certaln emergencies).
To provide the Main System with the current status of any Line Control Processor at all times and the results 25 ~ ~co~plete, incomp7ete or in error) o~ any given data-transfer cycle.
To provide modular building blocks for facilitating the expansion of the System by increasing t~le number of peripheral devic~s that can be included in the System in a sim~le ,`,~
3 ecQnomical ~ashion.
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To provide an I~O Su~sy~tem whereby the Central Pro cessor is relieved of executing I~O data~trans~er cycles and this work load is distributecl throu~hout the system via I~O control units ~Line Control Processors) grouped in mod-ular block units.
Brie Description_of the Drawing~;

-. The I~O Subsystem described herein a~d the operative components invol~ed will be b~tter understood with reference to the~following drawings o~ which:
FIG. lA is a schematic of a central Data Processing System ha~ing two di~erent types of I/O Subsystems; the two I/O Subsystems are designated as ~a) ~he Central Contr-: . ol Subsys-tem CCC~ with Input-Output Controllers ~IOC~ and bl the Line Control Processor ~LCP) Input-Output Subsystem;
.~. FIGSo lB, lC, lD, and lE, are schematics which indi-; ~ - cate ~arious components of the Central Contxol type of I~O
:- . ~ S~bsystem; : .
. ,~ . ., FIG. 2 is a schematic drawing of a modular unit o~

. the LCP I~O Su~system known as the LCP Base Module showing 20 its relationship to a variety of peripheral devices;

. 3 is a sc~ematic drawing of the cPntral processing unit of the Main System c)f the Line Control Processor IiO
: ~ :
Subsystem;
XG. 4A 1~ a simplified schematic showing ~he basic conIlective relationships bet.ween the Main System, the Line , , C~ntxol Processor;and a periphexal unit within the Line :Con~rol Processor I~O 5u~sygtem;

. : FIG. 4B is a chart indicating vari.ous codes for the :
various ~instructions executable by a Line Control Processor, 30 ; LCP; ~ -~17 ~ :
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.~ ' : 1:' FIG. 4C is ~ chart sh~wing how ~our in~ormativnal digits tABCD~ are organized such that a ~ine Control Procèssor can inform the Main System o~ operational result~
via a "R~sult Descriptor";
FIG. 5A is a chart of digitcll in~ormation ~Descriptors) used ~y the Input~Output Translator ~IOT~ to generate Co~mand Messages CC/Ml;
G. 5B is a schematic sho~ing the data.field boundar-ies o~ the Descriptors in FIG. 5A;
FIG. 5C is a block diagram of the Input-Output Trans-lator ~IOTI in its relationship to the Main System (Process-i or and Memoryl and to the hine Control Processor (~CP);
j ~IG. 5D is a char~ showing the information array in the IOT Descriptor Register;
FIG. 5E ~hows the mes~age 1 el interface between the IOT and the Distribution Card unit of theLCP Base Module;
:~ : FI~. 5F is a sketch o~ the IOT scratchpad memory;
: : PIG. SG is a sketch illustrating the address memory :~ : sc~atchpad of tha IOT CInput-Output Transl.atorl;
FIG~ 6A is a logi~ flow diagram of the in~er~ace be~ween the Main System and the.~ine Con~rol Processor ~LCP~;
: FXG. ~B is a generalized block diagram of a Line :~ ~ontrol Pxocessor;
IG. 6C is another generalized block diagram of a Line Control Processor with detail in regard to its data bu~fer : "
memory;
FIG. 6D is a detailed ~unctional block diagram of the ine Co~tro~ Processor, . , .
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FIGo 6E is a diagram sh~wing the intercooperating . logic and control signals ~etween the I~put-~utput Translator CIOT~ o~ the Main System and the Di~tribution Card unit ~or Llne Con~rol Processors wi~hin a Base i - ~odule FIG. 6~ is a chart showing the arrangement of ~
message block and the composition of a digital word;
FIG. 7A is a logic ~low diagram o~ a Line Control ,~
Pxocessox which ~and1es a peripheral unit and show~ the "status counts" or UReceipt o~ Instructions";
~IG. 7B is a ~low diagram s~o~ing how the Line Contxol Processor ha~dle~ a ~'Write" operation;
E'IG. 7C is a ~low diagram sho~ing ho~ a ~ine Control . . Processor handles the "Read" operation;.
:` FIG. 7D is a ~low diagram shD~ing how the Line Con~rol j . . . . .
~ Processor logically handles the Result Descriptor;
. : .
- FIG~ 7E~1 and 7E-2 ~ogethex ~orm a logic diagram showLng the overall iQgiC ~low o~ the Line Control .i, Processor.
2n :
~1 ;i. :

: : :

: ~ ~

Descri~tion o~ the_Rre~erred ~mbodimen~
The digital system described herein consists o~ a Processor, a ~emory, a series of Input-Output.Controllers CIOC's~ ~orming a first I/O 5ubsystem and a system of Line Control Processors ~LCP's) that make up a second I~O
Subsystem. The Line Control Processors basically handle input~output operations for specific peripherals with minimal interference to main processor.operations. Further, no peripheLal device is "hung up" waiting or memory access, ~ince the LCP ~or that peripheral is always readily available to service its peripheral.
A substantial number of prior data processing syst~ms utilize a hierarchical system of Main Memory in which a large capacity, slow ~ulk memory must transfer in~ormation ~ to a small high~speed processor memory before that infor-m~tion can be used. The pxesently described systffm allows ':
: ` the Processor and the I~O.~ubsystem to.. directly access ! ' . any area of memory, and since the memory size may go up . to one-million bytes, far more information is available to the Processor without the.impos:Ltion of additional I/O

~ acti~ity. This system may be provided.with high-speed ¦ ~50 nanosecond cycl~ time) bipolar memory together with an i error correction system. Bip~lar memory is not.only ~ast, :1 but is inherently more i~mune to the type of ~rrors that : cause program.failux~s, If an.error is detected, the error , ` sorrection occurs duri~g the normal memory cycle and there :~ ~ is no addition~l time re~uired for a correction.cycle.

: ~ ~a~ious operating relationships between the processors main memory and other units o the present system may be found : :
in a Burroughs Corporation publioatiQn entitled ''Burroughs B2800/B 3800/B 4800 series, MS-2 R~f~rence ~lanual~ Catalog . i 10905601 Cop~ ht 197~

Noxmally, I/O memory cycles account only for a small fraction o~ the total number o~ memory cycles available.

~Io~eYer~ dur~ng pari~ds o~ hi~gh r~O acti~it~, the prob~bility o~ any two dev~ces re~uesting t~e same memory cycle increases.
When, due to simultaneous re~ues ~,a de~ice fails to get acoess to memor~ within a system-allotted time period, then valuable time is lost while the operation is retried.
Furthermore, during periods of low X~O activity,many memory cycles are unused.

- The I/O activity problems are solwed in the present system by distributing the I/O processing among a group of LCP's or Line Control Processors orgainized into Base Modules ~ o eight LCP's each. In so doing, the Central Processor is ; ~ only required to initiate the I/O activity and it takes no i further role in the Input-Output (I/O) operation. The Central , I .
Prooessor inititates the I/O activity through a device called the Input-Output Translator (IOT~.
- The ~CP, once initiated, can buffer large amounts of data and, in most cases t an entire message block. At some .~ ; i point in the operation, the LCP requests an access to memory and when the access is granted, LCP transfers the inormation from its "word buffer" to the Memory at the maximum rate o memory operation. Now, if the xequested access to memory is n~t granted, ~CP continues to fill its word data bufer while waiting for an opportunity to access Memory. Thus, the perlphexal device is now protected against no-activity since its data transfers to the buffer of the LCP, which transfers ~: . .
it to~the Main Memory without missing a memory access period.
i m e result of this method and system is that the peak ; ~ I loa~s impo~ed upon the Memory by the demanas of I/O activity !
are eliminated; instead, the IJO Subsystem utilizes those ; memory cycles that would o~harwise be missed. Since this : ~
~21-:: 1 method o~ I~O pxocess~ng is moxe e~ic~ent, the s~stem is mora capa~le o~ a higher input~output CI~Ol data ~xansfer rate and can also support more I~O de~ices.
In the instant computex system wherei~ there are two categoxies of Input-Output Su~systems, that is, the second Subs~stem of I~O contxols and the æirst Subsystem of an Input~Output Translator wor~in~ with a group of Line Control Processors~ the control of ~he system is~acilitated ~y the use o~ "descrip~or" in~onmation which is passed among the various units.
A "Result Descxiptor" is a report to the Main operating system that describes the manner in which-an operation was compl~ted or the reason why the operation could not be completed. The Result Descriptors for the Processor and for the I~O control sy~items are 16 bits C~ne wordl }ong. The .
LCP Result Descriptors may be longer than one word, however~
and each ~it in the Result Descriptox represents the status o~ some condition that iB to be reported to the Main opera~-ing System~ .
: - 20 The LGP's ~Line Control Proeessors) and the IfOC's ~I~O Controllers~ al~ays write ~Result Descriptor~ upon completion of an operation: the Processor ~rites a Result Descriptor onl~ i an error condi~ion was encountered.
Result Descriptors a~e written into predetermined locations in ~emory; for the Processor, the location is address B0, for example.
, The Result Descriptors or th~ LCP's and ~he I/OC's re written into locations ~egi.nning a~ ~he address speci-~ied ~y the e~uatlon ~CHx202 plus 200, where CH is the channel : 30 : : -~2 . : , : , .

num~ex o~ the i~itiated de~ice, The IOT ~e.sult Descriptor is written into address 260G After the Result Descriptor has been writtenl an interrupt is generated~ -LCP Result Descri~tors, R~D: Upon the completion o~ its assigned operatio~, the LCP stores a Result Descriptor, which descri~es to the Processor the manner in which the operation was completed~ A~ ~CP Result Descriptor may ~onsist o~ one, two, or three 16-bit words~ Th~ ~irst Result Descriptor, ~D, is stored in Memory.at the location speci-~ied ~y the equation CCH x 20l plus 108, where CH is the channel number of an ~C~ more than.one word o Result ~escriptox in~ormation is to be ~ritten Cextended Result Descxiptorl, the addition~l words are s~ored in the address memory of the IOT. ~s shown in the table I.beLow, the first LCP Result Descriptor word is preceded by a l-word link and the channel CIoT~ Result Descrip~or~ Typically, the link is used by the operatin~ Sys~e~ as an address to the next : ~
: Result Descriptor to be.examined. Table II shows the basic word ~orma~ for a "data" word ha~ing 4 digits, A, B, C, D~
j 20 where each digit has 4 bits and each character has 8 bits.
S ~ ols are used to designate parts o~ each digit, as A8, ;: ~ A4, A2~ Al, etc. : :
T~BLE I . Result Descriptor I 6 - DI~ 16-BIT~ 16-BIT
: : . CH~NNEL~IOT~ ~ L~P
~ ~ RESULT DESCRIPTOR LINK RESULT D~SCRIPTOR
.: '~ 9 .
CHx20)~ 100 ~ (C~ x ~0)~ 108 : J :
. Channel~LCP Result Descriptor hocation in ~emor~
-23- . _ ' ~;

T~BLE II ; Dat~ ~ord Di~its - - - A B C

A8 B8 C8 D8 ) ~4 B4 C4 D4 One Digit = 4 bits ~2 B2 C2 D2 1 Al sl Cl Dl J

One Character = 8 bits = AB
. -One ~ord - ABCD ~ 16 bits The table III below indicates the forrnat ~or the I/O
descriptor which is normally s~ored i~ Main Memory and then accessed in order to regulate a particular type of Input/
Output operationO As will ba seen there are four syllables, wherein each syllable is composed o~ 6 digits. These digits are nu~bered Dl - D6, D7 - D12~ D13 - D18, D19 ~ D24, to indicate the relative positions of each digit. In syllablP
:. . , 1, the digits Dl and D2 always specify the type of input~

. . output operation to be per~orm0d and are generally called the l'OP-code".. Digits D3 ~ D6 are referred to as "variant

2~ di~its" in that they speci~y the various options that a ; ~ speci~ic input-output operatio~ can incorporate.
~ ~ ~ , .
: ~ Syllable 2 contains the address o~ the most signif icant digit (MSD~ of the Mai~ Memory saction which is u~ed in this .
I particular.i~putjoutput operation as a memory buffer area.
, ,' This b~f~er area is re~erred to as the beyinni~g address.

Syllable 3 ~ontains the address o the least significant , ' ~digit plus 1 ~LSD~l~ o the input~output core memory buf~er :' ~xea which is referred to as the "ending addxess~O The most

3~ :

.
:

signi.ficant address and the least sigrificant add,ress plu3 1 represent the maxim~n memo.y boundary limits of a ~ecord being tra~ls~itted. The length o~ the record may or may not utilize the entire area within this limit. But an attempt to exceed this limit causes termination of data transmission to that area~
S~llable 4 is used only for disk file desc:riptors and contains the disk address~
. The length of the record may or may not utilize the entire area within the beginning address and ending address limits. As stated~ an attempt to exceed this limit causes termination of data transmission to that ~.rea. ~or example, punch cards may be read into an area greater than 80 characters, that is, with a MSD and an LSD+l at 80 characters apart, or they may be read into an area less tha~ 80 characters; for e~mpleg the record area defined in-a ~- particular obJect program reflects 40 characters in a card reader record. Data within columns 1 through 40 of the punch card are stored in the record area of core memory zo allocated by MSD and LSD~l~

. .

.
~ ' ' ' '~
:
~: . .- - -- , . . ..
:
: ~.
: .. .-, : : :::
' .' ,,, ' ,' : ' " , ' :
. : ' ' : - ~ :

~:

o ~ I ~. I , ~ o 1 ~ 0 ~

~ ~ ~ , . .

H ~ ~ ç u ~ ] ~

:" ~ : ~

~ ~ - 2~i -S~s-tem Des'cri~'t'io'n':''C~'en'e'ral1 An I~O Subs~stem is~ provided as part of a digital system environment to supply means'of com~unication between a c~ntxal ? ' data processing ~ystem and a variety o~ peripheral devices which are attached to and work within the sys~em. The ; , peripheral devices which work with.the overal digital system here;n vary from mass storage devices, such as disks or disk packs, to system control devic~s such as the operator's ~ ~ , supervisory terminal) or to a variety of o~her peripheral : , `, lO devices such as printers, card readers, card ~unches~ magnetic tape stoxage devices, and so on.
' The I/O Subsystem described herein can be divided into; ! twu major subsystem categories, based on the method by which the ~axious peripheral devices are controlled~ The first ~`. i . :
category uses a method which employs I/O Controllers(IOCs) : . ~ ' workins in conjunction with the Processor and a Central , . , .. .. ~: .' ,.. ; :

: , , . :: , - . ... .. . . :: . .,.: . . . .

Control to handle I~O activit~ The second cate~oxy uses an Input Output Translator CIOTl in the central processing unit which works with indiYidual units called Line Control Processors CLCRls~. The uni~s known as Line Control ~xocessoxs are the devices which est~blish a communication path from the System ~Main Memory and Processor~ to a specific peripheral device. Once the communication path is established, the LCP can accept data from, or pass data to, the specific peripheral device t for later transmission to the Main System~ Since each hCP has a built~in data buffer~
then data can be trans~erred to and from the yiven peripher-al device at the comparatively l~w speed rat~ of the device;
, ho~ever, when the data bu~e.r o~ t~e LCP is connected to ¦ tran~mit to the Main Syste~ Memoxy and Processor, the data ~ I can be ~ransferred to the Main S~s~em a~ the highest rate allowed by the Memory of the Central System.
-; The ~irst category o~ I~O Subsystems which use IOCIs as~an intar~ace ~rom a peripheral to th~ Main Memory and . . : .
~rocessor has a Cantral Control ~CC~ unit which links the I~O channel and IOC with the Central Processor and Memory~
, These Input-Output Controllers accept instructions from the ; I Processor and they return data in~ormation invo1ving the I result of what happened regardin~ ~hat particular instruc~
tion~ This result in~ormation is plac~d in a speci~ied location in the Main Memory.
In the ~econd cate~ory of IjO Subsystem is the system ~herein the Processor and Main Memory communicate, via an Input-Output Translator ~IOT) r to a group o~ ~,CP Base Modules, j each Module oE which constitutes a unit supporting a group : ~ 0 ' -~8~
. ,: . _.
.~
. "

--- ;

of 8 Line Control Processor~ ~LCP'sl~ Thus an instruction from the Processor is translated by the IOT into a special~
ized set o commands ~hich is ac~epta~l~ to individual LCP's.
A~ter an ~CP accepts instructions ~rom the IGT, it will then report ~ack certain "result in~ormation" which is stored in a speci~ied location in the Main Memor~.
Thus, in this second I~O Subsystem, all.communications between the main s~stem Pxocessor and Memory over to a specified peripheral de~ice are controlled by an hCP which is uniquely~suited to that particular peripheral.de~ice.
~ hen a Line Control.Processor ~CP, ~r an Input-Output Contxol rneans havin~ a Centxal ControII is installed, it is ~ssiyned a unique number called its "channel number". For I/O Controls this.number corresponds to a word o~ scratch-pad memory located in.the Processor. For Line Control Pro-cessors CLCP ~ ~ this "channel num~er" corresponds to a word o~ scratchpad memoxy in the Input Output Translator ~IOT~.
To:accomplish an input~output operation in the.system, an IfO reguest is initiàted by an Initiate I~O Instruction which tel~ the Processox where to ~ind the appropriate IjO
Descriptor in the Main Memory and also which channel number it is intended ~or. ~The I~O Descriptor contains the OP code :and also ~he variants or ~he kind of I~O operation saIec~ed, and the ~eginnin~ ~A~ and ending tB~ ~ain Memor~ address of the r~mory area involved.
.

3 ~ The~Pro~essor accesses this I~O Descrip~o~ and then sends ~he OP code~ and its variants to the selected IOC
C~i.rst Subsystem) or to the IOT (~econd Su~system~.~The IOC
~ ox the IOT verifies the OP code and signi~ies acceptance or .: ~: :~:. 3~ rejection o~ the xequest.
~: : :: :
~; : ~ .
'~ :: . ,~
~ , . .

.) , In the ~irst Subs~stem the Processor.then loads the beginning ~1 and the ending CB~ addxesses..into a local register and infonms the IOC thalt the addresses are ~v~ilable. These ~articular addresses are trans~erred by the IOC into the scratchpad memory location or that designated I~O channel.
In the second Subsystem the IOT accesses the A and the B ~ddresses directly rom the memory address lines : leading to the Processor's "local register", 10pr ~IG. 3, ~ 10 àt the time o~ trans~er from Main Memory and i:hus ~he IOT
: loads its own local scratchpad memory lOpS.
. The.access to Main Memor~ is shared.by the IOT, the I . . Central Control and the Processor 7 l'he highest.priority is ; ~ . shared by the IO~ and the Central Control. The timing may ~ ¦ be so~ar~anged that each Central Co~trol is guaranteed and . . limited to ev2ry fourth mem~r~ cycle ~at, for example, 8 : - ~ The IOT is ~uaranteed the xemai~ing cycles. When the Central Control is not requesting memory,.then the IO~
~ :
: :can take all the memory cycles. The Processor takes all: 20 memory cycles.available on a lowest priority basis.
Thu8, I~O communications in the system~re~uire tha.
` . the Processor execute an Initiate I/O Instruction ~hich may be designated, for exam~le, as OP = 94)~ This.Initiate 't ' ~ Instruction speci~ies the channel num~er o~.the requested device and also the~location of the I/O De~criptor in Main Memory. `he I~O Descrip~r specifi~g t~e actlon ~o be taken by t~t2 peripheral device and specifies the boundaries in Memory of ~he da~a field. The Descripto~s, and the na~ner in which the~ are executed, vary, deperlaing on the : ~ 30 method by which the pexipheral davice i~ contl.olled.

-30- .

If an Initi~te ~O Instruction is executed for a c~hannel i~ containing an I~O Control ~first I/O Subsystem~, then the Processor sends the Descriptor OP code, variants and a C
address (if usedl to the I/O Conlrol. The A (beginning~ and B (ending) addresses of the Descriptor are stored in the -- Processor's I~O cha~nel address memoryO The I/O Control verifies that the OP code i5 valid, then signals the i peripheral device that a data transfer is to begin.
j As was previously discussed, the embodiment o~ the Ç
present digital system involves a duality of Tnput/Output Subsystems. The second of these involve a Central System with Input/Output Translator tIOT), a Base Module having a plurality of I~ine Control Processors ~LCP) and a plurality of peripheral units; the first I/O Subsystem involves, as seen in FIG. lA, a Central Control unit 12 which interfaces ., . .I . .
with a plurality of I/Q controls 13a and 13b which interface - with a plurality of peripheral devices 14a and 14b etc.
I The ~ollowing discussion wi]l involve the first I/O
.
Subsystem lnvolving IOC's with Central Controllers, CC.
The FIG. lB shows the system of connecting the I/O
channels with the Processor l0p, and the Main Memory l0~
through khe Central Control 12. Logic levels are generated j in each I/O channel l00, l0l (FIG. lC) and combined by Central Control 12 before being sent to the Processor l0p and the Main Memory l0m. O-ther logic levels are generated by the ~! Processor, and within the Memory~ and distributed by Central '~ Control 12 to each I~O control such as l3al FIGS. lA and lB.
There are also logic levels which pass through the Central Control 12 with the Central Control performing as the connecting ,"~ :

1 -3I~
.

block between the Processor 10 and I/O channel~. Pr~ority logic, 10 of FXG. lCIdetermines which of the I/O channels will be allowed access to the ~lain Memory lOm, should more than one channel need acce~s at the same time~
As seen n FIG. lC, there is included, as part o~
Central Control l2, a plug in translator which is capable of translating BCL (Burroughs Com~.on Language) data to or from EBCDIC (Extendsd Binary Coded Decirnal Interchange Code) as it goes to or comes from the Core Memory lOm. '~he I/O
Control units, 13 , 13b, FTG. lA~ request Central Control 1 tc use the translator, 12tl FIG. lC, or to bypass it. The translation takes place as d~ta is transferred bet~erl the I/O Control unit, such as 13 ~ and the Main Memory 10 .
Additional tirne is not required f'or I/O opera~ion even thou~h translation is necessary. The translator logic tran~lates incoming Burrough3 CorNnon Langua~ff ~BCL) da~a into EBCDIC ~E~tended Binary Code Decimal Interchange Code) data or the outgoîng EBCDIC data into Burroughs Common ~anguage (~CL). Those EBCDIC codes which are no-t assigned a BCL code, will cause to be generated a code for a BCL
symbol "~"~
The Central Con-Srol 12 functions as an interface between j ~ ~an I/O cha~nel and the Main Memory 10 during systel~ operatio as seen in FIGS. lB and lC. It determines the priority of memory accesses, should more tha~ one channel need access~
and it transla~e~ data coming to the I/O channelt as 100 om Memory 10m or ~rom the I/O channel to Memor~ The Central Control correlates various functions of the channels~
, ` . .
~he sequence o~ e~ents is init~ated ~y the Processor 10 ~hen an I/O channe1 i5 n~eded.
, ~' ' ' , ~
Z ~
,1 .

When the ps~ogram being performed has need of.a peripheral unit s~ch as 14 or 14b of FIG. lA, the Processor 10 execu-tes the "Initiate I/O Instruction". This inst~ction reads an I/O Descriptor from ~Iemory 10 and then sends the necessary information to the I/O channel, 100, thro~gh Central Control 12. This information contains the type of operation (OP code) and the variant informatiorl. The remaining portion of the I/O Descriptor including the beginning (A) and ending ~B) addresses~ is stored in Addre~ss Memory~ lOpam, FIG. lC, of the Processor lOp~ The cha~nel i~ sel~cted by the channel designate level (CDL) as seen in FIG. lB~ which line comes from the Processor lOp.
Once all the infoxmation is availa~le, the I/O cha~lel, 100~ is released by the s-tart channel bus (STCB), FIG. lBg to operate independently. When -the I/O channel has been rcleased, it operates as another processor and shares the Main Memory 10m with the main Processor lOp or other channels ~IG~ lC~
I~ the operation being performed in~olves an '~input -type"
peripheral unit lL~i such as a card reader, the data is received by the 1/0 channel 100 seen in FIG. lCI and the data is stored in a b~fer C within the I/O channel lOO.
The I~ channel then requests access t~ Main Memory 10m via ~entral Control 12. This request is processed by the -l :
' ~.5 priority logic 10 c which contro}s other re~ests at the same time . Once access to Memory has been gran ted to the channel 5 the information is transf0rred to Memory lOm. The in~ormation may o:r may not be translated depending upon the I/O Descriptor. ~he information is tnen wr;tten ~nto the :
.~ .
'' ' ' .

l - 33 ~

Main Me~lory 10m at the locatioll specifled by the beglnning ~A) and endi.ng (B) addresses in the ~ddress ~emory, 10 If it is desired, at so~e ~oint, for data or information to be transferred out to a peripheral termin.al unit, this is called an Itoutpllt'' operation, FIG. lD. I~ an "output"
~peration is bein~ perfol~ed, a similar sequence of e~ents occurs as before, except t~at data goes frorn the Main Memory 10~ to an I/0 channel such as 102 of FIG. lD. Then when a periphera]. un.it as, for example, a prin~er 14 needs data, the memory access re~lest is made to the Central Control 12 via the I/0 channel, 102. ~len pri.ority is granted to the channel, the da.ta i9 read from ~lain ~lemory 10m from the addres3 specified by the beginning and ending addresses located in the Address Memory lOp,~m; this data is then transfer~ed to the I/0 channel buffer C~ through the translator 12t (or bypassed around th~ translator depending upon the I10 Descriptor). As seen i.n ~IG. lD, the data is then transferred to the peripheral unit, such as 14 .
Ag seen in FIG. lE the Centrat Control 12 pro~ides an , . .
interface to/from the I/0 cha~lelsl the Processor 10 , and t~e ~ore Me~or~ lOm. Control information from the Processor 10 ~s sent to the Ce~tra~ Control 12, where it is distributed P
to each I/0 channel as 100, 101, etc~ The Central Control ~' 12 han~les all of the Core Memory requests m~de by the I/0 Control ~nits in this first T/0 ~ubsyste~. Data from each I/0 channel, which is to be written into Core Memory 10 is placed on the Memory Write ~us by the Central Control 12, ~nd data ~hich is to be read ~rom the Core Memory 10~ is placad : ~ .
on~he Core Memory Read Bus ~nd d.istributed to each 1-/0 ,'. 30 channel.

' : .
~ . - 3~

st'7'~L~

~ hen a re~uest is made b~ an I~O ¢hannel unàt ~ the Central Control 12 will o~tain the Co~e Memox~ address ~rom the Addres~ Memor~ location reserved or that speci~ic I~O
channel. This address ii used to access Main Memory 10m and the memory cycle is then initiated. The memory cycle could be either a "Read" or "~xite" depending on the specific I~O
operation. - -hen the Processor lOp reque~ts a memory access, the , - memory address in~olved is obtained from the Address Memory .. . .
` 10 lOpam located in the Processor lOp. This address is used to access Main Memox~ lOm, and the memory cycle Ceither a read or a writa~ is initiated.
Since only a ~iingle memory access can be made at a gi~en moment, multiple memory requests must be handled ~;~ indivldually, and this handling is accomplished automati-; ~ cally via Pri~rity Control 10pc GFIG. lC, lD~ ~y Central ;- ~ Control 12, as previously discussed... Each-Central Control 12 contains "priority logic" lOpc which is established or changed by a ~ield~engineerin~ adjus~mant. As I/O channels are added to the Central Control 12, they are also added to the priority network. Tha Processor lOp, in this case, has a lo~er priority than a Central Control 12~ The highest priority request is granted fir~it, and as soon :as it is complèted, the next highest request is automatically ~rant-ed. This process is repeated until all o~ the multiple .
re~ues~s axe handled. The requests are alti~rnately granted to each~Cen~ral C~ntrol unit Cwhen multiple Central Controls are used) depending on Which control was~granted~he last request. I~ a C2ntxal Control does no~ want the acc~ss, ; ~ 30 then it is granted to the Proce~sor lOp~
.
~ ` ~3i5 :
; 1 J
. `

During the course o~ a data transfer operation within the first categor~ Subsyste, the I~OC (Input/Output Controller~ may perform several functions depending on the .. OP.code, the variants, and the type of peripheral device~
T~picall~, the I/O Controls have the ability to buffer only ` one byte or at most one word. T.hus, when the data buffer : of a control is loaded, the I/O Controller or I/O Channel . Unit 100, 101, 102, must request a memory access; therefore, the rate at which data is transferred to or transferred from .-- 10 the System is controlled primarily by the speed rate at which 7 ' the peripheral device can read or write. l'he second I/O
Subsystem using Base Modules with Line Control Processors does ~; ~ not have this speed limitation.
When the I/O Controller requests a memory access, it i is, in effect, asking the Processor to perform a series of . . , - . .
operations; these operations include: ~a) the transfer of ~he data field address from the processor's I/O channel . address ~emory to the local address register; (b) the initiation of a memory cycle; (c) and the restoration of the 20 data field address to the address memory of the channel.
The I/O Controller also indicates to the Processor the ~amount by which the address must be incremented so as to ... . ~ p~int at the next data field location. Upon completion of the operation, the r/o Controller builds a Result Descriptor ~RjD3 indicative of how the operation was effectuated, then ~the I/OC stores the Result Descriptor in a reserved memory : location, after which it sets the Processor Interrupt flip-: ~lop.
In the second category of controlling I/O activity, use . 30 is made of an Input/Output Txanslator (IOT) interface unit which is located in the central processor 10. The IOT
interfaces with a ~3 group of Line Control Processor3 (LCP) which are ~ns-talled in ~CP Base Mdules. Up to eight LCP's may `be housed in an LCP Base ~Iodula. The Base Module for the LCP I 5 holds up to as ~uch as eight LCP's. The LCP i~ an intelligent interface unit which establi.shes a bu~fered data-transfer path between the p~ripheral device invol~ed and the main system of Processor and Memory. This communicatioIl path is established by the LCP upon receipt of a Comma~d Descriptor (C/D) from the IOT.
which has translated an original I/O Descriptor into a ~
~pecialized Co~land Descriptor for the LCP.
Since each LCP has a large "data buffer" of, typically, . 256 words, then data can be transferrecI to and fro~ a spacific peripheral device at the comparati~ely low rate of the device; however, when the data buffer is full, data c~n : 15 be transferred to t~e ~Iain System at the highes-t rate allowed by the ~emo~y speed of the ~Iain ~Iemory, which is at a fast rate.
; The LCP ~ase Module, which houses up to eight LCP's, operates in conjunction with the IOT to establish connection to and to initiate operation of a yarticular LCP. The ~CP
Base ~Iodule also s~pplies the timing signals, the maintenance logic, the power supply and cooling which is supportive of each ~roup of individual LCP's. - :
. The IQT i3 that portion of the central processing unit : !
which, upon r~ceip-t ofan I/O Descriptor, works iri conjunction wi~h the LCP ~ase Module to establish connection to a .~ particular ~GP in the channel specified by the Ini.tiate I/O
Instruction. The IOT translates the I/O Descriptor to a ,` ~ fo ~ ~Cor~nand~Descxiptor) recog}lLizable to the LCP, and, :` when conn~ction i5 . , .
~ , . . ..
; - , ' ' .
~ 7 ~

f ~ ,~
. ~ .
`~ '`
astablished, passes the translated descriptor to the LCP, after wh~ch data transm~ss-ion ma~ beg~n. During the time that the data is being transferred between the LCP and the Ma~n System, ~hen the IOT, upon demand from the LCP, requests memory accesses, addresses memory, t~en modi~ies and compares the data addresses. Fuxther, the IOT ccntrols the routin~
of data between the selected ~CP and the Main System, and it performs translations ~ASCII~EBCDIC) of the data if so required. Upon completion of an operation, the IOT accepts R/D (Result Descriptor~ information from the LCP, and then stores the Result Descriptor in a predetermined location.
The LCP system configuration allows up to 68 I/O
channels. In the I/O Control Subsystem there may be two CC's ~Central Controls~ with eight I/O Controllers each for a , .
total of only 16 channels.
In the LCP subsystem however, there may exist up to eight LCP Base Modules per single IOT. Each Base Module may service and carrv up to eight LCP's. Thus, one IOT may serve as many as 64 LCP's. A Multiplex Adapter may be used to provide the effect of l'two" IOTs connected to common LCP Base Modules.
This configuration may be used to improve I/O band pass to the Main Memory.
The entire I/O System has ~hannel addresses which must be unique in themselves. Access to Main Memory is shared ~ .
by the IOT, the Central Control and also ~he Processor.
In FIG. lA there is seen an overall system diagram showing the dual categories of I/O Subsystems. The first I/O Subsystem is made of Central Control 12 which supports I/O Controls 13a~and 13~ w~ich connect respectively to peripheral devices 14a and 14b. This first I/O Subsystem tusing Central Control) is connectecl to the Main Syst~m lQ
by means o~ interconnecting bus 11. ~-i Q

` The Ma~n S~tem 10 ~s shown comprising a Main Memor~ 10m, the Central Processor lOp, the Memory Control 10c, and the .. Input-Output Translator lOt.~ A PCC (Peripheral Control Cabînet~ interface 10~ connects via bus 5 to a Peripheral Control Cabinet 6 wh~ch houses the Central Control and the ; I/O Control units of the first I~O Subsystem.
The Input-Output Translator 10t Of the Main System, FIG. lA, forms a second I/O Subsystem through the use of cabinets shown as LCP cabinet numbers 0, 1, 2, designated as 4 ~ .
:: 10 160, 161, 162. Each of the L~P cabinets supports three LCP
i Base Modules, 0-8; for example, base cabinet 160 carries Base Modules 200, 201, 202; while LCP cabinet 161 supports LCP Base Modules 203, 204, and 205; likewise, LCP cabinet 162 supports LCP Base Module 206 and 207. Each of the individual LCP Base Modules is connected to the IOT IOt by ; means of message Ievel interface cables (MLI) 15, each of ~ which is made up of 25 lines.
- Referring to FIG. 2~ a typical LCP Base Module 20 is shown in greater detail. ~he Base Module 200 is composed of eight Line Cont.rol Processors (~CP's) 2000 through 20o7, in addition to a common Distribution Card 200d~ a common Mainten-ance Card 200m and a common Termination Card 200to The Distri-~ , bution Card 200d connects to one set of the message level .;; in~erface cables 15 which connect to the IOT 10t ~also see : FTG. 5E).
Each individual Line Control Processor is seen connected by output lines to a particular peripheral device, wherein, as seen in PIGo 2 the LCP's 2000 through 20o7 respectively connect to peripheral devices 50,51,52,53, 54, 55, S6, 57.

3~

~ 3g ~

, Wh~le`each LCP of the`Base Module may be slightly different ~n certa~n ~spects in order to accon~odate the idiosyncrasies of each partic`ular peripheral device which the LCP handles, eac~ LCP is of ~asically the same design and functional capability. With reference to FIG. 2, a typical example of each LCP is s~en in the LCP 20o6 which is seen having a System Interface ~lsi~ a Device Interface 22di and having a Word Buffer 2506 which is typically capable of holding 256 words.
Referring to FIG. 3 there is seen a m3re detailed block diagram of the Main System as it relates to the I/O LCP
Subsystems. The Main System 10 has a Main Memory 10m in which there is a reserve portion 10mi for I/O Descriptors and another reserve section 10mr for Result Descriptors.
` In addition ~he Main Memory 10m has another reserve portion 10nC for storage of channel numbers. The I/0 Descriptors, Result Descriptors, and Channel Numhers are information used by the System for control and for ecognition of the status of operations. These will be described in detail hereinafter.
The Processor 10p has a local register lCpr which is useful for storing information for the IOT. The Input-.
i Output Translator 10t holds a channel scratchpad memo~y lOpS.
The local register 10pr of the Processor 10p is used ;~ ` for storing the beginning tA) and the ending (~) addresses :: I ' `
of the appropriate I/O Descriptor. tIn the case of the fixst I/O Subsystem using a Central Control, FIG. lA, the I/O C
causes these address to be transferred into a temporary storage location called channel scratchpad memory or ~hannel address memory.~ In the case of the second subsystem using the IOT, the IOT
~ ~ ' ..
- ~ 0 - , - - -! ' accesses the A and B addresses directly from ~he memox~
address lines leading ~o the local register 10pr f the Processore The channel scratchpad memory 10ps :for all 64 LCP's.is contained in the IOT. The channel scratchpad memor.ies will also contain the re~uired channel numbers.
- l~ith reference to FIG~ 4A and the transfer v~ infor~
mation as between the Main S~stem 10 and a typical ~P 2000, a brief ~ook at these in~ormatlon woxds and their functions - ~ill indicate the nature o~ the operatiny relationship : 10 Command Descriptox CFIG. 4A~: .
The Command Descriptor ~C~D~ is a mod:i~ied form of the ; I~O Descriptor. The I~O Descripto.r is the information re-siding in Main Memory 10mf FIG. 1, ~and specifically in 10 of FIG. 3) which pro~ides data and information as to the i t~pe of Input~Output operation to be accomplished. The modification o~ the T~O Desc~iptor is accomplished by the ¦ IOT 10t ~Input-Output Translator, ~'IG. l~ which receives ¦ ~he IfO Descriptor ~rom the System ~Iemory 10~, retai~s a portion of the instruction t and then transmits the applica-bl~ portion to the LCP 2000 as a Command Descriptor.
¦ The Command Descriptor is a 17-bit wo.rd, A, B, C, D,¦ CFXG. 4B) consisting of an OP code digit (A~, ~ariant.digi~s 1 (B~, 2 ~Cl, and 3 ~Dl, and a parity ~it. However, the : ~ LCP 200o makes use of only the OP code digit and ~ariant ;~ . digit 1 fox instructional pULpOSe~ . Variant di~its 2 and 3 are always e~ual to O. The OP code digit ~ defines t~e : : b~sic op~ration to be perfor~ed b~ the LCP 200o, and the ariant digit 1 ~B] spaci~i.es modi~icakions of the basic ~ t operation~ No memory addre~s informa~ion is sent to ~he LCP;

; ~ : ' ', .

:`~

the System Memox~ addxess ~unc~ions are accompl;shed ~y the IOT lOt. FIG. 4B contains the Command Descriptor codes for all operations that can be per~ormed b~ the LCP~ These operations include. ~rite, Read, Write Flip ~ead, Test, Test Enable, Conditional Canc~l, and Echo. These operations will be later described hereinafterO
Descri~tor Link (~IG. 4A):

.
~he Descriptor Link ~L~ consis~s of two 1~ bit inormation words accompanied by a longitudinal parity word ~PW). The Descriptor Link is exchanged bet~een the IOT lOt, (FIG. 1) and a hCP, as LCP 2000 at specific times during : ; communication between the two units. The content of the~

I Descriptor Link is shown in the following table. The data . bits which are not listed are.reserved for fu~ure use.

. TAB E~ Descriptor Link ~Also see FIG. 5D) . Data Bit Desi~nation .
A8 Inhibit Access to sys~em memory.
.
A2 ASCI~ Translation required.

. : C2 ~ase Module Address: 4 bit.
. . ~1 Base Module Addxess: 2 bit.
D8 Base Module Address: 1 bit o' D4 ~CP address~ 4 bit.
D2 LCP address- 2 bit.
- . ~1 LCP address: 1 bit.
:: .
. ~ : ~ Data ~Intelligence) (FIG. 4A) .
~ These are th bidirectional communication lines for .
transfer o~ data ~rom the Sy~tem 10 over to the LCP such as 2000 for eventual transfer to a peripheral u~it such as 50;or ~: oth2rwise for trans~er o data ~rom the peripheral unit 50 :, .
over to the,~.P 2000 and thence to the System 1.0 for storage . in ~ . .,~

' ' ~Xemory lOm. In E~IGSo 1 an~ 3, these cha~nel5 would be the message level interface (~ILI~ ~5. ~ata transmi.s.sio:n between the System 10 and the LCP 200 is in the form of words (Table II) except ~or certain trans~liss:ions ~hich ~re limited to a singte character OI` for transmis~ions ending in an odd number of characters. Each "da-ta wordl' is composed of two 7-bit ASCII characters ancl a single parity bit. Data bits A8 and C8 are not used, (Table II).
It should be noted in regard -to the Command Des~riptor9 that after receipt of a Command Descri.p-tor, but prior to execution of an operati.on, the LCP 20 0 recei~es the Descriptor Li~ from the IOT 10 and stores it ln the LCP bu~fer 2~
oo ~FIG. 2). ~en the LCP 20 discoImects from the System 10, then reconr~ects for ~urther communication, the Descriptor I.ink is r~turned to t:he IOT 10t to identi.fy the LCP and the : operatlon in progress.
Result D~5~EaC ~F~r ~ A~
: A Result Descrlptor is generated by the LCP ~000 and forwarded to the System 10, after the instruction contained in a Co~nand Descrip-tor (C/D) .is executed, or when an er.ror occur~ during receipt of a Conunand Descriptor or a DescriRtor Li~k~ The Result Descriptor is sent -to the System 10 by the LCP 9 in a 16-bit word format, with a parity bit FIG. 4C
~.
: show~ the 16-bit fo~nat for a Result ~esoriptor, wherei.n digits A~ 3, C, D wil~ each have 4-bits.

The Longitudinal Parity ~oxd (LPW) is a 16-bit word . representing the longit~dinal parity of each t~ansmission between the Sy~tem 10 and the LCP 2000. ~1 LPW is . , ' , . ' -:

~; ~

accumulated àn ~oth the IOT 10t and the LCP ~000 during a transfer o~ inormation ~etween the two units. ~n LPW
register is provi~ed in the LCP 200o wherein accumulation of the LPW by the LCP 2000 consists of applying each word being transferred to the input o~ the LP~ re~ister and per~orming a binary add operation wi~hout carry ~exclusive OR functlon~. Then at the end.of a data transfer, the exclusi~e OR ~unction is again parformed between LPW~s of the sending and the receiving unit. If no errors have occurred, both LPW's will be identical, and the resultant . value in the LPW register will be "all Ols".
. Input-Output Translator ~IOT) ~FIG. 5CI_ The IOT.10~ translates the system I/O Descriptoxs into the appropriate operational messages relevant to each LCP.
.In return the result messages from the ~CP in the ~orm of - - Result Descriptors are not translated by the IOT, but are :~- stored directly into Me~ory 10m at lOmr as transmitted by the LCPs. The IOT performs all the in~ormativn transfers : between the LCP's and the Main Memory-lOm necessary to suppoxt the input-output capability of the second I/O LCP
Subsystem.
¦ The I/O ~escriptors, which are sent to the IOT from Memory lOm, are shown in FIG. 5A. Section lA of this figure shows the descriptors used: by the IO~ to.generate command : messages C/M for the LCP. These can also be referred to as Command Descriptors CjD. 9ection lB indicates d scriptors ` used by the IOT. Operations 40 through ~8 are translated into LCP OP codes and sent to the hCP's in "message" ormat~
The ":L" digit~ in the variant ~ield carry in~o:rmation used in the variant digit~3 (B~ C, and D) of the descriptor.

. ~4-. J
,1 , information sent to the LCP's~ ~hc S-digit ~s used ~ the IOT as sho~n by the note of section lA of FIG. 5Ao Each operation shown in FIG. 5A has t~o ~P codes; the difference is in the number o~ addresses used by the LCP.
The first diglt o~ the OP code designates the n~ber of addresses req~ired. For example, a ~al-le of 4 designate3 two~addr0ss oper~tion (e~cept "test" which has none~; a value of 5 for the first digit o~ the OP code designates three address operation. The second digit o~ the OP code i~ mapped into the actual OP codes sent to the LCP's ~s the nAt~ di~
FIG. 5~ shows the dat,a ~ield boundaries of operations going in the for~rd direction and in the backward direction.
(Forward - System to l,CP).
~IG. 5A also shows the four ~ypes of standard operational messages used for controlling the LCP's: these are l. Read 2. Write 3. Test

4. Echo The specific descriptor ir. ormation is obtained in ths for~ of variants whic~ accompany these OE codes. "Read" and Write" requlre system memory access. All opera-tions which ~, do not transfer data are consid0red "Test". ~hus~ a 'tTest1l il 25 1~ de~ined ~ an operation w~ioh results in the IOT receiYing ~, result info~ation only. 'iEchol' i.9 a confid~nce test ~'~ operation which causes the TCp ~o accept a bu~fer load of information from the System 10 and then retur~ it to the , Syst3m lO -~or chec~-out~

i ~, .
~ 5 ~

3~
, .

All communicationsbetween the Main S~stem 10 and the LCP is over a standard message level inter~ace 15 ~MLI~.
This communication between the IOT and the ~arious.LCP's is acsompli~hed by a standard flow discipline which is common to all hCP's.
In FIG. 5C the IOT 10t receives I/O Descriptors from the Processor lOp. The IO~ th.en connècts via Distribution Unit 20O~ to the requested LCP channel and sends the trans-lated descriptor information ~Command Descriptor C/D) in a message forma~ which indicates the LCP~s task. The IOT then becomes LCP "status dri~en". This means that the IOT res-ponds to.th~ various LCP states ~including memory re~uire-ments) as indicated via the control lines between the ~CP
~ and the IOT FIG. 4A. The IOT manages the transfer of in-- ~ . foxmation between Main Memory and the LCP's. The Lrp~s mem-ory requirements drive the IOT for all data transfers except that of initiation.
. Eithex the IOT or the hCP can initiate a connection to .
: Main Memory 10m~ The IOT initiates a~Main Memory conne~-tion to an LCP (and its associated peripheral) by performing an . algorithm which is called a '~Poll Test". On the other hand, the LCP initiates a connection to IOT and Main ~emory by an algoxithm called a "Poll Re~uest"~ On~e the LCP is connected, : I it indlcates its ~tatus via the control lines of FIG. 4A. ~n ~' ~CP which is initiating a i'Poll Request" mu~t compete with ` the other ~CP'~ in the:system; a connection to Main Memory 10~ is granted on a;;priority basis which will be descxlbed he~-einafter. During an operation, the IOT 10t may disconn~
.. . .
~ : ect from one hCP in order to s~vice another ~CP.

: . -~6- .
l . , .
' ~

?~

The message tx~nsmissions bet~een the XOT and the LCP
inv~lve dat~ and control mess~ges which are transmitted : 16-bits at a time along wit~ a ve:rtical odd parity bit.
Following the last message~ a 16-]bit longitudinal odd parit~
~rd (LP~) is transmi~ted accompanied by a vertical odd parity bit. Paxity is checked by both the IOT and the LCP.
I a parity error is detected by the LCP, then the LCP
repoxts this in its result information transmission ~Result Descriptor~ and halts th~ operation. If the IOT detects a .
parit~ error, it is inserted in the ~CP Result-Des`criptor.
The Input-Outpu~ Translator 10t (IOT~ consists of four major ~unctional sections, each conce.rned with one particu-lar aspect o f input-output operation. These functional sec~
'I tions are shown in FIG. 5C. Further, the operating rela-.
~ ¦ tionships between the IOT and the Main System ~Processor and Main Memory) and a}so the hCP and the peripheral device, are ~ also shown.
':~ - -.
Reerring to FIG. ~C, the Input Output Translator 10t communicates with the Processor 10.and the Main Memory lO
Th~3 IOT lOt also communicates with a selected ~CP.as Line Control. Processor 2 000 and t~ peripheral aevice 50. A
~ . series o~ control lines in FIG. 5C are shown from the Pxo~
- cessor 10 to the Initiation Module 10ta, the Connection : Module 10~b, the ~ata Trans~er Module 10t~ and the Xeconn-i ection Module 10td.
Initiation Modulev .
The Initiation Module 10ta accepts the des~riptor ~ information~ including the addresses, rom the Processor 10, T and then translates the descrip-tor OP code and assembles -the : : 30 information into a ~orm usable by the ~CP ;20~o. The A and . the B addxesses of the d2scriptor are stored in the IOT
. ~7-.

~`
-- l ;
scratchpad memor~ lOp5, ~G. 3, which has locations xeserved ~or each designat~d channel; tha rest o~ the descriptor information is assembled in a register tas shown in FIG~SD) ~sr subsequent transmission to the LCP 20000 Once the information is assembled in this "descriptor information register'l and the addresses are stored, the~ the contents -~ of the first register are shi~*ed to a second identical reyister. In this mannerl the first register can be cleared and the Initiation Module 10ta is thereby freed to accept a . 10 s~cond descriptor.
: The infoxmation contained in the descriptor register . of FIG. 5D consists of a number of items: -i ~a~ LCP OP CODE : these are ~our mutually exclusi~e. I . .
. bits, which are translated by the IOT from the . I/O Descriptor OP code; they indicata to the LCP
. ~he.type of:opera~ion tha~:is t~ be.commenced.
b) LCP Variants these are three digits which are used to pass supplementary information to the LCP concerning the operation that is to be ' .
~ commenc~d~ .

: (c~ IOT Digit : this digit speciies i~ data transfers ~ : : ~ are to be inhibited and whether or not data is to :
: : be translated.:

~dj Backwards Flag : when on~ this 1ay bit indicates : , that a reverse operation i~ to occur.

e) ~CP Address : this is decoded from th2 "B~"

: ~ ~channel number3 of the processor Initiate I/O
, instruction; ~his fie~d contains three bits which ~4~-: ~ .
. . .
.
: 1 specify one of the ei~ht LClP Base ~odules, and the other tllree bits which are used in combination to select a particular LCP in the designated Base Moduls .
~f) C Address : this i9 a six~digit C-~ddr6ss field (file address) of the I/O Descriptor.
~he combination of the IOT digit, the backwards flagg and the LCP address constitute the ~escriptor Link ~D/L) which is used by the LCP to re-establish co~nection to the System ' following a previous disco~nection. ~hen the Proces~or signals the IOT that th~ entire I/O Descriptor ha3 been sent, the ICT di3conn~cts from the Processor~ and the Tnitiation Module lOta passes control to the Connectlon Module lO
c~ U ~
The Col~ect~on Module lOtb of FIGo ~C has the purpose of .
~stablishing a communication path between a dssignated LCP, ;such as lCP 2000 ~ and t'he Input-Output Translator lOt. The Connection Moduls lOt~ desodes the~channel numbe~ ~hich appears in the Processor Initiate Instruction, and, with the ~20 decodsd valus, selects a communication path to the LCP Base ~odule~such as 20 , ~IG. lA,in which the'desired ~CP is i: . o located. The~Co~lection Mo~ule lOtb then ssnds ths LCP
address~to the selected LCP ~a~e Modulet ànd then signals ;the~Base Module, such as 20 ~ to begin a "Poll Test", 25~ ~ ~
The "Pcll Test" is an algorithm u~ed ~ the LCP Bass Module~to establish connection ~etween the ~3ase Module and a partioular LCP; t~e Poll Test algorit}~ i3 a co~:nectio~
which is~ lnLtiated by the IOT (as coIltrasted with an , ,g , ~ .

algorithm called '!poll request~ which is a connection initiatec1 by the LCP)o Once the cor~ect.ion between the I,CP
Base Module and the s~ecific LCP is establishedl the Base . ~odule 9 such as 200 of FIGS. lA an~ 2 J becomes transparellt to data transfers between the LGP and the IOT. The "Poll Test" algorithm also checks for priority7 transmission errors, and busy conditionsl any one of which, if detected, could abort the connection attemptO
Xf the connection attempt is successful, the specific LCP remains connected to the IOT 10t until the connection is te.rminated by the IOT. The LCP Base Module t~ces no further role in the communications between the chosen LCP and the IOT o In t}le course o~ the attempted connection, cer-tain 15 . conditions may be detected which will stop or a~ort the -~onnection attempt 9 with the rcsult that the existing condition i.s reported in the IOT Resul.t/Descriptor. The follo~iin~ are the types of conditions detected and reported:
(a) The channel addressed does not containan LCP or the L~P in the channel is off line.
~b) The LCP in the particular channel addressed is "busy", (that is, the LCP status is not 2 or 3~ the use of ~status counts'7 will be described ~reinafter).
(c3 The port is busy, that is~ some other LCP in that Base Module is presently connected to the System lO~
~d~ The LCP address has i~ it a parity error.
~en the.IOT and Base Module Distribution Control means uses.the "Poll Test" for connection to a particular I.CP, then . , .
if the Poll Test.results ~1 . . .

~ 150 _ .

in connection to th~t hCR~ the IOT 10t will txansmi~ the Descriptox ~inkCD~L~ the hCP OP code and variants, and the C address to the LGP selected. l~fter recei~ing t~is in~ormation-, the LCP signals the IOT I0t that it is either going to disconnect, or that it is now prepared to begin to transer data. TypicalIy, a "Write" operation (data from Main Memory 10m to the peripheral device, such as peripheral - 50~ causes the LCP selected to request a "data transfer"; on the other hand a "Read" operation typically results in a disconnection.
If a data transfer is requested, the Connection Module ' 10tb passes control over to ~he Data Trans~er Module 10~C.
Z I~ the LCP 2000 disconnected, then communication between the LCP 2000 and the IOT 10~ is terminated until the LCP
re~uests-a re-establishment o communication via the Reconnection ~odule 10td.
Data Transfer Module:
. . . _ _ In FIG. 5C the Data ~rans~er Module 10tC is used by the IOT 10t to control and to direct the flow of data between a connected LCP 2000 and the Main Memory 10m. ~The LCP may be in a connected state as a direct result of the actions of the Connection ModuIe lOtbl or as a result of the actions ; ~ of the Reconnection Module 10~d; in eith2r case the operation o~ the Data Transfer Module 10tc, is the same. When control i~ passed over to the Data Txansfer Module 10tC, the A and B
;~ addresses of the descrip~or are retrie~ed from IOT scratchpad memoxy 10ps of FIG. 3I where they had been stored by either the Initiation ~odule 10ta, ox by the Data Trans~er Module 10tC of FIG. SC~ at the end of a prior data transfer ~ 30 ~ operation~
.
~, 51~

~1 __ ____ _ , ~ - .
3~ ~ 3 ~ ~

A memor~ access ~e~uest is m~de and the A ~ddress is trans-~erred ~rom the IOT 10t over to the Pxocesso~ memory address register lO pam in the Main System 10, FIG. 3.
Assuming that a "~ri~e~' operation is in progress, in FIG. 5C, the data ~rom the memory location specified by the A address is bussed via Bm to the IOT Data Transfer Module lOtc. ~nce in the module, the data is transiated ~if speci-fied by the de~criptor?, and used to generate longitudinal parity, and then is gated via bus Bg to the selected LCP such as LCP 2000, accompanied by a strobe pulse~ When the ~CP
2000 receives the data, it acknowledges the reception by re-turning a strobe pulse back to the IOT lOt.
While the data trans~er from Memory 10m over to the ~ hCP 2000 is occurring, the IOT 10~ increments the A address : :1 and compares it to the B ~ddress. As long as the A address :
is less than ~he B address, the reception Qf the acknowledged ; str~be pulse ~rom the LCP 2000 will cause another m~mory : access to be requested and will allow the data transfer . sequence to continue.
¦ 20 When the LCP buer, such as 2500, FIG.2, is fillea with data from the Memory lOm, the LCP signals the IO~ 10t that it is going to disconnect; the IOT 10t then restores the incremented A address to the IOT ~cratchpad memory lOpS, ¦ : FIGo 3, a~ter which it termi~ates the connection between the : IOT and the LCP . The LCP, such as LCP 2 000 ~ then begins . : data transmission via Bp with its peripheral device ~0; the: :. XOT 10.t is now ~ree ko establish connection to another LCP~
pon: transferri~g the contents of its data buffer 2~oo to the peripheral device 50, the LCP 200o requests a ~ ~ ~ 3 b :~: .

- 5~ .
~' , re-establ~shment o~ the data path to Ma~n Memo~ lOm. This ~e-estci~l~shment ~s handled b~ t~e LCP Base Module 200 and the IOT Reconnect~on Module ~td.
In order to increase ~he overall rate of input-output (I/O) activity, the IOT 10.t may contain, as an option, an IOT Multiplexor. This multiplexor would ~nab~e the IOT to service an LCP during those memory cycles which would other-, wise be lo~t while the IOT was busy with some non-memory function.

Reconnection Module:
, An LCP, such as 2000, after having been connected to ! the IOT 10t and receiving the Command Descriptor (C/D) and the Descriptor Link (D/L), then the LCP 2000 may disconnect from the system in order to communicate with its associated : peripheral device, such as device 50~ Now, if that LCP
subsequently requires access to Memory lOm/ it sends a : ............ request to the Base Module 200. An algorithm called the "Poll Request" is the method by which the LCP ~ase Module (~n response to the request of the LCP) attempts to connect the LCP ~ack to the IOT lOt. The base .Module Distribution Card contains hard wired logic to acco~lish this. The ; purpose of the Reconnection Module lOtd is to acknowledge the "Poll Request" and to re-establish a data path over to the IOT lOt-The Reconnection Module lOtd, duriny the reconnection attempt, and working with the Base Module, a~ 200, resolves any priority confilicts that may arise ~etween various ~: requesting LCPis. ~len priority is resolved the Reconnection , Module establishes the data path from the requesting LCP
over to the IOT 10t Mai~ Memory lOm.
Once the data path is re-established, the LCP returns ~ he Descr.iptor Link over to ~he IOT l.Ot. ~The Descriptor : ~ 53 Link was originally passed to the LCP 2000 dur:ing the original connection sequ~nce). The ~ase Module 200 takes no ~urther role in the LCP IOT communication- Following the trans:~er of the Descriptor Link9 the Reconnectiorl ~Iodule lO~d passes control to the Data Transfer Module lOtc.
The IOT 10t must ha~e t~e ability t~ accep-t, store and to modify data field addresses in order to transfer data to and from the correct memory locations. Because ~lain ~Iemory 10~ ~ay include up to two-million digits (addresses 0 to 1,999j99g)~ and because the ~arious input-~utput devices may address the Memory 10m directiy, then -the I/O descriptor data ~ield addresses must be seven digit~ long. An I/O
descriptor da-ta field address must be either MOD 2 or MOD 4 ~modulus is abbreviated to MOD~; no odd addresses are permitted.
lS Because odd addresses are ~ot allowed, the least significant blt of the least signi~'icant digit is not required.
~urthermore, since the most sig~ificant digit can be only a "1" or a ~10~l 3 only one bit is required for the digit position.
With thase facts, it is possible to constr~ct a seven digit address using 24-bits. The -format, for the I/O descriptor data field address is shown in the table Y below.
~BLE ~

G ~ E D C B A Digit Position ~it Value 8 ~ ~ +

, ~
~ .
- I/O Descrlptor Data ~ield ~ddress ; No-te. ~ indicates bi-t not ~sed; mu~t be 7;ero ' . . ..

- ~ 54 ~

3~

` In the ~ddxess, the digit G ma~ ~e a one or a æexo, digits s through ~ may be any decimal ~alue ~O through 9), and digit A may be an~ even.decimal value ~O through 8)o As was indicated in ~IG~ 3, the IOT 10t has a ~cratch-pad memory 10pS. This is shown in greater detail in FIG.5F.
The IO~ contains 256 words of scratchpad m~mory~ each word o~ which is ~4~bits long~ As seen in FIG. SF, the scratchpad memory is divided into five majox areas. The areas marked A
and B are used to store the begin ~A) and the end (B~
addresses o the memory data fiela; both o~ these addresses are 24-bit~ long. The areas marked EXRDW 1. and EXRDW 2 are used to store extended result descriptors wherei~ each of these words are 16-bits long. The area marked "temporary storage" is used to store 1ags indicative of errors detect-ed durlng IOT operatio~. When the Result Descriptor is as~e~bled, the inormation ~rom the temporary storaga area is added to any existing Result Descriptor information.
., ...
Each of the ~ive majo.r areas is subdivided into 64 individual locations, one for each channel. . . :
~ ~he scratchpad locations are addressed by a combination oP eight bits which represent the Base Modu}e number and the LCP number/ the end address ~lag ~ADDRESB), and the '~ : ' xtended result descriptor ~lag ~EXRDW 1~. The six least signi~icant bits of th~ scratchpad address CBase Module number and LCP number) are derived from tha BF portion of ~ .
: the Processor's Initiate Instruction ~BFA - base number, BFB - LCP number~ The E~RDW 1 ~ignal is generated by th~
;
: ' : IOT 10t whenever access is required to either the extended i Result Descxiptor word, or ~o the temporary ~storage area.
;.j 30 , . ~~5 ,.
'I
~r ADDI~SB is generated by the IOT whenev~r acce3s is required to a B address or to the second ext.ended Result Descriptor area.
` The memory elements o~ the scratch~ad lOp5 consist of 24 RAMs (256 x l), organized in a 64 x 4 x 2l~ array (64 : channels, 4 words per channel, 24-bits per word). As seen in FI~. ~G, the eight-bit address bus, Bad, goes to all RAMs, 600, 601 o~602~ in the array, as does the Write Enable line 68~ Each R~M has one data input line and one data output line; these individual data lines are combin.ed to m~e up the data input (RA~IIN) 70i and the data output (RAMOUT) 700 busses respecti~el~
When the scratchpad address is applied to the array, : and the "Write Enable" is made acti~e~ the data on the IOT
. address bus is written into the ~lsO In order to read from the scratchpad, the desired location must be specified with the scr~tchpad address and the "read enable'l must be maae : active. The equested da*a is then transferred from the scratchpad to the IOT address bus.
~0 Address Store:
During the e~ecution of an Initiate I/O Instruction, the Processor 10 assembles the beginn.ing ~A) and the erdin~
(B~ addresses of the data field The Processor then tra~sfers the complete A address ~rom the Processor register 10pr to the 2:5 IOT address bus At the proper point of the.IOT initiation sequencs, the IOT generates the appropriate sig~als, then gates the Base Module and the LCP address bits to the scratchpad 10 . Now, with the channel's scratchpad loca.tion .~, ' . .

~ 56 ~
, ~

:~$ ~

addressed and with the "Write Enable'~ active, the A-addxess can be written intG the scratchpad. Subsequently the Processor 10 places the end (B~ address on to the IOT
address bus and again -the I~T generates the proper control signals along with the Base Module and LCP address. This time, however, the IOT also ~enerates ADDRESB, -thus causing the address on the bus -to be written into the B address area o~ the scratchpad (FIG. 5F). The beginning and ending addresses of the data field have now bee~ stored ir. the channel's address memory scratchpad 10 . W~en tke data transfer operation begins, these scratchpad ~ocations ~ill be accessed by the Data Trans~er Module lOtc (FI~o 5G)-Msssa~ evel Interface:
As was pre~iously described in refererlce -to ~IG. 2, the ~CP Bas0 ~lodule 200 is typical of the other ~ase Modules in that each individual Base Module contains a Distribution Ca~d 200d which services up to eig~ht LCP's. In addition, e~ch LCP ~ase ~lodule has a ~aintenance Card such as 200m and a Termination Card 200t.
The Distribution Card for each LCP Base ~odule proYides an inter~ace between the LCP Base ~odule and the Input-,, Vutput Translator 10t f th~ Main Syste~ 10. As seen in EIG.
2, the message level interface 15 pro~ides a o~a~nel to the IOT 10t from each LCP Base Module by means of 25 lines. ~ 25 ~ These lines are sho~n in FIG~ 5E. ~he ~unctions of each of these indi~ldually identified lines are liste~ in table VI
herein ~elow-:
`'`: ~ '' ~, i, ' T ~ (Re er to FI
Name Description __ ADDSEL Address Select~ T~i5 si~lal, when acti~e 9 : indicates tha-t the IOT is connecta~ to, or is a-ttempting to connect to~ a specific LC~.
Once the connection is made, the LCP remalns oonnected until the IOT drops ADDSEL.
AG~SIO Access Granted or Strobe I/O. If` an LCP
is not connected, this signal indicates th~t 1~ the LCPs request for reconnection has been granted, and i.nitiates the "Poll Requestl' algori~hm~ If the LCP is co~lected, this ~ignal is the IOT's acknowledgement for information received~ or strobe for information , 1~ transmittedr : TRM~IC Te~inate or ~las-ter ClearO If no LCP's are oon~ected, this signal will cause all on-line LCP's to clear. If an LCP is connected, this -si~lal will te~minate the collnected ICP.
~O LCPSI LCP Strober I~ an LCP is co~lec~edl, thls signal is the LCP's acknowledgement for infoImation received, o~ -the strobe fo~
~ J
information transmitted. ~his signal is also ~tsed b~ the Distrib~ltion Card as an 25 :~ ac~nowledgemen-t during Poll Test and Poll equest.

`': ':
~: , : ~ ' , .
~, :
' Des~rlption E~STS Emergenc~ R~3ql1est or LCP Sta~u3 8.
Wh.en activated by an unconnected LCY, this signal ind.icates that the LCP requires ~ immediate access to the IOTo I~ activated - by a connected LCP, thi~ signal indi'cates that bit 8 of the LCP stat,us is set~
IP~ST4 Interrupt Request, Poll Test Parity Error, .~ or LCP Status 4. When activated by an unconnected LCP, this si~nal indicates that the LCP requires access to memor~J~ i.e., th~
LCP is requesting a reconnection. I.f : activated during a system-initiat0d c~nnectjor ~ sequence (Poll Te~t), this sigral lndicates : 15 that ~ parit~ error wa.s detected during the Poll Test. If ac-tlvated by a co~tected LGP, IP+ST4 indicates t~at bi* 4 of the LCP
status is set.
.
PB~ST2 Port Busy or LCP Status 2. ~hen detected durin~ a Poll I`est, thi.s si.gnal indicates ': ~ that the I.CP Base is "bu3y". If activated ~j :
by a connected ~CP, P~ST2 indic~tes that~
.~ : bit 2 of the LCP status i9 set.
CS~STl Channel Select or I,CP Statu~ lo ~hen ,, :
~:~: 25 : activated by`the IOT and trans~itted *o an :
~ CP Base, this si~tal indicates 77channel , .
selec-t", and~that a connectiorl or : recor~ection attem~t has ~e~n inltiat~d. If actîva~ed ~y a oon~ected LCP9 CS~STl indicates ,. . ~hat bi.t l of the LCP status :Ls set~

. , .: ~ 5g -.~; ~ , .

ame ~ on P~RI~Y Parity. This bidirec,tional line carrie.s the pro~er (odd) parity for the info~mation on ~he 16 ~ata linesO
D~TAxn Data Lines (x=A, B, C, or D; n=l~ 2, 4, or : 8~. ~n -the unconnected state, these 16 : bidirectional linas are used for addres3ing and priority resolution in coImection or reconnection attempts. In the connected state, these lines are u~ed for the transfer of da-ta bstween -the IOT and the LCP.

The message level interPace 15 (MlI) which co~sists o~
2$ signal lines connecting the Distrlhuti.on Card as 200d~ of a particular LCP Base Module a~ 200, to the IOT 10t provides ~assurance that the signal discipline~presented to the IOT is . a standard one rega~dless of -the vari.a~ions of logic and operation fo~und ln the different types of LCP~s. It will be :
~ noted that some o~ the MLI si~lal lines 15 shown in ~I~T~ 5E
.
are bidirectional, and are assigne~ multiple functions t depending on the source of' the signal and the state ~co~lected or disconnec-ted) o~ the LCP.
. .
.~he~Distribution Card 200d for a gi.ven L~P Base Module ; is u~ed to provide a part o~ the ~lessage Level Inter~ace between the IOT:and the indi~idual LCP's within the Base i: ~
Z5~ ~ Module. The Distribution Card alsa works in conJunotio~
I . ~
with the IOT Connection~Module lOtb to establish a data pat;h to a speclried:~LCP ~Poll Test~, and, upon request by an ~CY, works with the IOT Reconneotion Module lOtd to establ.ish a path from that partictllar ~CP to the IOT (Poll Request).
. , .
, o During the tir~e a parti.cular ~CP is connec ted ~ i t follo~
a standard communication procedure with the IOT. Although ~.he sequence of even ts -follo~lred in the coml3luIlication procedure may not be identical for all LCP ' s, the e~ents oocurring in any one point in the sequence will be identical.
'Ihe steps in the sequence, ~hich are numbered O through 15 are called "Status Cour.ts" and are transmitted to the IOT.
~he IOT examines the "Status Counts'l each time it receives a ~trobe pulse from the LCP and~ based upon that status courlt, talces appropriate action. More detail in the sequence and use Qf status counts will be provided hereinafter. FIG. 6A
is a diagram showing the varioLls status counts and the logic ; flow which they involve. Detai.led explanation of this logic and the status counts in~ol~ed will be ~rovided hereina~`ter.
LCP B ~ ' A loc,al co~nmon baclcpl~ne is provided in each of the I.CP
~ase Modllles 200, 201~ 202~ etcO Each backplane connects to all the eight :I,CP ' s in the Base ~Iodule . The backplane is oonst:ructed so that all signal lines are bussecl the length of -the backplane, thus malcing each line a~ailable to all I,CPs in that Base ~odule. From ths in:lividual positi4n ot' a single LCP~ thess backp~ane lines fall into t~o general t~pes~
(a3 those going to the Distribution Card and on to -the IOT;
and (b~ those going to the Maintenance ancl Termination Cards.
With the exception of the ~arious clock and voltage lines, those lines going to the Maintenance Card, ( such as for example, 200m of FIG. 2) are used for local or off-line maintenance filnc tions~

.

Of those li.nes which go to the Dlstribution Card, and on to the IOT, sorne, such as the data and the parity lines, must be gated to indiYidual LCPs. This gating is enabled only when the LCP is in the "connected" state; when the LCP
disconnects, the gating is disabled. The LCP is in a ~connected" state when the LCP CaIl transfer data between the IOT and itself. The "disconnected" state of an LCP is where the LCP is disconnected from the IOT, but is now able to trans~er data between itself and its peripheral unit.
In addition to the gated lines, there are some lines which are dedicated to each indlvidual.LCP, for e~ample, the line which goes from the Distribution Card to only one LCP.
Those lines, which require no gating, are used for signals ~ such as the LCP request for reconnection or the LCP add.ress ; ~ 15 lines.
During -the ti.me an LCP is co~nected to the XOT, that LCP has the exclusive access to the Base Module Backplane.
It is during this "connected" tirne tha~ the IOT LCP data transfer occurs. Upoll cessa-tion of the data transfers, the LCP discor~ects from both the IOT and the Base ~lodule Backplane, thus freeing them for use b~ other L~P's in tha ~ system. Once disconnected, the ~CP is fre0 to co~unicate~
; via the ~rontplane, ~lth its associated peripheral devioe 9 such as de~ice 50. When a disconnected LC~ requi~es that t~e connection to the IOT be re-established, that LCP sends a request signalj via one of i-ts dedicated backplane lines, to the Distributio.~ Card, such as ~od. Reception of the L~P request cau~es the Distribution Card to begln the "Poll ~i ~equest'l algorithm and to initiate the IOT Reconnection `: 1 3~ Module, lOtd, ~IG. 5C.

~2 -.

Line CoI1t r:
An ~CP9 Line~Control Processor, is a de~ice which is used as an interface unit between a sc.ecific peripheral ~evice and the Main System. The I.CPs are made in a variety of types~ each clesigned to operate ~i.th a specific type o~
peripheral device. Since peripheral d'evices are different in their operational charac-teristics, the ~P is de~isad to handle, control and be partlcularly adaptab].e to :its own specific peripheral device. However~ there are certain general characteristics of the LCP interface unit whiGh establish a common char~cteristic for all LCPs. ~asically, the c?mmon characteristics of each LCP irlvol~e:.~he ability to transform serial data to parallel data or to transform parallel data to serial data; to transform format from character-to-word format~ or to transforrn from ~ord-to character format; to recognize and taXe appropriate action in.response to certain s-tandard control characters or signals~
.~ A generalized block diagram o~ a Line Control Proces.sor is shown in FIG. 6B, WhlCh also indicates the relationsh.i.p to Di~tri'bution Carc1 Unit 200d and IOT ]t~ If 1;he LCP is '; assumed to be i.n the "colunectecl" siate, anc1 that ~ "write~' ~ ~ operation has been initiated, then da-ta from the IOT 10t entsrs t~e L~P $hrough the backplane receivers 23 . rhen the Multiplexor 24 l i3 used to select the "data source" for the ~ ~ 25 operation, which in this case is the IOT lOto '~ The output o~ Multiplexor 24Xl i5 bussed to both the LP~ :(longi-tuc1inal parity word~ circuitry 24 and also t~ the Multiplexor Z4x~ which gates the data from ~lultiplexor 24 ,~, .

~ 3 ~

into the data buffer 2500. ~he LCP contim~es to recei~e data from the IOT 10t ~ntil the data buf~er 25 is filled.
In the period that the LCP is receiving data~ the LPW
circuitry 24 is generatin.g the LPW s~m; then at the end of the transmission, the IOT 10t sends a longitudinal parity word ~LPW~ which, if there were no errors in the transmission, clears the IPW circuitry 24w. If the circuitry ~4~ does not clear, then an error is indicated.
When the data buffer 250 is filled, the LCP disconnects from the Main System (IOT) by disabling its backplane transmitter dri~ers 23~ and backplane receivers 23r; ~he LCP
. then establishes a data path to the peripheral device, such as 50, by enabling its frontplane transmitter dri~ers 28X ancl frontplane recelvers 28r Once this path i3 established, the LGP uses ~ult.iplexor 27X to select data (translated or untranslated~ from ~he data bu~fer 2500 to be transmitted to the periph~ral device 50. ~le transmissio~ continues until . the data buffer 25 is empty, at which time the LCP requests a "reconnection" (to the IOT), either to store a Result 20 Descriptor or to request more data.
If a "read" operation is iIl progre~s ancl the LCP is ~` disconnected from the Main System (IOT), data from the . .
peripheral device 50 enters the LCP via the frontplane .
recPiver 2~r. The output of the receiver 28r is bussed to ~ultiplexor 24X1 9 ~hic~ now selects the peripheral device 50 tthrough ~rontplane reGeiYer 2gr) as the "data source". ~he output of M~ltipl~xor 24 1 bypasses the LPW circuitry 24 , ~ ~ and ~oes on to Multiplex~r Z4~, which selects Multiplexor ; 24X~ as the input to the data buf~er ~50~0 ~len the data ~ 4~3~

buff`er ~50oiS filled~ the frontplane recei.vers ~8r and the ~rontplane drivers 28X are disabled, t~en the ICP reconnects to the IOT lOt, and the backplane r0cei~ers 23r and backplane drivers Z3 are enabled.
~c l~le LCP now begins transmission (to the Main Systern lO) of the data from the data buffer 2500 ~ thro~gh the Multiple~or 27X and driver 23x, ove~ to the IOT lOt. Durin~ this transmission3 the output of Multiplexor 27~ also goes through .- the Multiplexor 24Xl over to the LPW circuit 24 . When the data b~ffer 2500becomes emptled, the LCP sends a si~nal to the IOT 10t indicating that the longitudinal parity word, LPW, is coming~ after which it then gates the final LPW
~um through Multiplexor 2~x and dri~er 23X over to the IOT 10t Af`ter the transmission of the longitudi.naL parity word ~ 15 (LPW~, the LCP may either disconnect from the Main~System ; (IOT) in order to receive additional data from t~e peripheral device 50, or, if there is no further data, the LCP ~ay store ~a Re~ult Descriptor and go on to an "id~.e" state.
: In the above described operations? the informational zo data could ha~e been tran~ferred between the LCP and the peripheral de~ice in the form of bits 7 characters, or woI~ds, ~` depending on the type of peripheral de~ice in~olved. The ~ method o~ data transmission is typically co~ltrolled br the , ~
type of perlpheral device used.
25 : : Typically, the informational d~ta is transferred between the ~CP~and~ the IOT 10t a~ "wordsl', with some in~tances v character transfersg as for example, the firs-t or the last ~ ~ ~ character o~a tra.nsmission. The~e data tran~fers bet~een :~s~ -the~IOT lOt and the LCP of FT~. 6B are controlled by the :2 ~ , ', ~ 5 -, ~

e~change o~ strobe pulses, and the reco~niti~n by the IOT 10t of the LCP "status counts", to be described il~reinafter.
As pr~iously introduced in cc~nnection with ~lG. ~A~
the status count ofan L5P provides st;andardized info~ation which is transmitbed to the IOT lGt and which per~its the IOT
to take the next appropriate action based on the status ecunt information~
Durin~ the time an LCP is t'connected'1 to the Main System, it follows a standard communica-tion procedure with the IOT lOt. Even thou~h the sequence of events followed in the eommunication procedures may not be identical for all L~Ps, the particular events ~hich occur at any one point in the sequence of communication procedure are all similar.
The ~teps in the communication sequence, n~bered Q through g 15~ a~e called ~status ceunts" and designated "STC". These status counts are transmitted to the IOT lO~ which examines the status eount ~STC~ each ti~le it receives a strobe pulse from the LCP~ and, based upon that status count~ the IOT
ean take appropriate action.
Refer~ing to ~IG. 6A and the following table, it will be seen that each status count has ~ particular function and ~; further~ depending on the t~pe of LCP and ~escriptor ; in~olved, the status count will have different exits. The -following table VII briefl~ clescribes the ~arious LCP
~25 5 tatU9 C s:~l.lIlt ~3:
IA~LE VII
Status C~unt E~ Q~n STC~O Master Clear STCal . Disco~eet. The LCP is commwnic~ting :
with it's peripheral device.

~ 66 -;
TABLE 'VII
Status Coùnt Description STC=2 Not ~eady~ ~'he LC]P is idle. The peripheral device .is not ready. The LCP can recelve de,scriptor information ~rom the System~,.
STC-3 Ready. The LCP is idle. The peripheral device is readya The LCP can receive dsscriptor inormation from the System.
STC=4 Re,ad. Th~ LCP transmits data from its bu~:Eer to the System.
STCe5 Send Descr.iptor ~i~k. The ~CP send~ the Descriptor Link to the IOT in vrder to r~-establish connection.
STC-6 Receive Descriptor Link.: The LCP receives -¦ the Descriptor Link ~rom the XO~ during . the IOT 'ieonnec~iQn" sequence --.
STC--7 Result Descxip~or. l'he LCP trar~smits its .
Result Descriptor to the IOT.
2Q STC=8 Write. The l:CP recei~es data from the System.
¦ STC=9 Encoded Status. One charac~er transmitted;
,CP sets Dl bit ~FI,..4C Resu1~ Descriptor) a~ a flag to the IOT" The IOT decrements the address, by 2, STC--10 Write On~ More Word. The hCP data ~uffer .. :
- ~ can ~ld only one more word~, .
: STC=ll I/O Descriptox LPW. Th~ LCP receives :' .and checks the L,PW for the IfO ~escriptor : : 30 received in STC=2 or ',TC-3. ~he.I~O Descrlp-: : tor~ after~baing txans:lated by the IOT, then . becomes known ~s the Comrnand Descriptor.

q ~LE YII
~ 3~E~ n STC_12 ~reak. ~lere is no more data to be . trans~srred. I~le J.,PW is transmittecl and checked.
Sl`C-13 Break Enable. Data transfer has been halted; the LCP is requesting a return to STC=8 lWrite) or to STC=4 (Read).
STC-14 Character Transfer. m e last transmission consisted of a character instead of a word.
STC_15 Xesult Descriptor LPW. The LCP sends the LPW for the Result Descriptor to the IOT.
, :
Re~erring to FIG. 5C, the Processor 10 starts the chain of input-output operatio~s ~y the execution of' an Initiate : I/O Instruction. In this sit~ation, tha Processor passes certain:informatio~, including the channel number of the `~ desired LCP over to the IOT Initiati~n Moclule lOt~ o~ FIG. 5C.
20 ~ l`he channel number is deooded to dete~ni~e the B~se ~lodule ~, numb~r and the address of the LCP, which are then passed~c~er ~: ~ to the Connection Module lOtb~ ~le Connection MDCIU1e then ,: ~ :
selects the:p~oper ~CP ~ase Module and SendS ~ Sigr1a1 (channel select) to the ~ppropriate Distribution Card~ as - . :
~ 25 200d) for that ~ase Module, as ~00, requesting tha.t a :, connecti.cn attempt be made. The above described operation , ~' ; i9 calLed a l'Poll Te~t" and is ~ means f`or the Main 5rstem to seek oonnection to an L~P; it ig7 ~urt~er, ~ method b~
which the Distribution Card 20 d~ in response $o the connection ~j~ 3 re~uest, al~o aktempts to çonnect to a specific LCP.

- 6~ -, " ~

Following -the transmission o~ a "Channel Select", the IOT 10t sends the address of the desired LCP to the Distributlon Card in the selected ~ase Module. At the s~ne time7 the IOT sends "Address Selec~" to all Bas~ Modulas in 5 the system. The ~istribution Card that receives both the Address Select and Channel Select begins a "Poll Test" and responds *o the IOT withan "LCP Strobe"; the Distriblltion Cards that recei~ed the,Address Select only, consider it as a "husy" signal, and they are inhibited from com~mication 10 with the IOT. When the :IOT 10t reoei~e,s the L~P Strobe, it drops the Channel Select.
Whan the Distribution Card receives an "Address Select"
and 1'Channel Select", a signal is generated which enables the LCP addrcss to be plaeed into an LCP address register in 15 the ~istribution Card. I~e BCD (B~nary Coded Dec~mal) output ~, of the LCP address register is decocled to enable one of eight lines. Each line represents one LCP in the Base ~od~lle.
When an l,CP detect.s that its address line is active, then that LCP responds to the Distribution ~ard ~,ith the 91g 20 LCPCON meaning "LZP connected". When thi 5 connec~ed ,~ signal is received in the Distribution CardJ a cor~ect ~
, flop ~CONF) is set. Then dependlng on the state of the I/O
`~ send line (ICSND/ ~IG 6C~ from the con~ected LCP, this wlll I

cause an activation of control lines for either receiving ~!
~, 25 data or sending data as betw~en the LCP and the IOT
IG. 6C).
If a Listribution Gard detects the absence of Cha~nel ~, ~ Select~ responds to the IOT with the LCP 7 5 s-tatus !
i ', ' :
~ ~ accompanied b~ a strobe. The L~P is now cor~ec~ed to the , 9 _ .
~ I

IOT and remain~ cc,nnected until the IOT drops Addrsss Select;
the Distribution Card takes no ~urther part i~ the IOT-LCP
comm~nications.
The above e~ent~ show the steps leadi.ng to a successful ~connection" attempt; howe~er, the co~nection attem~t could ha~e failed due to one of the following causes:
~a) there was no LCP at the location addressed or the LCP at the address loca-tion was off-line;
~b~ the LCP was busy, that is the LCP status count was ; lO not O or 2 or 3;
~c) the port was busy, that is, a ~econd Distribution Card in the Base ~lodule waY b~lsy;
(d) a parity error was detected in the address.
; The detection of any of these errors ~ould cause the connection attempt to be abortecl and a Resu~t Descriptor indicative of the type of failure to be. written ~nd sent to the ~ain Syste~ in lOmr of Memory 10m (FIG. 3).
In subsequent discu~sionsg reference may occasionally be made to specific flip~flops and sig-nal levels which are not specifically shown within tlle block diagramsO Since -the design and use o.~ such element3 ar~ well l~lo~, it is ~onsiderecl to be redundant and overcomplex to show:all such elements.
. .
: ~ Poll Req~_st:
An ~CP, after ha~in~ been co~ected to the IOT lOt and . reoeivin~ the Co~and Descriptor and the Descriptor Link~
: .
may "disco~nect" ~rom the Main Syste~ 10 in order to co~nunicate with its assocLated pe~lpherRl device, such as 50. I~ that LCP subsequently requires access to Memory 10~l9 , ~ ~
~' .
~'`, .
~ 7 ~

~ ! ~

~c -it sends a request CLCPXQ) over to the Distri~ution Card. The "Poll Re~uest" ~s the method by ~ich the Distribution Card;
in response to t~e LCP's request, attempts to reconnect the LCP to the IOT. A number of events occur durin~ a "Poll Request" operation.
If several LCPs within the ~ase Module 20O simultaneously request-access, the Distribution Card 20Od determines which one of them is to gain access by checking their priority levels;
. ~ thus, the requesting LCP which has the highest priority level~
10 (this priority selected at installation time) is given access - , to the Distribution Card. ~his,priority level is called "Base Priority" as it involves which LCP has what level of priority as among the eight LCPs residing in that particular Base Mocule.
~ ! Once the "~ase Priority" is resolved, the Distribution : ~ Card assigns a "Global Priority" (which has also been assigned and selected at installation time) to the requesting LCP.
The "Global Priority" establishes the priority rank betweer different Base Modules in the overall system rather than just 20 the prior.ity rank of LCPs in one single Base Module.
The Distribution Card 20Od contains a series of pins or socket-type connections which are connected to each individual ; i LCP~ These pi.n-socket connections can be jumpered (by a field engineer) to a priority encoder which assigns an internal base priority num~er from zero (low) to seven thighest) to each LCP, Thus; i~ several LCP'.s ln the same Base Module request connection concurrently, then the Distribution Card control j means wi].l put through the LCP with the hig~hesk prioxity~
j Another set o~ pin-sockets on the Distribution Card are :' ` I
connected to each LCPo These are "jumpered" or "strapped"
by a field engineer so that each LCP is given a "global" or external priority number to permit the Input~Output Translator interface o~ the Main S~stem to select amor~gst LC~'s which reside in d~fferent Base Modules of t~e system. Thus, when i the "global" px~or~t~ number is recei~ed b~ ~te IOT, and there are concurrent requests fromt ~ther LCP's in o~ter Base Modules, the IOT wîll select the LCP with the highest global priority numher, but thîs occurs only after internal base priority has been resolved by ~he Distribution Card.
, Those Distribution Cards receiving requests rom their associated LCPs, each send an "Interrupt Signal" (IP+ST4) ;

over to the IOT 10t. (See message level interface FIGo 5E
~ and Table VI). When the IOT 10t detect.s the signal IP+ST4, ,, I it begins the "reconnection" sequence and sends a signal (Access Granted) to all the Base Modules in the system. The "Access Granted" signal causes those Distribution Cards t~at ~; , sent t~e IP-~ST4 to ~he IOT 10~ to begin ~heir individual "Poll Request" algorithms.
~, . .. . .
. . In response to the "Access Granted" signal, the request-. ing Distribution Cards send their individual Global ~riorities . . , over to ,~,,he IOT lOt. The IOT compares the Global . . .
.. . .. . . .. .. ... .. . . .

', , ~,, .

.i. .
', ` . .
;~ ' ~ :-: ~ . .. .. .. .
.
. - ~ , . . .
: . . :
~ : .: . . ..
: . : - . . ~. :
.

. . . -, , . . . . .. . . .
.. .. : . . - .. . - . . ~:
, ~riorities o~ the re~uestin~ Distxibution Caxds ~that is, sends the Channel Select signal over to the xequesting Distribution Card -~hich has,the highest Global Priority one clock~time later~ and the IOT sends an Address Select signal to all Distributio~ Cards in the system. The Distribution Card that recei~es both the "Channel Select`' and the "Address ` ; Select" responds to the IOT with the LCP S-tro~e, then sets its LCP Address flip-~lop, thus dri~ing the specific address line of the requesting LCP. When the LCP,detects that its own address line ls active, it then responds to the Distribution Card with the LCP connected signal ~LCPCON~.
, Upon receipt of the LCP Strobe, the IOT 10t drops "~ccess Granted" signal and the "Channel Select" signal; and I when the Distribution Card detects the absence o~ the "Access `` ¦ Grante~" and the "Channel Select" and detects the presence ., I . , .
of ~CPCO~, it then assumes a connection to ba completed and xesponds to -the IOT with an ~CP Strobe, accompanied by the , .. ,~
LCP Status Count and t~e Descriptor Link.
. :
The Poll Request is now complete; the Distributivn Card takes no further part in the LCP-IOT communication. The LCP
and the IOT csntinu~ with the ~econnection sequence until ~, ¦ the LCP is connected, after which control is passed to the . ~ .
; ~ IOT Data Trans~er Module 10t~, FIGo 5C. The LCP remains connected until the time when the IQT drops its "Address Select" signal.
^
Error Checks:
Each transmission ~et~een the IOT and a paxticular LCP
.~
is checked ?fOr errors. The error checking methods used are , ~a~ vertical parity checking on each word transmitted, and ~ 3G ~b) longitudinal parity checking on each block,transmitted.
:

.
;

~l ;

:j ~
(a~ ~ertLoal ~arity:
In "Read" opexations, the LCP sends ino~mation to the IOT 10t on 16 message le~el interface ~M~I) data lines, (FIG. SE) accompanied by the ~arity bit on the MLI parity line, FIG. 5E~ The data and parity lines go to a parity generator~checlcer on an IOT base driver cardO Xn "Read"
- operations, the pari~y generator checker is usea to ~ount the number of l-bits on the MLI data and parity lines. If ` the total number o~ l-bits ~including tha ~arity bit~ i5odd, then parity is correct and a signal term ~PAROK, FIG~
6D) ~rom parity-generator A8 is generated~ I~ the total number of one bits is e~en, then.the PAROK si~nal is not generated; the absence of PAROK at the time that data is received, causes the IGT to set a vertical parity error ~lip~lop ~P~RF~. ' Similarly, in "Write" operatlons the~16 data lines , from the Main System 10 are bussed to a parity generator~
checker on the IOT bas~ driver card. The data on the 16 lines is examined and if an even numb~,r of l-bits is de-, tected, the term PARGEN is generated~ This PARGEN signal is then used to force a "1" bit onto the message level inter-~ace parity line ko accompany the data to the LCP. On the :
LCP Base Distribution Card, the state o~ the parity bit - ~ controls the parity generator-checker circuit. The parity generator-checker circuit examines the states of the 16 data lines and generates PAROK if the total number of l-bits, .
, ~ including parity, i8 odd~
' tbj _ ngikudinal Parity Checking:
,i Longitudinal parity checking is an error detection method in which a check woxd generated by a sending unit i5 :~ ~ , , . ' ' ' ' : _ .
.

compared to a check ~ord ganerated in the 5am0 m~nner by a receiYing unit. These check words a~e gener~ted by treating each word in the transmission as a 16-bit number, then - .performing an exclusi~e OR operation (binary addition without carry) of each word in the transmis~ion. At the end of the tran~mis~ion, the s2nding or transmitting de~ice sends the check word it ha9 assembled over to the receiving de~ice.
If there have been ~o errors in ~he transmission, the addition o~ the check word ~rom the transmitting de~Lce to the check wor~ in the receiving device results in a sum o~ ~O". Thus, if the sum is not "O", a longitudinal parity error flip-flop is flagged (LPERRF).
A~ was discussed in connection with FXG. 6B, the LCP
was pro~ided with LPW circuitry 24w. ~ikewise, there is longitudinal parity ohecking circuitry in the IOT lOt. This . .
circuitry connects in a parallel path to the data bus shown as the lower ~6 lines o~ FIG. 5E.

:: :

: ~
-: .

: . ~ .

:
:

.

i3~

The Line Control Processor (LCP~I such as element 20 may be better understood with reference to FIG. 6C which represents a basic block diagram of the major elements ~- i~ol~ed in addition to some specific details with regard to the RAM buffer such as 25 of the LCP, 2000-The LC~ buffer 2500 is a random access memory ~R~M) which is functionally 25~ bits (0-255) wide and 18~bits deep.
It can ~hus hold Z56 words of 18-bits each. In one typical embodiment, the ~uffer 25 may have a section designated bu~fer A, 25 , having provision fo~ 90 longitudinal word~s of 18 bits each; another section designated ~5xi; a Command Descriptor C/D section designated 25c; a buffer area B, 25b which may typical].y be 90 words long, ~i.eO, from address 128 ~ over to address 218~; another buffer area designated 25 2; a 15~ ~ Result Descriptor R/D area 25r; another area designated 25x3; and a Descriptor Link D/L area designated 25d~
The ~1 buffer 2~oo is addressed by a memory address register 36 ha~ing a system address register section 36S and a device address register section 36d~ which communicate to the buffer 25 via an eight-bit address bus~ B8. ~he ~
buf~er 25 is functionally composed in the vertical direction ; (~IG. 6C) of 16~bits plus a parity bit, plus an ei~hteenth :
bit called an "end flag bit", the end flag b~ts residing in a storage section designated as 25e~
A ~'data b~s~' 47 provides a data input and output channel ; f~r the buffer 2500 to communicate to the ~ain System 10 through the system interfac~ logic 215s; and for the buffer 25aO to con~unicate to its peripheral unit via a device interface 22di. The system interface logic 21~i~ the devlce .

, ~

interface logic 22~i, and the CO~mO~l logic 2.2C sc~ematically represeTlts blocks which refer to more speciPic elements which are described in connection with ~IG., 6D, Referri.ng to FIG. 6F, there i.s shos~n a "messa~e block"
of the typc- used in the LCP buffer 250 cf FIG. 6C.
As mentioned with tha discussiorl o.f FIG. 6C in regard to the R~M bl~ffer 25 , this is typically a message block of "n" words, which block provides 90 words (or n = 90) ~or data storage; and also there may be proYided three words ~or Result Descriptors R/D; there ma~ be provided three word locations for Command Descriptors C/D; and therc may be one word locatior~ for Command ~1essages C/Mo ,., ~IG. 6F also sho~s the basic word format, in that a word is composed o~ four digits which are: A~ B, C, and D
plus a parlty bit ~ar~ed VPB ~vertical parity ~it), which normally ma~es a -total of l7-bits per word, ; As seen in the drawing o* ~IG. 6F~ the four digits A, Bl C and D are each made up o~ four bits designated as the 1l8rl bit, the "4" bit, the "2" ~it~ and the "l" bit.
Ill FIG~ GC, the buffer 2500 i.s also provided with an 18th bit or "end flag" bit which is pl~ced in the locatior .
designated 25 o~ FIG, 6C, .; ~ ~ ' ~: T~e ceMtral or Main System l~ communicates with the peripheral te~qinal unit via t~e LCP. The ~P pr~ides the . 25 mcans for transf'erring control information and data f`rom the Main System lQ to the peripheral termirlaI units, such as ~0, and vice-ver~a~ '~he LCP looks at the CQmma~d ~escriptor ~ C/D recei~ed from the Main System 10 and 5et9 :i tself up to :~ : perfo~m the operation required .i~ it is sensiti~e to that ,; ` , ' , ' ';

; - 7~ -particular command. I-t also tr~nsfers -the same Co~an~
Descriptor C/D unmodi.fied to the pe.ri.pheral t~ninaL unit.
The peripheral t~-rm~nal unit acts upon tb.e Command Descriptor C ~ and r~turns Result De~criptors R/D to the Main System 10 via the LCP. The message block and the ~ord ~o~ma-ts ha~e b~en shown in FIG. 6F. Iypical Co~and ~escriptors C~D and Result Descriptors R/D will be sho~l subsequentlr hereinafter.
The L~iP accepts the Co~nmand Descriptor c/n -t:ransmitted b~ the Main Systeln 10~ The C/D contains a digit of the OP
code, 3 digits of ~ariants, and ~ digitis o~ C address. The Co~nand Descriptor C/D is recei~ed by the ~CP via 4 di~its per transmission ~or a total of 3 ~ords (~ digits per word).
The two least si~nificant digits contain all zeros. With each ~ord there is a vertical parity bit (VPB) and the entire C~D is followed by a longit~dinal ~arity word (LPW3. Should a pari-ty esror be detected on tran~nission o~ -the C/D7 the LCP will branch to a Result Descri.ptor R/D mode and report a descriptor error to the Main Sy~tem 10.
The random access n~emory b~lffer 25 (RAM of the LCP) buffers the ent.ire Command Descript;or, thQ v~rti.cal parity bit and the longitudinal pari.ty ~ord with;n the ~CP~ Line ~ Control Processor.
,~
~e LCP examines the first word of the Co~nand Descriptor ~/D and determines whether it is an EC~iO OP7 HOST LO~D OP~ OI' ~Ei~D NO timeout OP~ I~ it is one of these, it sets the appropriate flag.

Fo7 lowing the receip-t o~ the Comrnand De~criptior C/D, th~
; Line Control Prooessor LCP proceeds to accept; the Descriptor ~ . ' .

.~,, ' .
~ ~ rjt l Z3~

- Lir~ D/L. l~i~ is a two word transmission follow~d by a longitudinal parity word LPW. Should there be an error, the LCP branches to the Res~lt Descriptor R/D mode 9 and .reports a descriptor error to the S~stem lO.
T~e random access memory ~S of the buffer (such as 2500) acts as the buf~er for the 0ntire Descriptor Link D/L, the ~ertical parity bit (VPB) and the longitudinal parity word LPW.
Disconnect Mode: ;
~ollowing the receipt of the Descriptor ~ir~ D/La the .
, LCP goes to the "disconnect mode".
Reconnect ~lode~ .
If it is an ECX0 OP, the Line Control Processor LCP .
proceeds to "reconnect mode" and starts operating on the ECH0 OP which involves the recei~ing of two buffers of data : (each 180 bytes, or 90 words of 16-bits) and the trans~itting ~f the same data bacX to the System ~emory 10 ~ . -I~ it is other than an ECH0 OP, the LCP examines the readiness of the peripheral terminal unit. Should the peripheral device be in the "not-ready" state, the LCP
branches to the Result Descriptor R~D mode and reports this i to the System lO.
~If the peripheral device is nready" the LCP starts communicating the Co~nand Descrlptor C/D to the peripheral device) while at the same time branches to the '~idle" state to make itself available for a possible "Condltio~al Cancel OP~q The Line Control Processor LCP stops in this "idle"
state until one of two things happen:
.

.

~ 78 ~

3~

1. The p~ripheral device sets up the Line Control Processor LCP to a ~data transfer" state.
2. The S~rste~l 10 co~municates a r~onditional Cancel ` ` Oplt or an Uncondition~l Cancel.
If it is number 2 ~bove, the Line Contr~l Processor LCP accepts one word from the System 10 followed by the longitudinal parity word LPW~ and the LCP determines if it is a valid Conditional Cancel OP. In any case the LCP
communicates this to the peripheral device. If the situation in~olves number 1 abo~e~ the LCP branches back to the ~ "disconnect" state, where data transfer between the LCP and ,. its peripheral can occ~r.
After transmission of the Command Descriptor C~D to the peripheral, the ~CP is driven by the perip~eral device "state", which defines the operation mode and the memor~ requirements.
, Data is transferred in 9'message blocks1' together with a longitudinal parity word ~LPW) of 16~bits following each b10ck and wi-th a parity bit on every ~-nrd (e~cept in a disk pack controller situation, the message blocX ~ou~d consist o~ a segment). If -the Line Control Processor LCP detects an error on data received from the peripheral de~ice or from the Main System 10, it reports this information to the ~perip~eral de~ice and then branches to the Result Descriptor-~/D mode and reports it to the Main System 10 2~ ~n the "Read'9 mode, the data transfer between the Line Control Processor LCP and the peripheral device ~is de~endent on the re~uirements of the peripheral de~ice. On the other hand, data transfer between the LCP and Main Memory 10m is de-pendent upon 1-he memory access rate of the Main System 10. 5ince , ~ ~ the peripheral :

, . - . , . ~

device may operate in a "stream" mode, and the LCP must compete with other LCP's ~or acc~!ss to memory, the LCP
alternates between i-t's two buffer areas to accommodate the trans~er rate o~ the peripheral de~ice.
Table VIII below indicates certain types o~ Co~mand Descriptors C/D which are used and acted on by the LCP.
- All other C/D's are transparent to the ~CP and pass throu~h to the peripheral de~ice:
: TABLE VIII
Command Descriptors.
The ~CP is transparent to all Comma~d Descriptors except for the following as determined by testing the ~irst word o~ the C/D:
1. ECHO OP ~bit Al is true) . 2~ ~IOST LOAD ~A4 and B8 are true~
- 3~ READ-NO T/O ~timeout) ~A8 and B8 are true) : 4~ CONDITIONA~ CAN OE ~ OP ~A2 and B8 are true~
, ..,., ~ , ~ 5O ~NCONDITIONAL CANCEL

! oP code digits o~ the C/D are de~ined as follows:

¦ ~O Read (A8) - Any operation where data is transmitted from the LCP buffer to the Main S~st~m.
(10001 ~: Write ~A4) - Any operation where data is trans-~erred from Main System Memory to ~CP b~ferO
100~

.: j Test ~A2) - ~ny operation where no data transfer . takes place between ~CP and Sy~tem : Memory but results in a ~/D storage in System Memory~ ~0010) . Echo ~ Operation that resul~s in receiving a ~: I messaye block from System Memory and : ~ then transmittin~ the same block back to Sy~tem Memory~ ~0~01).

. , .
~80 ~, ' .
.

3/~
Normally Result Descriptors R/D are generated by the peripheral unit and accepted by the LCP in one, two or three words~ ~hen the LCP generates a ~/D, only one word is sent : to the ~ain S~stem 10. .Table I~ shows the condition~ ~or the ~CP to generate a Result Descriptor: :
. TABLE IX
Result Descriptors Bits Condition A8 No~ Ready' . .
-~ lO A4 Descriptor Error A2 System Vertical Parity Error Al System LPW Error .
B8 Time-Out B4 Remote DeYice Vertical Pa~ity Error ~ B2 Remote Device LPW ~rror Bl (blan~) '. . : ;.: : , , ' ' ' ' ' ~ .
.
,, - .

. . , . . : : ..
. - - . . .

Referring to FIG. 6C with r~spect to the lines between the device interface ~2di and the per:ipheral unit, the peripheral device uni t may be provided with a port interface ~hich may be desig~atsd a5 a DDP or devics dependent port i~terface, 5d~ which is tailored to the requirements of each speci~ic type of peripheral device.
Th~ LCP comm~nicates to the peripheral via the DDP in an asynchronous mode. The "Write" operation is defined as a transfer where the LCP is writing into the peripheral device unit. The "Read" operation is de~ined as a transfer where the I,CP is reading from the peripheral device unit~
~ef~rrlng to ~IG. 6C the ~ine marke~ HTC~ ay be des~gnated as the Host Transfer Control ~svel, and when the ~CP "Wrlt~s" into the peripheral device unit, this signal is lS the asynchronous level, which signifies the presence of data on the data lines~ This level. is de~activated by the peripheral unit sending D~/ (perLpheral message level) or by sending DINTL/ (peripheral device interrupt le~el7 to the LCP~
When ths LCP is "Reacling" data on a ~esult Descriptor R/D from the p0ripheral unit, this HTCL/ signal is the asynchro~ous ac~cnowle~gement that the data on the data lines has been recei~ed by the Line Control Processor LCP~ IJpo~
rece~pt o~ this levsl, the peripheral device ~mit must de-activate D~IL/ or Dl~TL/. ~hsn the peripheral unit causes the de-activa-tion of DML/ or DINTL/, then the LCP de-activates ~: ~TC~/ (the Host Transfer Control Le~el).

', .
, `
:, : ,.
_ ~2 -When the peri~heral device unit drives the LCP to the Command Message C~M mode, the Host Transfer Control Level HTCL/ is sent to the peripheral de~ice ~mit when the LCP's buffers are empty and no system terminate has been detected.
The HTCL/ ~ust be answered by the peripheral device unit with a DINTL/ and-a ch~nge-of-state.
The line in FIGI 6C marked HINTL/ lS designated as the Host Interrupt Level and is used by the LCP to indica-te to - the peripheral ~ni~ that the LCP wishes to interrupt the operation. The response to this le~el by the peripheral de~ice must ba DINTL/ and a ch~nge-of-state, to which the LCP responds by de-act.~ating its Host Transfer Control Level, HINTL/. Following the d~tection of the trailin~ edge of HINTL/, the LCP will res~ond to the new mode of operation described by the state line shown on ~IG.6C as ST-4/, ST-2/~
ST-l/.
When an inter~lpt from the System 10 i5 ac~i~ated in the "Write" ~ode, -the Host Interrup-t Level HI~TL/ signifies that the last word of d~ta has been transmitted and the ~PW i~ on the data l:LIle of ~us 4~ e p~rlpher~l unit needs to respond to the interrupt with a DINTL/ and a change-of~state.
In the "Read" mod~ when the LCP detects the "Read T~rminate 7t ,command the LCP will activa~e the Host Interrupt Level HIi~TL/. In the Command Message C/M mode/ the LCP will activate the Host Interrupt Level HINTL/ if a "Read Terminate"
has been detected.
The lix~e o~ FIG. 6C designated HCL/ refers to ~1Host ~ear" which indice.tes -to the peripheral unlt that the LCP

. ~ .
.

a ~

is being cleared by the Main System 10 5 or that a.parity error has o.ccurr0d during a read.
A combination of the Host l`rans~er Con-trol ~avel and the Host Interrupt I,evel (HTC~/ - HINTL/) lndicates to the peripheral unit the presence of a ~ost Load Command Descriptor C/D. ~he peripheral unit responds by activating . t~e line marked ~INTL/ ~peripheral interrupt le~el) and the Status Count ST - 2; the LCP acknowledges by de-activatin~
both levels o~ HTCL/ - ~IINTD/. Following the trailing edge 1.0 of DINTL/, the LCP trans~ers data in the "Write mode".
In FI~. 6C a bidirectional data bus Bd is provided having ; 16 data lines and a pari~y line betwesn the LCP and the peripheral unit~ Wh.en controlled by the LCP, these li.nes are active as long as the Xost Trans~er Control Level ~TCL/ is active. ~len control is held by the peripheral unit, these lines are active as long as the peripherai device mess~ge le~el DML/ is acti~e. ,The directio~ of t.ran~fer is determined by the status of the peripheral UIli t. ~le line ~esignated ; DML/ refers to the peripheral de~ice message level a~d i3 a ZO unidirectional line. When the ~CP is reading data or a Result nescriptor R/D from the peripheral unit to the LCP, the peripheral de~ice message le~el D~IL/ is used as a transit :; si~al to i~dicate the p~esence of stabla data on the data ~, lines, When the peripheral de~ice receives a Command `~$ ~e~crip-tor C/D or data fro~ the LCP, this signal, D~/, is : used as an ackno~iledge level ~or data~
. ~
~ he peripharal device (Yia its port interface) uses the DINTTL/ (peripheral interrupt leYel) to requLest the ~CP
to change its mode o: operatîon. I~hig is done b~ ac-tivating . ! : . .
. . .
.

' DINTL/ a.~d presentin~ the proper state on -the ~-tate linss, ST-4/, ST-2/, ST-l~. The state lines ~wst be ~table durin~
the tin-ie that DINTL/ is act.ive.
In the 'lWrite Mode~
_~_ _ _ DINTL~ is the.acknowledge le~el to the Host Transfer Control Le~-el HTCL/ and the TPW data word, or else it is the response to HTCL/ or HINTL/ in the Command Message C/M mode.
DrNTL/ will cause a change-of-state to occur for either the above. When the LCP is writing into the perip~eral ~nit, the peripheral device interrupt level DINTL/ is based on the leading edge of ~TCL/ or HINTI./, DINTL/ is de~acti~ated by the trailing edge of these signals (~.TCL/ v HTNI~
In the "Read Mode"~
Ihe per.ipheral inter~pt level D-~TTL/ is a no-data transfer ~Is~robe~ used exclusively to change states, DINTI,/
; is acknGwledged by the Host Trarsfer Control L~vel Y.. TCI,~ in . the Read Mode. When the LCP is reading from the peripheral - ~ device unit, the peripheral device acti~aces DIIITI,/ instead of the peripheral messa~e level DML/, and de-acti.vates DIN~
~o when the peripheral unit detects the leading ed~e of the , Host Transfer Control Level HTCL/.
.` ~ In the Host I,oad:Mode:
~ mode i~volves the transYer or loadiIIg of data ~rom j the perip~eral device, as ~0, FIG. 6C~ into the LCP (Eost) for the "~ead Model' and vice versa *or the "Write Model'.
', The pe~ipheral device interrupt level DINTL~ i3 the acknowledge le~el to HTCI,/ - E~'rL/ as the Ho5t Loa~ Comman.d~
The peripheral de~-ice activates DINTL/ and changes -to State 2 ~Table x.3 T~e LCP acknowledges this by de-ac ti~ra-ting ~ i ` . . -::~
; ~ - 85 -3~ .

both HTCL/ - HI~TL/, and i~ in the 'l~rite Mode"~starts writing into the peripheral devioe memory. To interrup~
t~is mode the perip.~eral de~vice unit 50 activates DINTL/
in the same manner as in a regu~ar "Write Mode".

~
In ~IG. SC, these unidirectional. lines ST-4/, ST~2/, ST-l~, indicate to t~e LCP the state o~ the peripheral de~ice, and ~rom this, th0 LCP de~ermines what kind o~
operation mode is required. For e~ample, in a typi.cal embodiment, -there may be eight states, 0-7, as seen in Table X, for the peripheral device which might be used to indicate the following collditions: peripheral de~ioe not on-line; Read operations; Write operations; Result Descrip*or; Command Message ~C/M); reset LCP timer (F~T);
~5 ready or writing Command Descriptor (C/D); last word of ; ~ a block or the Result Descriptor and longitudinal pasity wo~d (R/D-LPW) is next to be transmitted.
A typical coding system for the state lines from a typi¢al peripheral device ~nit is shown hersin below in Table X~ ~

, , ~
' ' , ~ "

~$~

~, o hl h h h h h h h C

~3 ¢1 .
. . h `, _. I _ ~ ~
.' .. I ~ V o , ~ Pl ¦ ~ h h h I P. O a~
~ I ~r~ X

~1 I
~ ' ~.~
I O ~ 1 0 I
O 0 ~ ~ ~I O O

t' i I O O O C
I

~, :
: ~ 87 --~$~
The interface discipline between the L(.P and the peripheral devise un.it via the peripheral de-vice unit port in-terface~DDP 5d~ ~IG. 6C) may again be looked at in terms of a "~eading Mode" and a l'Wri-ting ~ode"~
Readin~ ~1ode:
; With the Line Control Proce~sor LCP reading from the peripheral device unit (S-tate _ l ~ 7~, the peripheral device unit ~as 50, ~IG. 6C) places a word on the data lines and activates tha perip~eral de~ice m~ssage 10~el D~. The LCP acknowledges this by activating the Host Tra~sfer Control Level (HTCL/). The peripheral device unit now de-activates DML/, and -then the LCP de-activates the HTCL/4 This process continues in State = 1 until:
lo The L~P activates the Host Int~rrupt Level (HINTL/).
The peripheral unit acknowledges by de-activating the peripheral message ~.evel ~ ), if active, and activat~s ~ the peripheral device i.nterrupt level ~DINTL/) with a change-:,~ of-state. Thi~ indicates to the ~eripheral device that the LCP has a "Comn1and Message" C/M to send to the peripheral devlce~
2. The peripheral device activates the peripheral device interrupt level DINTL/ i.nstead of the peripheral message level DML/, with the proper chaDge in the State Line50 The LCP
. acknowledges by activating the }Iost Transfer Control LeveL
~5 (HTCL/), and, following the de~activation of DINTL/, lt de~aotivates the Hvst Transfer Control Leve~ HTCL/ ~nd goes ; on to the proper State, DI~TL/.doe~ nQt trans~er data on the data lines.
~ .

: ~ :

3, ~hen the peripheral device detects it is transmi-sting the Last Word of a block~ the perlp~era.l. device changes to Status ST - 7 with the lsddir~g edge of DML/. ~he LCP
answers the peripheral device ~,~ith a Eost Transfer Control Level (HTCL~) and e~pects the next transfer to be the longitudinal parity word LPW.. The I,PW is transmittad with the peripheral message level D~/ and answer0d wi-th a Host Transfer Control ~evel (HTCL/).
4. I~` tha LCP detects a ~er~ical or longitudinal parity error, the LCP will not acknowledge the peripheral mes~age level D~IL/ from the peripherzl clevice. Instead the LCP will generate a Host Clear T evel (~iCL//).
In the Writin~ Mode:
If the LCP is writing data lnto the peripheral device (State - 2 1 7) 9 the following aCtiQns ta~e ~lace:
The LCP pla~es a word on the data lines and activates the Host Transfer Control Le-v~l (HTCL/). The peripheral devlce acknowledges by activating the peripheral devi¢e mQssage level (D~IL/~. The LCP now de-activates the Host ~0 Transfer Contro7 Le~el (XTCL/), and then the peripheral device de-aotivates the peripheral message level (D~I,/).
This process continues (Table X) in Status ST = 2 uIltil~
The peripheral device changes state to ST _ 7, then ~. ~
`~ aotivates the peripheral message level D~l~/ ~hich flags the .~
LCP that ~he Tast Word of that block has been re~eivedO The next~word in the data lines must be a lo~gitudinal parit~
~ ~word LPW w~len the Hos-t Transfer Control Level ~TCL! becomes ,, :
active again. Then the peripheral device aoti~a-tss the peripheral interrupt level DINTL~ instead of the psripheral 3~ device message le~el DML~, accompanied by a change in the St~t~ Line~
: 1 ' , 2. At ST w 2 or ST - 7, the LCP act.i~ate~ the Host Interrupt Eevel HINTL/ instead o~ the Host Transfer Control.
~evel HTC~/. I~ this mode, H~T~/ si~nifie~ an in$er~up-t and t}lat a ^.ongitud~nal parity ~ord LP~ is on the data liIles.
'l~e peripheral de~ice acknowledges by acti.vating -the periphera]. inte~rupt ievel DINTL/ and a change-of~stzte.
The LCP de-acti~ates the Host Interrllpt Level ~INTL/ and goes *o the proper mode a~ter DINTI,/ is de~ac-ti-~ted.
In another ~lo~e oalled the l'Result Descriptor R/D Model', the LCP rea~s a Resul-t Descriptor ~/V f~om the peripheral de~ice (State = 3 ~ 7). When in the RfD Mode J the LCP is reading the Resu~ Descri~tor on tl~e data liries from +he peripheral device. The Result Descriptor R/D can bc from 1 to 3 words long plus a longitudinal pari-ty word LP~-. The 1~ firs~ and secund words of' the 3-word Res~lt Descript~r R/~
are read in Status ST _ 3. The last word o~ the Resul+v Dcscriptor R~D i.s read in Status ST = 7~ The peripheral - ~ de~7ice message le~reL DMl~ signifies there is stable data on the data lines. Each Result Descriptor R/D ~ord transferre~
is then acXnowledged with a Eost ~ansfer ~ontrol. Level ~TCL/~.
If a l-word Re.sult Descrlptor R/~ is received by- the ~CP, then data transfer occurs after going from Status ST _ 3 to Sta~u~ ST = 7 together with a peripheral c]evice message le~el DML/ which signifies a l-word Result Descr.iptor R~J The ~5 next word ~n the data lines is the R~D longitudlnal parity ~' ~ord ~PW which is st~obecl by the peripheral de~ e message : ~ lev~l DM~/~ A~ter the LCP finishes reading a complete Resu~t ~ ~ Descriptor R/D together with its appropriate longitudinal :1 - 90 - ' parity word LPW, the peripheral de~Ji~e return~ to.Status ST = 6. It can IlOW aecept a C.ommand Descriptor C/D.
Command Messa~ C ~ Mode:
. This invol~es the situation in which. the LCP is writing a Com~and Message into the peripheral device ~State ST - 4).
Whe~ the LCP i5 in the "Read" mode a~d i9 di.rected to the Com~and Messa2e C/M mode ~DINTL/ + ST - 4) 9 the LCP continue ~o send data to the Main System 10 until:
1. The ~ead-sy3tem terminate~ is detQeted which results in aCtiYatin~ tha Host Interrupt LeYel HINTL~ or:
2. ~ata buffer are~s A and B (of buf~:er 2500, FIG. 6C) :.
are emp~y and the "raad-sys te~ te~minata" is not detected~
This causes the LCP to aotivate the Host l'ransfer Cortrol Level HTCL/, indicating tha t the ~lain System 10 expects mora .~ 15 . data.
r~ d ~his occurs whe.n the perîpheral device resets the LCP
tim0r (State ST = 5), A ohang~-o~-state to ST = 5 rese~ts the L~P. timer~. Ihis chan~e-of-state occurs without a strobe.
20 : The peripheral-device uni-t must rsmain in ST = 5 for at edst 500 n~luseconds. ~ . ,.;

In: this case ..he LCP is~ writing a Co~mand Descriptor r ~ C/D-; iIltO the peripheral de~rlce (St&te = 6) o ~In this send 25; ~ Go~mand~:Descriptor Moda C/D~ the LCP writes 3~words followed by~a~longitudinal parity:word~LPW. ~The Xost Transfer C~ontrol Level~HTC~ at accompanles the C/D and LPW i ack~lowledged by~the perip~èral~:devloe~interrupt le~rel ~INT~/ ~nd a change to ~ the proper~st~te~

:

The Last Word of Block ~lode: !
~ his is the State - 7 (of Table X:)` and during a "R~ad"
cperation with ST = 7, the LCP i~ reading the last word of a block of data (or else a Result Descriptor RjD) from the peripheral device~ ~he next word wil.l be an LPW. During a ~rite" operation with ST = 7, the LCP is writing the last word of a block into the peripheral de~ice. The next word will be a longitudinal pari-ty word LPW.

0~= : .
~*ter the LCP writes the Command Descriptor (`/D into t~e peripheral device unit and before the peripheral device changes from Statu~ .5T = 6 ~^ith the peripheral in~errupt level DINTL/, the ~ain System lO can terminate the operation (OP) b~ issuing a "Conditional Caneel". In this c~se, the LCP de-activa-tes the Xost Transfer Control Level HTCL/ and then activates th~ Host Interrupt Level HINTL/ as long as the Status ST = 6 and DINTL/ is not acti~eO

The Main System lO can generate an "UncQnditional Canceln. This causes the LCP to generate the Host Clear LeYel HCL/ to the peripheral de~ice. No acknowledgement required from the peripheral deviceO

~,. ~ : '' ' ' ~ . : . .-:

~ ' ' ~ .

:

The LCP ~Line Control Processor) Subsystem consists of a number of individual LCPs which communicate to the Main ^System io throu~h the IOT lOt. While each of the se~eral $CPs ha~e basically the same design and provide the same basic system functions, there are ~ariations o~ a minor .
nature as between the various types of LCPs, si~ce each LCP
i~ tailored to meet the operational requirements o~ the ~ particular peripheral terminal unit that it services.
-~ The discussion followin~ herein will in~olve an operational description~of one preferred embodiment of a particular LCP which is pro~ided for a-peripheral terminal ~ ,i unit known ~s the "Supervisory Terminal".
The necessary functional elements of the LCP include reglsters, counters,-encoders1 decoders, b~sses, logic 15 ~ ele~ents9 etc. In addition there is a large scale integrated (LSI) reoeiver/transmitter for implementlng communicatlon between the LCP and its peripheral terminal unit. Within the LCP, ther~ are functionally two divisions t~hat are used ~or communication between the LCP and the ~lain S~stem lO.
They are desi~nated as the 7'read module" and "write module".
These modules exist "functionally", but they are not separate components, since many of the logic levels Or which they are composed are shared by both modules. The "read modulen is used to transfer data from the LCP o~er to the 25 ~ ~ Main System 10~ and is active when the transmit flip-flop (~M~TF) in ~the LCP is set. The "write module" is used to trans~er data from the Main System lO o~er to the LCP, and active when the receive flip flop (RECVF) is set~
Funotlonally, the componsnts of the LCP are contained `~
in thrse major sections: (A) Tex~inal Control; I(B) Data Fl~ow;

: ~$,~i -3,J~
and ~C) Syrstem Log~ic Section, In vrd~r to understand the means by which the LCP cor~lunicates ~.ith the Mai.II Syst~m 10 and with -the assoc~ated peripheral t~rmi~al unit ? s~ch as 50g the functiorlal characteristics of the followlng compoilents ~ill be discussed:
A. eri~hera]_Te~linal Control Secti.on 1, Univer3al Asynchronous reoei~er/transmltter (U.~RT).
2. UART Multi.plexvr.
lQ 3~ Llock check character r0gister (BCC~
4. Bloc~ check character decoder, . 5. End co~e d~coder.
6. Memory address register.
. B. pata _l `~ 15 1o Input Multiple~or ~ : 2. 0P code register.
.
3. ~ariant register.
4. Yalid OP encoder.
,~ , . .
: . 5. LCP bufrer ~R~
6. Terminal bus m~ltiple~or,

7. Terminal bus.

8. Ver-tical parit~ ~enerator~checker.
;

: ~. Data Latch regist~r.
. ~
: lO.~Longitudlnal pa.rity word ~LPW) re~isterO
25 ~ PW encoder:~
120 End cvde decoder.

`:~;: :
;~,: ~ .

:j :

~:3 ~

,~ .
~ 94 _ :
, , , . , :
. , ~. -~ ,.. . ...... ... ..

-~

C. Syst~m ho~ic Section tatus Count ~STC) regist~r~ .
2~ STC decoder~
: The above mentioned functional components will be .
understood ~lth raference to FIG. 6B, 6C~ 6D, 6E and 6F, : ~ . with particular references to FIG. 6D.
~ . ~ Examples of types o~ interconnections between peripheral : devices and I/O interface units may be found in U.S. Patents, .
such as 3,510,843; 3~514,785; 3,$26,878. Examples of the ;~ ~ 10 circuitry involved in communication between remote units and ' corresponding bu~fer registers in a typical ~ashion can be found by reference to U.S. Patent No. 3,390,379 With reference to FIG. 6D and the Peripheral T~rminal Control (Section A) previously mentioned, the universal asynchronous receiver transmitter tUART) 31 is used as the : interface between the asynchronous serial data channel of the terminal unit device interface 22di and the parallel : -data ~ransmission channel o~ the LCP. The transmitter section of the UART 31 converts a parallel data character ~ . ~
and the control levels into serial information containing ~ a start bit, data, a parity bit, and a stop bit. The :~ : receivex section of the UART 31 converts serial information, , . : containing a start bit, datal a parity bit, and a stop bit, : ~ into a parallel data character.. The UART 31 yenerates a parity bit for information transferred to the terminal unit :device interface 22di, and it also checks the vertical parity f information received from the de~ice interace terminal ~ .
: unit 2-2d~
; The U~RT 31 has provisions for selecting ~arious character ~ 30 lengths, odd or even parity generation/checking, and a choice 1 : of one or two stop bits. For use with a particulax LCP, th~UART
~-'. :~ .
31 h~s opt~ons selec~ed to pro~ide the follo~ing characteristics:
al a character con~aining se~en data bits;

(b) generation/checkiIlg o~ evell vertical parity;
~e) one stop bit, The UA~T Multip~exor 27X accepts an 3-bit character frt3m elthel the AB ~first t~o) di.gits o~ the te~minal b~s 47 t3r from the blo`ck check character register ~BCCR) 33.
The selected input is sent to -the parallel data input bus of the UAR~2 31. ~le UART Multiplexor 27~ is used only- ~or the transfer of data or for a block check character ~'rom the LCP ovsr to the terminal device interface Z2di.
~he Block Check Character Register (BCCR) 33 is a rcgister whlch consists of ei~ht se~3arate flip-flop~ operated in the "-tog~le" mode, with in~uts co~ected to +,he ~ di~its o~ the terminal bus 47. ~lile the ~,CP is trans~erring data to the terminal de~ice interface 22di, the ~CCR 33 acc~nulates a block check cha-ractar ~BCC) to be sent to the de~ice .~ i.nterface term.inal ~lit 22di. ~hen the LCP is recei~-ing data from the de~ice i~terface terminal wnit 22di~ -the BCCR
. 33 also accumulates a t'block check character" to be checke~
:;
against ~et another ~biock check charac-ter" (BCC) sent froM
: 20 the device interfa&l3 terminal uni~ 22di. The bloc~ check eharacter accwnulat~on is started upon the receipt of ~he ~irst character ~ollowing a STX ~start of text) or a S0~-I
~start of heading~ character, and cvn-ti.nues until an El'X
(end o~ text) character is recei~ed~ Onlr messages and i ' J ~ 2~ con~rol sequences containing a s~r.x or a SOH character will i~ cau~e a block check character (BCC) to be accumulated~
i .~ The accum~lation o~ the BC~ consists of applying each oharacter being -trans*erred to the inpllt of the BCCR 33 alld par~o~ming a binary additlvn without Garry (Exclusive .

; OR ~unction). Prior to each operation in which a BCC will be accumulated in the BCCR 33 7 the register i~ cleared. At the end of a data transfer9 the exclusive OR ~lction is again per~ormed between BCC's of the sending and receiving units~ If no errors have occurred, both BCC's will be i~entical and the resultant ~alue in t~e BCCR 33 will be ~all zeros".
The block check character decoder 34 receives the output of the BCC~ 330 At the end o~ a transmission from the peripheral terminal unit 50, a BCC is received and checked against the contents of the ~CCR 33. If the two BCC~s are identical, then the output of the BCCR is equal to "all zeros" and the decoder 34 generates the BCCOK le~el ~Block check character 0~) which is used in the BCC error logic.
~, , 15 The memory address register 36 is_an eight bit register ~ whi~h develops addresses for a ~56 word LCP bu~fer 2500.
; ~ The register 36 is oontrolled so as to provide selective or sequential addressing o~ the buffer, ~ required by the data transfer operation which is to be per~ormed.
The Termination Card 200t (of ~XGo 2) pro~ides a one-second tiu~er which is enabled ~or operation only during a ~ead" operation when the LCP is conditioned to receive data ~`
from the peripheral unit, such as 50. wheDi enabling inputs are acti~e, the timer allows the peripheral terminal unit a one-second pe~iod in which to begin a transmission or continue an inter~upted transmission o~er to the T-CP. If .~ , ~` ~ the one-second period eIapses without a transmission from the peripheral terminal unit, a time-ou-t flip-flop (T~OUTF) is sét~ generating time-out level (TIMOUTL), and the LCP then .
; . .
? ~: . , !

initiates an end to the read operation hy setting an end flip-flop ~ENDF). However, this timer can be programmatically inhibited from operating by placi~g t;he proper code in the variant-l digit of the Command Descriptor ~FIG. 4B)o With reference to FIGS. 6B and 6D and the prior discussion regarding the Data ~low section of the LCP, ~Section B)g the input multiplexor 24 1 provides the ~election of a 17-bit word from threa sources- the data input lines Bi, the output lines B~5 from RAM data buffer 2500 or the peripheral device interface levels 24m which are generated on the Maintenance Card (such as 20Om, FIG~ 2) from the outputs of push-button switches on the maintenance panel. The selected leYels received by input multiplexor 24X1 are transferred to the OP code Reglster 42 and variant register 43, ~- 15 the terminal bus multiplexor 24 2 or the valid OP encoder 44, : . as re~uired by the operation to be performed.
~ The OP code Register 42 recei~es the digital OP code of ::. the Command Descriptor C/D7 and in co~.. junction with ~he output of the variant register 43~ specifies tha operation to ba performed by the LCP. The vari~nt register 43 receive~ the variant digits contained in the Command Descriptor C/D and, in co~junction with the outpu~ of the OP code register 4~, speoifies further de~a~ls o~the operation to be performed : by ~he LCP.
: 25 The Yalid.OP Encoder 44 is a network which receives Command Descriptor C/D information at its input; then, if the .
: OP code digits and the variant digits 1, 2, and 3 coincide with ~alues representing valid operations ~or th~e LCP, this '~ encoder de~elops the vaiid OP (~OP~ level~ whioh enables .~ ; , .
!

L,.3~

the Command Descriptor C/D to be loaded into the OP coda register 42 and the variant register 43.
The LCP RA~ buf~er 2500 is made of a network of 18 RA~f . ' de~ices~ each one o~ which has a capacity Or 256 information bits, Referellce to FIG. 6C will show more detail of the R~M
buffer 2500. The buffer networ~ can ~;tore 18-bits in each of its 256 address locations; 16 are data bits, one bit is ' :
a parity bit, and one bit is an end-f:lag bit~25e of FIG. 6C~
to identify a word location containing an ending code.
Referring again to FIG. 6D, the terminal bus multiple~or ~ ne~work 24X2 provides selection of a.17-bit word from four ', ' sources: the input multiple~or 24Xl; the UART 31 parallel -.
;. . data output llne; t~e LPW 24W register output; and the Re~ult Descriptor le~els 24 d~ The output o~ the terminal 15:: hus multiplexor network 24X2 goes to the term~nal bus 47.
Appropriate~voltage levels are provided to those LCP components, ~' (such as the data latch register 49, vertical parity generator/checker 489 buffer 2500, LPW r~gister 24w9 decoder 52 and end code decoder 35 etc.) which have inputs received ' ~ from the terminal bus 47.
' :~ 20 The termlnal bus 47 connects the output of the terminal :
bus multiple~or networ~ 24X2 o~er to ,the following components:
the data latch re~ister 49, the LCP RAM buffer 25o~, the LPW
register 24w, the vertical pari tr generator/c~ec~er 48, the 25~ BCC~re~gister 3~, the end code decoders 52 and 35, and the UART multiplexor 27æ.
,: The verticai parity gener~tor/checker 48 generates odd parl~ty f or e~ery word transerred by the LCP over to the Main syBte~ 10. The gene,rator/chec~er 48 also checks for odd , :: . : : . : : .

~ ~ ' . '.

parity of every word transferred from the Main Syste~ o~er to the LCP~ Each word to be transferred from the particular LCP over to the Main System 10 is~first placed in the 17-bit regi~ter called the data latch register 49~ The data latch register 49 then transfers the word over to the Main Syste~
10. The use of the data latch register increases the rate `, of data transfer by allowing quicker access to data stored in the LCP RAM buffer 2500.
- The longit~dinal parity word (LPW) register 24 is made ~' 10 of 16 separate flip-*lops operated in the l'toggle" mode. It recei~es its inputs from the ter~linal bus 47. When the Main System 10 sends a Co~mand Descriptor C/D, a Descriptor Link D/L, or data, over to the LCP, the ~PW register 24W acc~ulates a LPW (longitudinaI parity word) to be ~hecked against an . LPW from the System 10. When the ~CP sends data or a Result ''' Descriptor R/D oYer to the System 10, the ~PW register ~4w also acsumulatesan LPW to be sent to ,the System 10.
.
Accum~lation of the LPW consists of applying each word being , sent or recei~ed to the input of the LPW register 24 and ,; 20 performing a binar~ addition without carry ~exclusi~e OR
~ ~unction).
. The LPW register ~4~ is initialized to "all ones" prior to each operàtion in which an ~PW will be accumulated in the LPW
register. At the end of a data transfer from the ~ain Sy~tem 10, the~exclusive OR function is performed'bet~een the accumulated LPW andan LPW from the System 10. If no , '~ errcr~ ha~e ocourred, both LPW's will be identical and the ' ~ ~ resultant value in the LPW register Z4w will be "all zeros".
' i ~ . ~ , - . ' :, . . :
:

In FIG. 6D the end code decoders 52 and 35 are used to de~ermine the receipt of an ending code character. Decoder 52 handles the AB digits and decoder 35 handl0s the CD
digits. The AB digit end-code decoder 52 is used to ident;ify an endin~ code in the first character position of a word fro~ the Main System. This decoder is also used to identify an ending code in any character sent from the te~minal unit device interfacs 22di. If decoder 52 recei~es such an ending code, it causes the level EDCODE and the le~el SY5~N~
to be generated. The CD digit decoder 35 is used to identi~y an ending code in the last character position of a word from the System. Receipt of guCh an ending code b~
decoder 35 will cause the volt~ge level SYSEND to be generatecl~
The above discussion involved the second section B of the LCP. Now the third section C~ the System Logic Section of the LCP~will be discussed with reference to ~IG. 6D.
The Status Count Register 53 (STC~ is a fo~lr-bit regi~ter. This reglster develops Status Count le~els ~STC,n~
for use in the ~CP and le~els designated LCSTUn (LC~ Status I,evels) fo~ transmission to the Main System 10. In conjunction wlth providing floating logic le~els~ the STC
~ register 53 also controls the sequencing of operations ~or the f LCP~ Each Status Count deYeloped by the ~TC register 53 specifies a dlfferent phase of operation in the executiorL
:~ 25 of a Com~and Descriptor C/D, as was pre~iously outlined in ~ t, ~
~ connection with FIG. 6A. The decodar 54 is a binary coded ;.~
d cimal (BCD~ to decimal decoder whlch changes the BCD
values o~ the STC reglster 53 to decim.~l ~ralues required ~y .
: thc LCP system.

~: :
~ -- 101 -Reference to FIG. 6E will be ins-truc-~ve in ~e~iewin~
the system interrelationships ~etweetl the major LCP elements in~olved in re~ard to the logic an~ control signals operating between these elements. ~IG. 6E shvws the major logic and control lines between the IOT (Input-Output Translator) 10~, the ~istribution Card 20 d (~or the Base Module 2003 7 the particular Line Control Processor I,CP 2~ 0 and the peripheral terminal unit 50.
~irst referring -to the lowermost group of control lines, the LCP 200o and its Distribution Card ~od' ~he clesignation LCPREQ (n) is a group of eight "request" lines where the letter "n" represents the nunlbers 0-7 for ~ach speci.fic LCP
ln the Base Module 200. Eaoh of these signals is dri.~en by one particular LCP over to the Dis-tribution Card 200d~ This 15 . si~lal is used by a particular LCP to "requast" a connectlon ; to the System lO and causes the Distribution Card 20 d to : ~et up a "Poll Re~uest".
.
:; ~he next designation LCPCON is th~ designation for "LCP
~ colLnected~O ~ This line is dri~en by the co~mected LCP (0-7~
'` ZO ~ to the Distribution Card 200d. This signal is dri~en by the ~CP when it detects its own particular LCP add~ess and it is not in an "of~line" condition. The signal i5 a re3ponse ~' : to the LCP address an~ si~li~ies to the Distribution Card 200d~the presence of the LGP addressed.
25 ~ The designation~LCP9TL signifles "LCP Strobe Le~el"~
; miS line is~driven by the ~col~ectedl' LCP o~er to the ; Distribution~Gard. It is the partlcular LCP's designation :o~ ~send"~or "acknowled~e'i9~depending orl the d~ta directio~
, . , ~ ol~0d-~ ..

. .

The I~;~ND designates I/O senc1. ~lig line is driven by the "comlectecl" LCP to the Dlstribution Card 200d.
~li5 llnes defines ~,he direction of the bidirec~lonal cla-ta lines mar~ed D~ cn~ When this ]i.ne is activa low, the data lines will ~e driverl by the ~istribLltion Card 20 d to the Main Syste~ lO via IOT lOt.
The L~CSTU (n~ designates the status of the particular I,CP where "n" may designate either of LCP's 0-7. This lir1e is driven by the particularly-connec-ted LCP to the Distribution, Card 20 and reveals the "status" of the LCP as .shown in od FIG. 6~.
Rere~ling to FIG. 6E, a nu~nber of connections a:re provided as betweelL the LCP, such as ~0 ancl the Distri~u-tion Card 20 ~. The DAT~ (xn~ re~resents the ~messa.ge level interface'~ (as preYious:ly sho~ in ~`I*. 5E of which the lower l6 lines are the data~Lines for the digits ABCDl. The next higher line is the PAXITY line which carrie~ the parlty bits. These 17 l.ines constit~ e the message level interface and a.re of a bidirect.ional nature, that is to say, transmission zo may occur in either direction alo-r1g tllese liIles depending on the logic control linas used to deterl~ine the direction of transmission.
The desig~ation El~REQ in FIG. 6E signifies the " .
i 'lemergency request" 1ine. This line is driven by one or more ~25 LCPs to the Distribution Cards. The LCP may drive the emergency request line at any ti.me. The emergency request , : ~ signifies thatar.L~CP needs sys-tem access quicl;ly to a~oid a data transfer fail.llre. Only LCPIs whose lack of systeM
,:. ~ .
~i~ access will necessitate operator intervention or di~ficult . . .

, , : .
' .
, ' ~ 103 . .

~l~h~

error recovery, will drive the emerg2ncy reque.~t in conjunction with their LCP request. Tho3e LCPs which zre not emergency requestin~ will di~b~e their ~CP request with this line. A Distribution Card detectl~O an emergenc~
request, will cause a Global Prior.ity of "seven" to be transmi-tted to t~e ~lain System lO during a "Poll Request".
The designation TERM in FIG. ~E designates a "ter~inace' vo~tage level~ This is generated on a Distribution Card ancl is ~ent to the ~CP to terminate or end an operatlon.
The designati~n LCPAD "n" in FIG. 6E designate3 the LCP address ~where "n" ca.n be 0-7~ to designate the individual LCPsO One of these eigh~ signal line5 iS dri~ n by the Distri.bution Card to each particular I.CP. The rQceiver in the LCP w.ill be jumpered to the proper lin~.
This signal is functionally a co~tection lina to the ICPc ~n ~CP receiving its LCP address 1 "conn2ctec1" to the ~lain Sys~em lO through the Distributiorl C~rdO
~ lhe STIOL in FIG. 6E si~nifies the "Strobe I/0 Le~cllin i ~ rhis line is driven by the connec-ted ~istribut:i~n Card. Itrepresents the System's "send" or "acknowIed~e" depenrii~g on the da.ta direction.
~he ARQOUT line of FIG. 6E is the oUtput end of the Distribution Card which has an input design~ted ARQIN. These ~;~ represent l'acoess request in" and "acces3 request out'10 :
These signals are d~ive~ a~d received by ~istribu~ion Cards ;~ 'o~ly and ~onsist of short lines bet~een adjacent Distributio ~ards~ They are used during "P~l T~t" to resol~e .~ :
Distrlbution~C~rd priority~ The line,s I~B 1 and the I)CB 2 represent Dist~ibution Card "busy" le~els. These are ; ~ .

: ~ .
~, , . :

j yenerated on e~ch act~Ye Distr~bution Card in a Base Module to resolve Dl'str~but~on Card prioxit~ in the module duriny a "Poll Re~uestl' se~uence.
The PTALB line designates "Poll Test acti~e level".
?
This is a bidirectîonal signal le~vel between Distribution Cards in the same Base Module. A Distribution Card perfoxmin~ a "Poll Test" operation sends this level to the , ~ other Distribution Cards, thus inhibiting them from conducting ; ~ , a "Poll Test" or a "Poll Request" sequence.
Each Base Module may service not only one "main system"
i 10 via its Distribution Card (200dl FI~.~) but may be provided with multiple Distribution Cards to cooperate with ancl servlce ~ j other host "main systems". Each Distribution Card in a Base .~ . I
Module can service a different host system and each host system would follow the same basic organization shown in FIG.3.
- The REQACC line designates "Request Access". This line is driven by and received by Distribution Cards only. The line is used to signify an interrupt request as being "active"
by the Distribution Cards.
~o l'he BUSY line of FIG. 6E designates a Base Module "busy"
level. This is a bidirectional signal level developed on a -~, , :
Distribution Card when that card has made a "connection" with the Main System 10 ~ The level is sent to other Distribution Cards on the same Base Module to indicate that the LCP
backplane is in use.~
Now further in reference to FIG. 6E, the relationships between the IOT 10t and the Distribution Card 200d will be discussed. At the upper left o~ FIG. 6E, the LCPST
designates the LCP Strobe Pulse. This is generated on a Distribution Card ~rom the LCP stxobe level and is sent on ` to the Main System via the IOT 10t.
The PB~ST 2 designates "Por~ Busy" or the LCP status 2 line. This line resides on the message l~el interface as shown in FIG. 5E. In the "unconnected" state, this line ~, , . ,~ c t.~"~

indicates a Port Busy condition during a "Poll Test"
algorithm~ In the "conne~ted statel', this line carries bit 2 o~ the LCP's st~tus to the System 1Ø
. m e IP/ST 4 designates an Interrupt Raquest or a Poll Test parity error, or an LCP status 4 line. In the unconnected state~ this line is used to carry an"Inter~lpt Request" from the LCP or else to indi.cate an address parity error during a "Poll Test" connection attempt. An Interrupt Request indicates thatan LCP is requesting access to Memory.
- 10 In the '1connected" statej this line carries bit 4 of the :; LCP's status to the Main System.
The ER/ST 8 designates "emergency request" or the LCP
status 8 lineO In the "unconnected" state, this line :. represents an emergency request from the LCP. "~mergency : 15 request'~ designates that an LCP needs i~nediate access to the Main SystemO In the "connected" state, this line carries bit 8 of the LCPs status to the ~lain System. Once connect~d, the LCP indio.~.tes its System ~lemory requirements by its status. The ~CP status is gated continuously and may only be considered valid by the System at ICP "Send/Acknowledge"
time O
~urther in FIG. 6E to the connections between the IOT
10t and the Distribution Card 200d7 the connections designated PARITY ~nd DATA l-xnl- re~er to the message level interface : 25 lines pre~iously discussed. The CS~ST 1 designates "Cha~lel Select" or LCP status 1 ~ine~ In the "unconnected" state, this lines carries "Channel Selectl' from the System 10 to -the Distribution Card. "Channel Select" is us~d in convunction :
with "address select" in bot~ connection algorithms~
.

106.
, However, in the "conrlected't state, this ;7ine carries bit 1 of the LCP's status to the Main System 10. This line, is a bidirectiorlal line,, The receiver on the Distribution Card ~ill be any standard 1~L, d~eviGeO The dri~er on th~
Distribution Card will be a tri-statc driver such as a 80C7/
809~ (National~Sem;corLductor Corp.) or eq~livalent whifh will , be active only in the conrLected state.

'The 'FRM. designates the "terrninate" level. This is sent ~rc,m the ~Iain System 10 to a Distribution Card when a data -transfer operatiorl is to be terminated.

~- ~ , The ADDSEL line of ~IG~ 6E designates "add~ess select". ~ -~his signal line inflica-tes t~at the ~5ai~ System is connectied~ ;

cr i9 attempting Gonnection to a speci~ic LCP. This line is ; used in conjunction with "Chamlt.l Select1' for both connectlon algorithms to ach:ieve comlection. Once a connection to the L'CP is~achieved, the System and LCP remain connected ~Lntil ,:, the signal line is inacti~ated by the System~ ~le~ the line is actlve, the System can be cGnsldered "b~sy".

Again ~eferring to ~IG. 6E, the AG/SIO ~esignates "acces.s ~ granted'7 or t'Strobe I/O". When~the interface is in an "unconnected state", this line carries an t'ac-,ess granted"

signal. "Access grante~" is used to aclcnowledge an Interrupt " !
Requ~est for~connectlorl and to begin a "Poll Re~est"
gOrlthm.~ ~With the interface in~a "oor~ected" state7 this ~ ~lina~ carrles a t'Strobe I/OI';sigl~al. 'rhis s;gnal is the System~'s 5end/~cknowledge line ~n transferring lnfQrmatlon between the System 10 and the;LCP Base Modulf~.; The~actual signal~ls a~10~0 nanosecond mln~imum pulse sent from the~
System~and~latched ky~the Distribution Card. The Dlstribution : Card will generally cl:ip the fi.rst 50 na.nos0conds from the si~nal to allo~ '~'or cable settling time.
In regard to FIG. 6~, the contrvl signals as between t~e LC7? ~000 and the periphera7. termi.na1. ~nit 50 indicate a line designated ~TLN~ This desi~lates Re~lote Data Line Le~el. This i9 2 bidirectional sig~lal level ~lish permits the transfer of ser.ial data between the LCP and tb.e periphera1.
termin~l unit in one direction or th~ other direction as deter~lined by the le~l~
.
Discussed here and below are the operational seque~ces of the LCP. ~e logic terms are re~erred to as ei.ther being active or iIIacti~e ii~ order to a~c.id ~r~ a~bi.guit~ that mi.~lt result from using tha terms True a}ld ~alse.
ec~ y~ e Contr_ Proce.~i~,or:
Previously in FIG. 6A~ tlle loglc flow in~ol~irlg tne 5tatus Counts.(STC) between the L~P 20 and the ~lal.~ Sy3tem o o lO was discussedO Now referring to FTG. 7A thgre ~ill be ~een in gr~ater detail a simplified ~low diagram illustratin~
the ~e~eipt of instructions by the I,CP. This ~'lo~ e~hal~t shows the hasic actions of the LCP durin.g receipt of instructions and also shows those actions which can occur ~ue to modi~icatiorl o~ the original instruc-tions~ the receipt s : of a time-out level, and the ~ccurrence of' error con~itions.
Prior to receiving any o~ the se~en possible instructions ~ from the~Main Sy~tem 109 the LCP i~ no~mal1y in an "~.dle"
state at Status Count 3. ~o~ever, t'ne ~CP can also be in a STC 3 during a "Rea~" operation, awa.iting either a ; conditional cancel instruction fro~ the Main System 10, or : : data tran5mls~ion from the peripheral te~minal unit, such as : 5~
' ~.' : .

10~ - :
i,l .

J
The ~ollo~iny ~ill descxibe the actions o~ the LCP
during receipt o~ instructions ~rom the System 10 and duriny preparation ~or the instxuction sxecution. These actions are itemized as Ca~ ~bl, and (c~.
~ a) System-LCP connection: with the LCP in STC 3, the System ma~es a connection with the LCP through a "Poll Test"
sequence, and the LCP xeceives. its uniquffs address level ~ LCPAD~ ~n~, as was illustrated in FIG.6E. The receipt of ;~ : LCPAD ~n) cau~es the LCP to send the LCP connection level (LCPCON,FIG. 6E) ko the associated Diskribution Card 200d and generates LCPADL ~LCP Address Levell, which "enables"
portions. of the LCP system logic section. The address level LCPAD Cn~ also enables the LCP backplane network by gener-' ating a gate system level~(GATSYS~. Then a strobe ~STIOL~ is , received ~rom ~he Distribution Card ~200d~ FIG. 6E)~causing S~IOE :(Synchronous Strobe ~lip-~lop~ to be se~. The set~ing : of STIOF activates:the~desired module of the LCP by 6etting :~ ~ RECVF ~Receive ~lip~FIop), enablfPs setting o~ ~h~ LPW
; :~ register ~24W/ ~IG. 6DI to logic "l's", and sets selected 2a ~ ~lip-~lops to a beginning state. The Command ~escriptor C~D
is received in the LCP and is loaded intf~ ~he~OP code regis-ter 42 and variant~register~s 43 ~FIG.6D). Receipt o~ the C/D~results in an LPW being plaoed into the LPW register 24w,.
The CjD~is~checked:~for~v~lidity and the~valid OP flip-flop OP~f~ is set~: The~LCP then steps rom STC 3 o~ér to STC 11 tFIG.:7~) to recel~e;an~ LPW ~rom the Syst~m 10. ~
b)~ Receipt of~LPW~by~the LP: In FIGo 7~ at STC~ll, a l~ngitudinal parlty ~ord (LPW) ifa received from~the System ID and i- checked againff-t the ccntent6 o~' the LPW~register , ~ . .

,f 24W to ~alidate longitudinal parit~ o~ the C~D trans~orO
~ertical parity is also hecked, then a ~ertical level OK.
(~LOX) and vextical parity OR level ~A~OKl is set~ The LCP buf~er address is preset to 253 in the memory address register MADR 36 ~FIG~ 6D~, and setting of the LPW register 24W to logic ~'l's'l is again enabled; than the LCP steps to STC 6 to receive the Descriptor Link D/L from the System 10.
c) Receipt of Descriptor Link and Descriptox Lin~ ~PW:
at STC 6, the LCP receives the two words of the Descriptor hink D/L ~rom the System 10 and a~ LPW is accumulated in the hP~ registe.r 24w. An .~PW is then recei~ed ~rom the System 10 and is checked against the contents of the LPW registèr i 24w. The Descriptor Link D~L and the LPW are stored in : bu~fer address locations specified by the memory address xegister.MADR 36 as addresses 253, 254 and 255 ~IG. 6CI;
: . Fro~ STC 6~ the h~P branches to ST~.8 for a "Wrlte" opera-: ~ tion, or to STC L ~or a:"Read" operation, or to STC 7 i~ a . ~escriptor Link error.occurred.
:
:~ ~ ~ There are alternate ~low path situations such as: (a~

; ~ 20 when a "conditional canceli' instruction is received ~rom the ~ ~ : : :
System 10, or (b) a data transmission is received ~rom the peripheral terminal unit, such a~ 50, or ~c~ a time-out level is generated, or ~d) a receipt of test instructio~ns.
To further amplify these.alternate flow path situations per ; FIG.~ 7A:~ (a) Receipt o~ Conditional Cancel I~struction: at STC 3, if a conditional cancel instruction is reaei~ed from he System`10,. while the LCP LS a~aitins a tr~nsmission from the peripheral terminal ~ it.50, a.cancel ~lip~flop CANCF¦~ is set and the L~P steps to STC lL to receive a 30 ~: Command Descriptor lo~gitudinal parity word, ~PW. From : STC ll, the 110~-~:: .

A~!3~

LCP steps to STC 7 and sends a Result Descriptor to -the System 10, indicatiIIg that the ca.ncel operation is comp].et~d.
(b) Receipt o~ Transmissioll f~om the PeripheraL Terminal Unit:
at STC 3 during a "~ead" op~eration, if ~he t~rmin~l busy ~lip-flop (TRMBSY~'3 is set9 indica-ti.ngr -that terminal unit has ~tarted transmit-ting, -the LCP steps to STC 1 to receive data from the periplleral terminal wnit. The LCP continues to receive d~ta and oompletes the remai.nder of the Read . operation in accor~anee with in.structioIls contained in the Command ~escriptor C~D.
~c3 Reeeipt of Time-Out Level: during a 'IRead" operation~
with t'ne LC~ in STC 3 awaitlnig a trall~mission from the peripheral terminal unit (and if the l-second ti~er i5 not inhibited) then if there is a l-second delay in recei~lng .the transmissio~, the tim~-out level (T~IOUTL) is gene~ated.
With T~IOUTL activet the end fllp-flop (ENDF) is ~et, the terminal complete (T~ICNP) level is geIlerated, ~nd the LCP
` steps to STC 1. At STC 1 a request for reconnecti.on to the ;~ System is init,iated and the l,CP steps to STC 5, FIG~ 7B.
~t STC 5 wlth END~ set, the Read o~eration is terminated and the LCP steps to STC 7 to send a Re.s~llt Descriptor, R/Ds 1;0 the System lO. A time~out level can al~o be recei~Jed ~i-~h -~e LCP at STC 1.
. - :
(d) :Receipt of Test Instructions: at STC 11, ~IG~ 7A,i:~
~, ~ ~ 25 TE5TF ~Test Flip-i~lop) is 9e t indicating tha~ a tes t ~ : ins~uctiGn was recei~red, the LCP complete~s the test operation :.. .
~y s~epping to STC 7 ~ and se:rlcling a Result Descriptor R/D ts~
he Sys tem 10 ~ ': , ~ .

:, .~ ''~/,' ' ~

, Error Conditions: the occurrence of two types of ~rror co~ditions (ea) and (e~) during the recei.pt of instructions will be acted upon b~ the LCP, as fol].ows. (ea~ Com~and ~escriptor parity er.rvr~ FIG. 7A, at STC 11, if the 5 . ~LOK (Validity Level OE) le~el is not active, or if ~OPF
(~alid Opera~lon Flip~Fl~p) is not set3 the LC~ steps to : STC 7 to send a Result Descriptor R~D contailling a dffscriptor error to the Syst~m; (eb) Desoriptor Link parity error: at STC 6~ if the ~OK level is not aetive9 the LCP
steps to s~rc 7 to send ~ ~esult Descriptor R/~ containing a Descriptor Link error to t~e System 10.
; W~ te O~eration-R~ferri.ng to FIG. 7B~ there i5 seen a sequential logic diagra~ whi.ch lS simpli~ied to show *he steps i.n~olved in the 15 : "Write" operation. Let us assume that one buffer load ~f . ~;;; data will be transferre~ from- the System 10 to the peripheral ~: terminal unlt 50, ~ollowed by a partial buf~er of ~ata : containing an endln~ cod~e character in the last character positiQn~(CD dijgits~ of a ~or~.
r The ~ollowing steps ~a thro~lgh i~ describe actions of the LCP, such as 200 ~ during transer of d~ta from the : S~stem 10 ov~r to the LCP, and f'ro~ the LCP to t~e peri~pheral : : : terDinal u~it, suc~ as 50.

(a):~Receipt of~dQta~rom system~ at STC 6) if a "Write'~

25~ operation is;speci~ied by~the Com~and DescriptQr C~, the .~
I.CP:e~able~s:the settln~ of th~ LPU register 24~ to logtc.

91~J th~n steps to sTa 8 to~ receive data from the Systs~ 10.

IOSF ;(I/G Send Flip-Flop)~is used and put`in a r~set , j $ate at ~his tlme to enable the ~idirectional ~ata lines ~/ ~

~ 112 -"~: ~ ..

for t.rans~er of data from the System 10 over to ~e LC~.
There are provided m~tltiple~or control levels SLAIN (Select A Input Multiplexor) and SLB~N ~Select B Input ~ultiple~or).
These are both inactive, connec-t~ g the data lines to the input multiplexor hetwork 24Xl of ~IGS. 6~ and 6D. There are other m~ll-tiplexor control levels SLAR~ Select A Level Terminal Bus Multiplexor) and SLB ~M (Term:inal Bus ~lultiplexor Select B Level). These also are both inactive, cvnnecting the input multiplexor network 24Xl to the input o~ the Terminal Bus Multiplexor Network 24 2.
At STC 8~ the Receive ~lip-Flop ~RECVF) is set, acti~ating the write module of the LCP. The setting of RECVF causes the write enable level (WES~S) for the LCP buf~er to be active.
Thus, data is transferred fro~ system ~lain ~Iemory 10 over 1~ to the LCP buffer 2500 ~ one word at a time, b~ way of the terminal bus ~7 of the LCP. An Asynchronous Strobe (STIOL) from the associated Distribution Card 200~ ~FIG. 6E) I accompanies the transfer of each word, and as each ~ord is . , recei~ed by the LCP, the LCP sends a strobe level (LCPST~) -to t~e System 10 to "acknowledge" receipt of the word. As each word is piaced on the terrninal bus ~7 then, in addition`to being sent to the buffer 25 ,it is also applied to the inpu-t of the vertical parity generator~checker 48, the LPW
register 24W and the end code decoders 52 and 35. Vertical parity is chec~ed and a longitudinal parity word is accumulated in the LPW register 24w. Transfer of w3rds continues until the next to last data wo~d address 251 is attained in the Memory Address Regis-ter 36. The LCP then steps -to STC 10 of FIG. 7B to receive one final word from . . ..

' ~ 113 - - f the System. At STC 10~ the LCP rece:;.ves -the final word to ~ill the buffer, a~ld then steps to STC 12 to receiveallLPW
~rom the Sy~te~l 10~
(b~ Receipt of ~PW an~ dlsconnl3ct from the Syst~l 10:
at STC 12, the LCP receiYe~c~ LPW fror~ the System 10 and c~ecks it again~t the LPW aceumulated in the LPW register 24W during the data transfer~ The I,CP then enables setting of the LPW regis~er 24 to logic "l's'l and steps to i-ts STG 1, di~connecting from the Sy~tern 10 in order to trans~er data to the peripheral terrninal ~nit, such as 50. Te~linal bus multtple~or con trol levels SLARAM and SLB~I (Select A
and Select B of 24X2) are both inactive t~us to connect the output of the bnffer 2500 with t~e input to ~he terminal bus multiplexor net:work 2l~ 2~ The input multiplexor 2~X2 has control levels S~AIN (Input Mul tiple~or Selec;t A Level) ancl SL~IN (Input Multiple~or Select B Levei) which will be controlled during the data tran~fer by the state of ~he evan flip-flop (E~NF) .in order to access a c:haracter alternately from the AB digi-t~ and the CD digits of a word in the b~frer 2500.
(c) Transfer o~ Data -to Peripheral Termina~ Unit. with ~urthar re~erence to FIG. 7B, at STC 19 the rgceive 41ip flop : (RECVF) is reset, thus enabling the recei~e module of the LCP~
~he terminal start le~el ('~ERST)~i.s generated to prepare the LCP ~or operation wit~ the peripheral terminal unit~ '~he , .
TERST le~el enables the set~ing of master cle2r UAP~T fllp~
flop~MCUARTF) in order to cIear the IJ~RT 31 (FI~ ~D~.
'~: ` ~he setting of a termlnal acti~e ~lip-~lop ~T~ACTF~1 a sen~
~lip-flop ~SENDF31 and the ter~ina~ ~usy flip-flop ~T~5~S~F,J
. ~ ~
' ~ :

~ ~ 114 ~

r~ r ~

are also enabled, activa-ting terminal control logic for a Write operation and specifying that the peripheral terminal Wlit i9 in a "busy" state. The M~mory A~dress Register 36 ~ (~IG. 6D) is set to M~DR 0 to access the first word in the bu~fer 25 . In the UART 31, the'transmitter holding ~ register empty"(lH~E) le~el.is active, and the setting of - the UART empt~ flip~flop (U~RTETF) is enabled to provide a ~trobe le~el to the UART multiplexor 27x.
The UART 31 accepts one char~cter at a tinte from the LCP buffer 2500. Ihe even flip-flop ~EVNF3 is used in c~njunction with the Memory Address.Register 36 to control accessi.ng of characters. When loaded with a character, the ~
UART 31 transfers the character serial}y o~er to the peripheral terminal unit, such as 50. As each character from the buffer 15 ~ 2500 iS placed on the terminal bus 47, it is also applied to the input of the block check character register (BCCR) 33, , whieh (after a STX/SOHyl'start of test/start of heading"
character has been received) begins to accumulate a bloc~
chec~ character during the data transfer. The U~T 31 continues to accept cha.racters from ~e buffer 2500 ~ th~n transferring them to the peripheral terminal unit 50, until : memory address le~el ~DR 252 is attained in the ~lemory Address Register 36, indlcating that the last word in the . buffer has been accessed.
~ ~ ld) Request for Reconnection to System 10- the memory address level MADR 252 causes the buffer transfer flip-flop B~XFR~) to be set, indlcating-that the buffer 25 needs se~Yice, and the LCP initiates a request for reconnection to the sy!tem by enabling~the se~ting of the LCP request flip~

.
A, .. . . .

flop LCPRQF. The setting o~ IOSF (I~O Send Flip-Flop which indicates the direction o~ data flow on the message level interface~ is ena~ied to condition the data lines for trans~er o~ data to the System 10, and the setting of MADR
253 level is enabLed to ~llow access to the Descriptor Link . D/L (FIG. 6C). The LCP then steps to STC S of FIG.7B to . send the Descriptor Link D/L to the System 10. There are . floating logic levels which generate LCPADL ~LCP Address - Level~ when the ~CP address levels (0-7), LCPADn, is received ~rom the associated Distribution Card during the reconnection sequencet and the LCP generates.a level called gate system ~GATSYS) to enable the backplane networkl The level LCP
s connected ~LCPCON~ is sent to the Distribution Card 20od to ¦ indicate that the LCP is connected.
~e) Tran~fer of Descriptor~ink and the Descriptor Link LPW: in FIG~ 7B, at STC 5, the transmit flip-flop ; ~ CXMIT~) is set, activating the "Read" module of the LCP.
, ,, The LCP trans~ers the Descriptor hink D/L and the ~PW
~previously received at STC 6) back to the System 10. The LCP enables the setting of the LPW register 24W to logic "l's" and if the Main System has more data to send, the LCP
. steps again to STC 8 to receive additional data from the . ~ System 10.
E~ R~ceipt of Addltional Da a and ~nding Code from . System 10: at STC 8, ~he actions of the LCP while receiving the "second" buffer load of data from the System 10 are the : same as those perfoxmed during receipt of the irst buffer ::~ , . :
. load, up to the point that an "ending code" is`recognized by the.termin~l bus 470 When an "ending code" in the lask ., ~
~ ~ 30 character position ~CD di~its) o a word is placed on the : -116- ~~~
, .~

terminal bu~ 47, t}l2n a system eZnd le~el ~SYSE~D) is generated. SYSEN~ le~el causes the data input for the end-flag 25e of E`IG~Z 6C ~RA~ 18 L) toZ be active and the - end-~laZ~ bit ~El~FG~ and t~e ending code character are both ~tored in the current buffer address. l~Le LCP then steps to STC 12 to recei~e an LPW from the S~rstem 10.
g? Receipt of LPW and Disco~ect ~rom System 10: at STC 12 of ~G. 7B9 the LCP receives the longitudinal parity word LPW and cheoks it against the LPW accwmulated in the ; LPW r~3gister 24w- The LCP then steps to STC 1, disconnecting from th~ System 10, to trans~er the remaining data and the e~ding code to the pe~ipheral terminal ur.it.
(h) Transfer of Data and Ending Code to Peripharal Terminal Unit: at STC I, the actions in trans-~erring ~he remaining data to the peripher 1 terminal unit are the same as those performed during transfer o~ ths first buffer l.oad~
up to the po:i~nt that an~'ending code~' i9 r~3cognized oll thé
~. :' . : ~
ter~inal bus 47. ~len an ending cod~3 is placed on a terminal bus 47~rom Z~hs output~of the buffer~29 , the~ending oocl~
is~trans~errsd and the end flip-~lop (ENDF) i9 set. ~1e~
ac~umulated block check character in ~he ~CCR 33 (if a BCC, ! . ~
` ~ : i9 bein~ generated) is then transferred to the peripheral : . .
;te~minal ~n~t such as 50~ ; SENDF (send fllp-f10p) and TRFZCF
(te~mina1~rec~sive f1ip-~lop~ars both in a reset state~
~;Z~ 2~ caus~ing~t~rminal complete ~(TMCMP~ level to be actiYe~ The te~m1na1 oomp1ste leve1 causss -the LCP to initiateZ a request for conneotion to the System 10.
Raquest for~Rsoon~eot1on to Term1n~ts Write Operatîon: ~the LCP réquests a reconnection to the System ~y ~-- .
e~abling the setting o~ LCPRQF (LCP Request ~lip-Flop). ~n con~unction with the reco~lection5 the LCP steps to STC 5 o~ FIG. 7B, sends the Descriptor Link D/L to the System lO
and then steps to STC 7 to send a Result Descriptor R/D to thé Sys-tem 10.
The above disc~ssion completes the explanation of the general flow path for a 'IWrite" operation in which more than one buffer load of data ~as transferred, and in whioh the opera$ion was concluded by receipt o~ an "ending code".
This describes the normal situation. However, there could be alternate flow paths and possible error conditions wllich might oecur as follows, in reference to ~IG. 7B. The followi~g items (a) through ~c~ describe the actions of the LCP when "modifications" to the original Write instructions are made b~ the System lO or the LCP.
(a~ Request for Emerge~cy Aceess to System lO~ during transfer of data fro~l the LCP to the peripheral terminal unit 50, when the LCP buffer 2500 is completely empty9 a flip-~lop BFXFRF is set. This is the buffer trans~er flip-flop which is located on the Terminal Card; this flip-~lop is set when the LCP bu~fer is filled with data from the terminal ~unit~ or when emptied of data during transfer of data from the LCP to the peripheral terminal unit. When BFX~RF is "
set9 this enables the setting of LCPRQF (LCP Request Flip-Flop5 which, when set, ~ndicates tha-t the LCP requires access to the Main System Memory lO ). The setting of the LCPRQF initiates a request ~or reconnection to the System 10 to either sand data to the Main System or to obtain more data if the buffer is empty. If a xeconnection is not completed priQr to the time the transmitter-holding register of the - .

- -- lll3 .
. ., ~ ' ' . .~,, J ~

UART 31 is ready to accept anothe-r character, the LCP c~u.ses the emergency reques t level (:SMRR~Q) to be gener~ted. The EMRREQ leve:L is sent to the associated Dis-tributioIl Card 20nd to initiate a.n emergency reqllest f`or recorlnection to the 5 sys tem .
(b ) Rece:ipt of Ending Code (A:B digits ): if an ending code is identified in the f`irst character position (AB digits) of a word from the System lO, then EDCODE (erld code level) is generated. EDCODE is generated on the terminal cor~trol 10 oard when an end code character is in the A ancl B digit5 of the terrninal bus 47. Also generated is SYSE~ID (S~rstem End Code Le~rel) O When active 3 the SYSEND level indicates th~t an end code charac ter is on the terminal bus 47. 4t STC 8, the EDCODE level en~bles the setting Or a character end flip-:f`lop 15 (CHARENF), ancl the SYSEND level :~,enerates the 18th bit Wri.ta end-f:~ag level 7R~ I8L. ~e "Write'l end flag level is generated on the te~inal control card from the EDCODE level; this is the data input level :E'or the end-:elag RAM of' the LCP buffer 25 l~he ending code and the ENDFG (end-flag le~rel is generated 20 on the data flow card from RAM 18 L, when active, ~his level identifies the address of an end code in the LCP buffer3 are stored in the current buff`er address o:f the LCP I and the LCP
iteps over to STC 12 (FIG. 7B) to receive a longitudinal ~ !
paritr word I~PWo At STC 12, the LCP recei~es an LPW from 25 the System lO and checks it against the acc~mulated LPW in th~I,P.-W~ ega~ster-.24 _~he_LC;e_i;he~steps ..to..STC..C`T to.
" .
`t ~ initiate decrement~ing Qf: the System Memory Address. (The address must be decremen ted by two digits to accurately:
: , ~:
re~lect the address o:E' the ending code in Sys-tem Memory)~
~ i :
:;~ :: ::
. ~

~ - 1 1 9 -,' ~ : , ~

~rom STC 9, the LCP ~tep~ over to STC 1 to tran~fer data and the ending code to the peripheral terminal unit 500 At STC 1s recQgnition of the ending code on the terminal bus 47 causes the LCP to perform the same actions described - 5 during the previo~s "Write't operation at STC 1 when data, çnding code, and block check characters are transferred to the peripheral terminal unit S0, after which ~e LCP disconnects from terminal unit S0 and rec~nnects to the System 10 and : termina~es the "~xite" Qperation. P
~ ~- 10 ~c) ~eceipt of Terminate Signal from Syste~ 10: a ;~ terminate signal (TERM lavel, FI~S. 6C, 6Ejis sent from the 5~stem 10 -to the LCP whenever System Memorr space designated ~or LCP operation is to be e2ceeded. During a "Write"
operation, the TER~I level can be received at STC 8~ STC 10, :15 . or STG 12, FIG. 7B~ -The actions o~ the LCP upon receipt of : the TERM level (Terminate Level) ~epend upon the Status Count in which the LCP is operating, and upon whether or not the .
receipt of TERM leve.l is preceded by a receipt of an nending coden from the System as follows:
~1) Receipt of Terminate Signal Before Ending Code:
i~ the TERM level is received at STC 8 or STC 10, the LCP
steps over to STC 14, At STC 14, regardlass of ~hethar TE~I
level remains active or is now inactive, the LCP steps over to STC 12~ receives and checks a longitudinal parity ~-ord ~PW, then steps o~er to STC ~ to send a Result Descriptor R/D:to the System 10.~ If~an ending code is received ~n the CD digits (last character) of a word at STC 8 or STC 10, and the TERM:level is also received9 the LGP steps to STC 14.
At the STC 14~ i~ the TERM level is still active, the ending ,. ..
` ' ' ` ' ' - .

~ 120 - - ` ` `: `

code was not placed in the LCP buf`fer 2500. ~he LCP then ~teps ko STC 12, receives and checksan LPW, then steps o-~er to STC 7 to send a Result Descrlptor R/D to the System 10.
(2~ Reeeipt of Terminate Sign~l After EIldi~g Code:
if ian ending code is received in the CD digits of a word at STC 8 or STC 10, the LCP steps to ~TC 12 to receive LPW. At STC 12, if the TERM le~el is now recei~ed, the ending code is transferred to the LCP bu~er 7500 and the LCP steps over to STC 1 to transfer remaining data and the ending code to the peripheral terminal unit 500 At STC 1, recognition of the endiIlg code on the terminal bus 47 causes ENDF to be set. (End flip flop: when set, thiC. flip-flop i~dicates that the terminal control sec-tion of the LCP has ended its operation~.
; The setting of ENDF indicates that there i9 no more data to be transferred; afker the data, ending code, and ~look check character are triansferred to the peripheral te~ninal unit 50, i the LCP disconnects from terminal:50, reconnects to the :~i Sy3tem 10, to terminate tha "Write" operation.
.c J AG; ill~strated hereinunder, at STC 1, the recognition Or the ending code on the terminal bus 47 causes the E~D~
i (end flip-flop) to be set~ The setting of E~DF indicates that there is no more data to be trans~erred; a~-ter the data~
~ : ending acde ~Id block check charaoter are *r~nsferred to the `' : periphera.l terminal ~nit 50, the LCP reconnects to the . 25 :Sycitem 10 to tel~inate the "Write" operation.:
'.1 :
n ending code i5 received in the AB digits of a :word a-t STC 8 or STC 10, and th~ TE~ level is also recei~ed, he ~CP step~ to STC 14. At STC 14~ if T~RM leve~ is inactive, the ~hole word containing the e~ding code in the ~ ~ .
, ,~ .

~ ~ 121 : ~ , ;~ ~

digi.t wa.s transfe~red to the LC~ buffer 2500 . A correction of System Memory Addres5 ls necessary. The LCP steps to STC 12, receives and check5 the LPW, then steps to STC 9 to initiate decrementing of the System Me~lory Address. The LCP
then steps to STC l to transfer data and ending oode to the peripheral terminal unit 50.
If the TE~M le~el was still activ6 at STC 14, th~n o.nly the ending code character was transferred to the LCX buffer 2500 and no correction of System Memory Address is required.
The LCP steps to STC 12, recei~es a.nd checks the LPW, then : .
~ ~ ~ steps directly to STC 1 to transfer data and the ending code ~. .
~ o~er to the peripheral -terminal unit 50.
Error Conditlons: During a "Write" operation the followlng error conditions (a,b,c,d) will be act~d upon by the LCP:
(a) Access Error: after transmitting EM~R~Q level to the assoclated Distri~ution Card, if the LCP does not receive ~:
a~rec.onnection~to the System 10 prior ~to th0 time the UART 31 :
is oompletely~empty, the~LCP~enables~the~:settlng of the~
access error~flip-flop:(ACCERF). The settln~ of ACCERF
20~ enables~settin.g of the end M ip-flop (ENDF), and the:LCP
~ initiates~a request for reconnection to thej System 10 to termlnate the~"Write" operation and to send an error ~esult ~:
Descrlptor~R/D to the System 10.
(b)~Sys~tem Vertical Parlty Error: durlng transfer~of ;
data::fro~:the;~Syst~em lO~to~the~:~CP, if -the vertical parity is-~no~ O.~ and--the-VPAl:~OK-leYel-ls-no,t~_active-~a~fter_eaFh~
check of ~ertical pari:ty, then the~vertical:pari~y error flip-flop (VPERF~ is set to indicate the exiqtence of a vertical paritr error~ The absence o~ YP~iRO~ level also prevents the vertical longitudinal OK le~el (VLOX) from being generated, and at STC 12, the LCP steps over to STC 7 to send ~n error Result Descriptor R/D to the System lO.
~c~ Lon~itudinal Parity Error ~FIGo 7B) ~hen the longitudinal parity word is checked after a data tr~nsfer ~rom the System 10 to the ~CP, if lon~itudinal parity OK
level (LP~K~ is not acti~e, the longit~linal parity error ~lip-flop (LPERF~ is set to indicate existence o~ a longitudinal parity error. The ab~ence of LPWOK level (the Lp-*r OIC level: i~ g~nerated on the data *low card from the terminal bus 47 levels; when active, it indicates to the System Logic Section of the LCP that the LPW is correct3 prevents VLOK level from being generated, anA at STC 129 the LC~ ~teps o~er to 5~C 7 to send an error Result Descriptor R~D to the System 10.
~d) Terminal Yertical Parity Error: during transfer o~ data from the ICP ~uffer 2500 to the UART 31, i~ the verbical parlty OX ~VPAROK) Level does not remain active for each character transferred, the terminal ver-tica? parity error flip-flop ~TYPER~) is set to indicate eYistence of a ertical parity err~r~ ~en the LCP reconnects to the System ~; lO and~terminates the "Wrl~e" operation, the Result De~scriptor 25 ~ X/D sent to the ~ystem lO at~STC 7 will indicate the parity error~ ;
,~

Re~erring to FI~o 7C ~ there i3 seen a simpllfied logic ~ char~t ~howing the "Read" opera~ion. A l'Read" opa~ation is : ~ : :
~ 123 _ generally accomplished in conjunction ~Jith some form of "Writel' operation. As an e~ample, assuming that a '7W:rite"
operation ha.s been completed and the peripheral terminal unit 50 has responded with an acknowledge oharacter (AC~), indicating that the peripheral te~ninal unit 50 is now ~apable of sending information~ Again, assuming there will be no delay in receipt of data fro~ the pe~ipheral terminal u~i* ~0~ and that one buf~er load of' data will be re¢ei~ed followed by a partia7 buf~er of data containing an ending code. It is al50 assumed that the end.ing code will be received in such a way that it wlll be placed i.n the last character pOsitio~ D ~igits) of a ~ord in the L~P ~u~fer ~500 (F~G- 6C)-General Flow Path: The following paragraphs (a) throu~h (l) describe the actions of the LCP during transfer of data ~ro~
the peripheral terminal unit 50 to ~he LCP, and also ~rom ~;' the LCP over to the System 10.
(a) Dis~onnect from Main Syste~ 10: referring to ~IG.
~' ~ 7~, at STC 6, when a "Read" i~lstruction is specified in the Cominand Descriptor C/D~ from t~e System~ the ~EADF ~read l flip-rlop: loca*ed on the data flow card; the logic state o~ the read~lip-flop is controlled by output le~els from t~e QP oode register; the set state of RE~F indicates that a ~Read" operatlon is being performed by the System) is set.
The L P enables set~ing of tne LPW register 24W to log.ic : rl'~", then step~ to STC 1, disco~necting from the System 10 .
` to recei~e data ~rom the peri.pheral terminal unit 50, The terminal bus multiplexor 24yz (FIG. 6D) select A le~el (SL~RAM) is active, and SLB~I, SLAIN and SLBI~ le~els are ; . .

, : :, .. . . .

inacti~e to pro~ide a path for data from the UART 31 over to the L~P buffex 2500-(b) Receipt and Storage of Dat~ :~rom Terminal Uni-t:
referring to FIG. 7C, at STC 1, with RE~D~ set, the termi.nal start (IE~ST) le~el is acti~e. Thi5 TERST le~el causes the U~T 31 to ~e master cleared and enables t'he set~ing of - T~RMACTF (terminal active flip-flop, located on terminal control card; the logic state of this flip-flGp is controlled by TERST, TRECF and SENDF; the set state of I~Cl`F indicates that the terminal con-trol sec~ion of the LCP has been acti~ated for a "Readl' or a "'Write" opera-tion) to acti~ate termlnal control logic. R~ADF also enables the setting of the termlnal recei~e flip-flop (TRECF) to allow receipt of data from the peripheral terminal unit 50. The buffer 2500 has its addres~
preset to MADR location 255 and if the e~en ~lip~flop (EVNF) .. .
i~ not alread~ .set, i~s setting is ena~led to'initiate control of'buffer addressing. Data characters are transferred seriallr from the peripheral terminal unit 50 to the U~RT 31 in the LCP, and the U~RT checks each character for e~en -~ertical parity.
(b l) ~ Receipt of First Character and Generatioll o~
}'; ~ ~ertical Parity. with the terminal recei~e flip-~lop (TRECF3 ~ set~ and the data store ~lip-flop (DAT~ST~),in a reset ~.
state, receipt of the first character causes the data 25~ raoeived e~el ~DR) to be acti~ ~e DR le~rel erlables j :
setting o:~ $he reset ~JART flip-flop ~RSUARTF~ and also the .; :
terminal busy fl:ip-flop (TRMEiSYF). The even flip-~lop, E~NF~
.i set, ¢ausing the buffer address to.be increme~ted tG MADR
;~ location 2. The settlng of t:he data store f:Lip-flop, D.4TA~5TF, . :' ~ ~ . .
:' ~
,, _ 125 ~ 1 .

*~

d the resetti~g of EVN~' are then e~abled, in preparation for storillg the $~irst character in th~ bu~fer~ With RSU~RTF
set, ~he SLAR~I le~el is generated ~ick places the first character on the ~H ~igits and also on the CD di~its of the terminal bus ~7~ forming a complete word. ~ parity bit is ~not included with this word~ The contents of the terminal bus 47 are applied to t~le vertical parity generator/checker 48 Of ~IGo 6D. Parity for the word on the terminal bus 47 i~ generated and a flip-flop, used to desi~nate odd ~er$ical parity is set or reset, as applicable to indicate parity, until receipt o~ a ~econd character from t~e peripheral terminal unit 50~
(b 2) Storage of First Character in Buffer: with the data ~tore flip-flop DATAS'rF set, the reset state of EVNF
causes the buffer ~rite enable A ~RWA) level to be active.
~` The System Write E~able~WESYS) le-vel is also acti;re, and - these two levels provide the Write Enable input for the AB
i and CD digits of the ~uffer network. The flrst character i~
therl stored both in the AB and the C~ digit locations of ~DR

' 20 location 0 of Memor~ Address Register 36. Transfer of the ,1 -,!~ *irst character from the U~RT 31 -to the buffer 2500 causes the reset UAR~ flip-f'lop (RSUARTF) to be rese-tr Thc data reoeive level ~DR~ is then made inactive~ ~ollowed b~ the resetting of DA~AST~ (Data Store Tlip~Flop~. This ~ combination o~ logic prepares the U~RT 31 to accept the s~cond char~cter from the peripheral terminal unit 50.

, (b~33 Receipt and Stora~e of Second C~aractar: when ~; the second~`cllaracter is received by the UART 319 the data ,, ~ ~ ~ receive level (DR3 is agaln made active and RSUARTF is set.
,: j :: :
~ lZ6 -This lngic in co~binatlon with the reset st;ate of' the even flip-flop ~VNF i-nhibits the buffer address fron~ being incremented. l`he Setting of the data store ~lip-flop DATA~'rF
and the even f]ip-flop EV~-F are then enabled in preparation for storing the second character in the buffer. The terminal bus n~ultiplexor select A level, SLA~M~ is still acti~e and the character is placed on both the ~B and the CD digits of the terminal bus 47. The contents of the terminal bus 47 are again zpplied to the ~ertical parity generator/checke~ 48.
Parity is generated for the word on the ter~inal bus 47 and is compared with the parity generated during receipt of the first character. ~`rom the results of the comparison, a single parity bit is generated for the first and ~econd characters.
With the data store flip-flop DAT~ST~ and the even flip-flcp EVN~ set, the ERWB le~el (Write Ena~le level for CD
digits of LCP buffer? is generated and the second character is stored in the last ch~racter position (CD ~igits) of buffer 25 at address location MADR 0, overwriting the : . o~
character previously placed there. The character on the ~B digits of the ter~inal bus 47 i9 no t stored in the buffer ` 250~ because the ERWA level is not; active ~EXWA is the Write ~nable level for the AB digits of the LCP buff`er). A parity ~ bit from the ~ertical parity ge~erator/checker 48 is added ; 5 to the co~plete word now contained in the Memory Address ~Register at MADR 0.
~b-4~ Receipt of Additional Characters and Start of Blcck-Check Character (BCC-j Accumulation: additional charac~erS
, ~` are accepted by the LCP. With the receipt of each character~

_ 127 -I
:- -- ~ .

the lo~ic stat~ o~ the even flip-~lop EVNF is complemented to cont.rol incrementing of the ~emory ~ddress Register 36, so as to place data intv the bu~fe:r 250~ in word formatO
With the receipt o~ the l'start o~ heading/star-t of text' character (SOH/STX) ~ro~ the peri~heral te~minal unit 50~
-the block check character regis~er 33 o~ ~IG. 6D is enabled and each character ~ollcwing the SOH/STX character is applieAd ~ to the BCCR 33 to accumulate a block check character BCC
for the message bein~ received. Accumulation of a BCC wi~.l continue throu~h receipt o~ the first buf~'er load of data and through receipt of succeeding buffer lvad-s o~ d~ta until the ending code (ETX ch~lracter).is received, The actions that occur when an ending code ls received will be described subsequentl~ hereinafter~
;` 15 . (c) Buf~er Filled: ~hen the LCP buffer 2500 ~ S
¢omp~.etely ~illed Inth data, the e~en ~lip-flop EVNF and the Memor~ Address MADR 252 level are se~ enabling t~le setting ~ : Or the bu~er transfer ~lip-flop (BFXFRF~. The setting of : BFXFR~ ind.icates thkat the LCP bu~fer ~500 needs ser-vice, and the LCP initiates a request for a reconnection to the S~rste~
10.
(d~ ~equest ~or Reco~ection to System lOs after dlsconnection, src 1, *he LCP ini.tiates a request for a . , reco~ne~tion to th~ Systern by enabling the setting o~ the LCP requ~st ~ flip-:~lop LCPRQF. I~e set tin,g of the I/O send f~lip~flop ~IOSF3 is enable also, to condition the data lines f`or trans:~er of data to the 5ysterr 10~ and ~ the sett;ing 4f ~the Memory Address Ma~R 253 (FI~ 6C) is en~b]ed to al 1 ow access to the De3cripto:r l.inX D~L~ he T CP then steps to : :~ :

~ 128 -- - ~
3~

' STC 5 to send the Descx~tox Link D~L and the LP~ to the I S~stem 10.
The term M~DR re~Prs to Memor~ Add~es~ levels. These are generated on the Terminal Cc,ntrol Caxd ~rom outputs of ~he Memory Addrass Register 3~. These le~els represent address locations, shown in Table XI, in the LCP buf~er 25oo (FIG. 6C) which are reserved for the following:
TABLE XI
Location Description .
251 Next~to-last data word - 252 Last data ~ord 2$3. Descxiptor link in~ormation word 1 254 Descriptor link information word ; ~ 25S Descriptor link ~PW
¦ When on~ of the eight hCP address levels, LCPADn~ is xeceived ~rom the associated Distribution Card 20Od during he reconnection sequence~ then the LCP addres~ leve~, ., , I . .
i LCPADLt is activeO The hCP~DL address level i5 generated ¦ on the Terminal Control ~ard when the app}icable LCPADn ¦ - 20 . le~el is active~ The LCPADn level also generates the gate I system level, GATSYS/ to enable the LCP backplane network.

¦ The ~CP connected (LCPCON) level is sent to the Dis~ribu-~¦ ~ tion Card 20Od to indicate that the LCP is recsnnected.

The SLAIN level is acti~e and the SLBIN, S~ARAM, and khe ~: SL~RAM levels are inactive in order to allow th~ Descriptor Link D~L to be transerred to the Latch Register 49 ~PIG.6D~.

:: ~ 30 : . .

:: ~ , , . 1 ~ ' ' ' ' .

~ .
.i \~

q~

te~ Tx~ns~er o~ Desc~i;ptox hink D~L and khe Descriptor Link LPW: in FIG. 7C~ at STC 5, the transmit flip-10p ~XMITFI is set. ~he transmit flip-~lop is locat ed on the System Loyic card and the set state indicates : that the LCP lS transferring data to the System 10~ thus, actiYating the "Read" ~odule o the LCP. LCP transfers - the DPscriptor Link D~L and the longitudinal parity word LPW (previously received-at STC ~) back to the System 10.
The LCP then enables setting of the LPW register 24W to logic i'l's", and staps to STC 4 to transer clata to the System 10.
i (f~ Trans~er o Data ~o System 10: at STC 4 of FIG.
7C, the transmit flip-~lop ~MIT~ and the I/O send flip-flop, . IOSF, are still in the "set" state ~rom the operation at ~ STC 5. The asyn~hronous strobe ~lip-flop ~SYNCF~ is sét ; to enable asynchronous t~ansfer o~ data to the Syst~m 10.
Data is transferred from the LCP bufer 2~oo, by way o~ the ,, ~
:. : ~ data latch register 49 ~FIG. 6~ to the System 10 ~via the system interface 22si o~ FIG. 6C~. Transfer is accomplished one word (plus a parity bit) at a time. The ~CP strobe , I
level LCPSTL accompanies the ~rans~er o each word, and as , each word is received by the System 10, the System sends a strobe pulse to acknowled~e re~eipt of a word. Each word ~ placed on the terminal bus 47 of FIG. 6D for transer to - the System 10 is ap~lied simultaneously to th~ latch regis-ter 49 and the ~PW register Z4w~ The LPW register 24W
: 1 accumulates the longitudinal parity word LPW during the data trans~er. When the last data word address of the LCP

~ ~ buffer~2500 lM~DR 2S2) is attainedl the synchronous flip--: 30 flop ~S~, which is located on the Terminal Control Card .
: and is set when the LCP is al50 . -130-,, ,.

s1~

transferring data to the peripheral ter~llnal unit3 is set, resulting in the d0~elop,nent of the synchronous level, S~L, and thei~ the LCP steps over -to STC 12 to send an LPW to the System 10.
(g~ Transmission of Longitudinal Parity Word to System 10: in FI~, 7C at STC 12, the LPW accllmulated in the LPW
register 24W during operation at STC 4, is sent tv the System 10. The LCP then enab~es settin~ of the Lp~r register 24 to ~ogic ~17sf' and steps to ST~ 1 to receive additional data from the peripheral terminal unlt 50 (~ia the terminal ~Init .
de~ice interface 22~i of FIG. ~C), A~ter this, the LCP
steps to SI'C 5 to send a Descriptor Lin~ to the Main System 10.
:, .
(h) Reoeipt of Additional Data and Ending Code from 15 ~ Peripheral Termi~al ~rlit:~ upon the second entry to STC 1, a terminal acti~e flip-flop (T$~Cl`F) ari~ a t~rminal receive llp-Plop (TREC~) are both in a set sta~e ~rom the pre~ious -~ operation at STC 1. I~le: berminal receive flip-flop TRECF is ~ located on the terminal control card and this flip-flop is , set when the LCP i9 recei~ing data from the peripheral terminal unit; the terminal active flip-~lop, T~L~CTF, is also located on the t rmlnal~control card and, in its set state, indioabes t~at~ ~he terminal e~on-trol seobion of the LCP
has been activate~ for a~i'Read" or "Write" oper2tion, The ~ L~P bu~fer address is again set to MADR 255 in preparation for:receipb~of data fro~the perlpheral terminal~unit 50.
At ST~: 1, bhe~ actions of the L5P~while re~eiving ;the second buff~r~load of~data from the peripheral terminal ~it 50 : : :

. :

:~ :

are the sarne as tho.se perfo~ed duriII~ the :receipt of the first buffer load, up to the point that an ending code is receiv~d Oll the ter~inal b~ls 47.
Assuming that prior to receipt of the end Godeg at STC
1, that the following two conditions exist~ VNF ls reset, indicating that the ne~t character to be received will be placed i.n the last charactex position ~CD digits) of a word; and (2) both ~SUARTF ~Reset U~T Fli~-Il.op) and the data store flip-flop (DATASTF) are reset. ~hen the ending cod& character is received, RSUARTF is set, providing the necessary logic level to generate t.he Write Enable ~ERW 18) level for the ending oode RAM. ~eceipt of an ending code is recogni~ed by the LCP wllen the character is on the terl~inal bus 47. Recognition of the ending code causes the end code level, EDCODE, to be g~nerated, which develops the data input level (R~l 18 L) ~or the ending code RAM; the end~flag bit (FNDFG) i5 then s~ored in t~le present buffer address o~ the bu~fer 25 . The setting of EVNF and DATAS~F is then enabled 3 which conditions th~ LCP to store the ending code i.n the buffer 250~. With EVN~ set, the ERI~
~Write Enable le~el for CD digits) ~evel is acti~e ~md the !~ .
character is stored in the last character position o~ the same word adclress in w..hich the end-flag level, ENDFG~ is stcired.
~ ~.
~5 ~ Check of ~CC and Request for Reconnection to . ~ ~ Systsm lO~ with DATASTF ~et~ the EDCODE level enables the .: setting of the end ~lip-flop (E~DF). ~he LCP now receives a block check charaote~ ~BCCj from the peIipheral terminal ~ ~ ~nit 50 anA chac~s it against t~e acc~ulat;ed ~C~ in the , 'i ~ 32 - .

D' .~

block check character register 33~ The setting of the.end flip-~lop ENDF c~lses the terminal recei~e ~`lip-`10p ~RECF
to be reset, and tha ~ernl:inal complete level (l~lCMP) to be acti~e, tenninating the actions o~ t~e te$min~1 control section of the LCP; The LCP then initiates a request for a reconnection to the System and steps ~ro~ STC 1 to STC 5 to se~d the Descriptor Link D/L to the System 10.
(J) Transfer of Desoriptor Link D/L and the Descriptor Link LPW: as in the pr~ceding recon~ection to the S~stem, at STC 5 $he LCP se~ds the Descriptor X,ink D/L and the LPW
to the System, and then steps to STC 4 (Re~d~ to trans~er data to the 5ys'e~ 100 (k) Transfer of Vata to System 10: at STC ~9 the actions of the~LCP are the same as described before at STC 4 J until the word containing the ending code character is placed on the transfer bus for transfer to the Syste~ 10. ~ecognition ; ~ of the ending code causes the System anA l.evel ~S~SEND) $o be developed~ and the LCP steps to STC 12 to send an ~PW to . the System lO.
~13 Transmission of ~PW and Result Descriptor R/D to System lO- the I,CP sends the LPW accumulated i.n the LPW
register 24.~ to the System 10. After the LPW is sent, since the terminate complete level (TMCMP) i5 now acti~e, indicatin~
that there is no more data to be transferred, the LCP steps ~ I
to STC 7 to send a Result Descriptor R/9 to the System 10.
.~ At STC 7, the LCP sends a Result~Descriptor R/D to the System 10, then steps to STC, 15 (FIG. 7D~, and .sends an ~PW, : then returns~to id~s at S~C 3 to awai-t another inst~uction .
from the System lOo I
The abo~e discussion has in~ol~ed th~ general flow path -~ for a "~ead" operation ~n wh~ch more than one buffer load ofdata was transferred from a peripheral to -Whe Main System, s~ and in Wh~ch the operation was concluded b~ receipt o~ an ; ` ending code.
~ - However, during a "Read" operation, other situations may .
~ccur to cause alternate logic flow pa-ths and the handling of possible error conditions. The followiny sections ~a) ¦ through (d) indicate the actions of the LCP when modification~
~ , 10 to the original "Read" instructions are made either by the .:.:: ~
System 10 or by the LCP:
a) Receipt of Time-Out Level: referring n~w to FIG.
i 7E, which is made of two sheets, 7E-l and 7E-2; at STC l, with ~ operation of the one-second timer not inhibited, and data being .',, ~s' received by the LCP from the peripheral terminal unit 50; if the sen~ing of data i5 interrupted for a period of one second, the time-out level (TIMOU~L) is generated. With TIMOUTL active, the end fIip-flop (ENDF) is set, and the terminal complete level (TMC~ ) is generated. A request for reconnection to the System 10 is initiated and the LCP steps over to STC 5.
At~STC 5, with the end fllp-flop (ENDF) set, the Read~opera tion is terminated and the LCP steps over to STC 7 ko send a Result Descriptor R/D to the System 10. A time-out level can also be received with the LCP at srrc 3 as can be seen in FIG.
7E at STC 3 "idle~status".
(b) Transmission Still Expected from Peripheral Terminal Unit: In FIG. 7E, at STC l, with the ~CP conditioned to receive data from the pexipheral terminal unit 50, then if : . , ~: : i, ............................................ .

data is not being leceived, the LCP staps ilmmediately to STC 3 in order -to be in a condition to receive a conditiona~
cancel instruction . rom the System 10. The LC:P will return from STC 3 over to STC 1 if a data transmission bagins.
(c) Request for Emergency Rec~nnection: during transfer o~ data from the peripheral termînal unit 50 to the LCP, w~en the bu~fer 2500 iS completety filled~ a buffer transfer flip-flop (BFXFRF) is set9 initiating a request for a reconnection to the System 10 to stora data. ~The buffer ;1~ transfer flip-flop (BFXFRF) is set when the LCP bu~fer 2500 is fllled wit:h data from the peripheral te~linal unit 50, or when emptied during transfer o~ data from the ~CP to the peripheral terminal unit)~ If a reconnection is not completed prior to the time the UART 31 receives another ; ~15 character, the emergerlcy~re~uest le~el ~E~ is generated.
The EMRREQ l~evel lS sent t~o the~associated Distriblation Card 200q to inltlate an emergency request for a reconnQotion te ;~
the System~10 d) Receipt of Ending Code (AB digits): the actlon~
20 ~ o~ the LCP~rela-ti~g to receipt o~ an~ending code~ ~hich will ~ ~ -~e plaoed on the AB digits (first charactar) o~ a word,~ are ~ore ~arl~d ~than those involved with recaipt of an en~ln~
code to be placed on the CD digits of a ~ord~ ~is condition exists~because~a transmi~s3ion from~the~perlpheral term~nal 25~ unlt~may con~6ist of data~followed by an ending code, or it may~consis~t~merely of an ending code by itself`. Additlonall~, de~ore~entine~of the Sys~em Memory Address may or may not ba required~when~;storing the ending code, in order to;re~lect the aocur~ate locatio~ of the ending code in System Me~or~ l~O

.

V ~
Thus, the ~ollowing ~ctions o~ the LCP ~o~ these ~axious conditions are discussed below in paragraphs dl and d2:
tdl) Receipt of Ending Code ~ollowing D~ta: i the ending code follows a series of data characters and is re-ceived on the terminal bus 47 whenthe even ~lip- flop ~WFl is set, the character, when stoxed, will be placed in the ` ~B digit position of a woxd in the hCP bu~ex 25~o. When the character is ~eceived, the end ~ode le~e:L ~EDCODE~ is generated, càusing-RAM 18 L ~Write end-1ag level) to be active, and the ~nd-flag level ~END~G) is stored in the pres~ntly current buffer address. ~The end code level ~EDCODE) is generated on the terminal contrQl card when an end code character i~ in the A and B digits of the terminal bus ~7. The end-flag level, E~DFGt is generated on the ~` ~ data flow card from RAM 18 L, and when actiYe, this level : .~ - ide~ti~ies the addr ss o~ an end code in the LCP buf.~er ¦ 2500. The write end-flag le~el ~RAM 18 L~ is the data.
input level for the end-fLag RAM of the LCP buffer 2SoO).
. The s~t state o the even ~lip-flop ~EVNF) then causes : 20 the bufer address to be incremented to the next word address. The setting o the data store flip~flop ~DATASTFI
: ~ and the complementing o~ the~even flip-flop (EVNF~ are then ~ enabled. With EVNF reset, the write enable A ~ERWA~ le~el is generated and the ending code is stored in the AB digits of the buffer address following the one in which the end-~lay level ~NDF~ was stored. ~he hCP then initiates a requP.st for reconnection to khe System to transfer data and ~the ending code to.the Main System 10.
~During transfer of final data from the LCP buffer 2500 .~ ; 30 to the System 10 at STC 4, an ending code :in ~he AB digits ` . .

: . ~136 '~
'.1 ;~ 'X

of a word wil.l be recognized when ENDF& (end-fl.ag level) level is acti~e and the system end code level ~SYSEND) is inac-tive. Thi5 lo~ic combination in.di.cates that the next word to be transferred corltai.ns an endin~ code irl the ~B digits. In FIGo 7E, the LCP _:teps to STC 14 to accomplish transfer of a single character. At STC 14 the setting of a . word transfer control flip-flop (WTCF) is enabled unconditionally. The settin,~ of th~ character trans~er flip-flop ~CTSE) is enabled to specify that the character transfer state was entered. Ihe ending code is stored in System Memory 10 , and the LCP steps firct to STC 12 to send ~
longitudinal parity word LPW to che S~r5teln 10, then steps over to STC 7 to send a Result Descriptor R/D to tlie System 10.
(d2) Receipt of EndiTI,g Code Only: as per ~IG. 7E, at STC 1, ii the transmission from the peripheral terminal unit 50 consists of a single character (end code), it will :, ~; be received on the teIminal bus 47 with the e~en ~lip-flop ~ EVN~ in a set state, and will be placed on the ~B digit .~ ~ position of a word in the ICP buffer 2500- The chara-ker ZO , i5 stored and the LCP initiates ~ request for reconnecti.on .
to the System to tral~sfer the character, as seen in the 3rd '. block of ~IG. 7E at STC 5. This steps over to STC 4, and with the end code level (EDCODF) acti~e, the setting o* the character end flip-flop (CHA~ENF~ is enabled. The character .;, ~ .
25~ is transferred (STC 14) to rhe System 10 and the LCP steps over ` to STC 12 to send a longitudinal pa~lty word (LPW) to the S~stom 10. ~At STC 12, l;he set s-cate of CHAREN~ ~the character nd :~lip-flop) caus:es the LCP to st.ep directly to STC 9 to ~: in~`tiate decremeIlting of the System ~le~ory Address 10~.

~ ~ , .

.
~ ....

I Then the LCP steps to STC 7 in o~der to send a Resul t Descriptor RjD to the S~stem 10.
~ e) Receipt o~ Terminate Signal ~rom S~st~m: a terminate signal ~TERM level~ i.s sent from tha System to the LCP during a Read opexation whenever a~ailable system memory space designated or the LCP operatio~ is to ~e ` exceeded. During a RPad operation, the TERM level may be ~:~ received ~FIG. 7E) at STC 4, STC 14, or STC 12. The actions : of the LCP upon receipt o~ the TERM le~el depend upon the status count in Which the LCP is operating when the TERM
: level is xeceived, and upon ~hether or not the receipt of the TERM le~el is preceded b~ the receipt o~ an ending code ; character from the peripheral terminal unit 50. Under these . . ~ . .
: . conditions, the actions of the LCP are discussed in the :~ . following paragraphs el~and e:~
:~ ~ el)~ Receipt o~ Terminate Sign~l Before Ending~Co~e ~ ~ ~ is Received: i~ the LCP xeceives the TERM Cterminate sig-nal~ level from the S~stem before it has ~u~fiaient time to rece~iYe:and store an ending code, the LCP then acts as : ~ 20 . follows~
el (al The receipt o~ the TERM leveL while the hCP is ~, trans~errin~ data~to the System at STC 4, causes the term-:~ inate;flip-~lop ;~TE~MF~ to~be set, and the~LCP steps over to STC~:;12..~ A~ longitu~inal~par~ity~word ~PW is~sent to the S~ste~ and the:~set~state:of the terminate level (TERMF~
causes~the LCP to~:terminate~;the ~ead opera~lon and step over ; ; to STC~7 to send a Resul~t Descriptor R~D:to the System 10.
el:lb~ In FIG. 7E,~:~the ~CP steps from STC 4 over to STC 12:after transferrinq a:word containlng an ending code :: ~ 30 ~ in the~CD;digits over to the System 10. If~the TERM level :~ is no~: :
: ~ -138-: ; :' :
received at STC 12, the setting o~ -the word transfer control ~lip-fl op ~WTCE) ls enabled, and the LCP remains in STC 12 for an additional strobe time~ If durin~ the secoIld strobe time, the TE~M le~el is ~till acti~e, t~is indicates that the ending code was not transferred~ The setting of TERMF
~ ~terminate flip~flop) is enabled and the LCP steps over to Sl~ 7 to send a Result Descriptor R/D to the System 10~
el (c) ~-e LCP steps from STC 4 o~er to STC 12 when the la~t word i~ the buffer 2500 has been transferred. If the T~RM level is no~ recei~ed at STC 12, the ~CP re~ains in STC 12 for addit}~nal strobe time. T~e word transfer control ~'lip-flop ~w/rcF) is sat ~nd regardle.ss o~ the,loglc state of the T~RM le~el during the second strobe tlme, th~
LCP terminates the Read operation and steps over to STC 7 to send a Result Descriptor R/D to the System 10.
el (d3 ~ The LCP will be in STC 14 i~ the last data ~ord trans~erred at STC 4 is~to be followed by an ending~ `
code in thé AB dlgits of the next word. If the termil~ate (TERM~ level lS now recelved~at STC 14, the ending code is ~ ~ not~ stored and the LCP steps to STC 12, it sends an LPW to the Sy3tem, alld then steps to STC 7 to send a Re~ult ;~
Desoriptor R/D to the System 10 4 eZi ~ ~Raceipt of Terminate Signal After Ending Code is Received: ~;if the T~cp;~receivas~the terminate level (TERM~
25~ f~om the Sy~-tém 10 a~ter an endin~ code has been recei~ed from~the~peripheral ter~inal unit 5Q, then thè LCP acts as shown in~ the~ followin6~::paragraph3 eZ (a) ? e2 (b), e2 (c) e2 (a~ - ~I~ FI~. 7E, the LCP steps from STC 4 over~to T~12 after trans~er~i;ng a word~containing an ending code 139 =
: .

in the CD digits to the System 10. If the TERM l~vel. is now recei~ed at STC lL2, the set ting o~ the word trans~er control flip-flop (WTCF) is e:nabled and the ~CP remains in STC 12 for an addit:i.ona~ 3t~0be time.. I.f cll~ring t~.Le second strobe ti~ne, the TERl~ level is no lo~lger active~ this i.ndieates that the ending eocle was transferred. The LCP
then steps o~er to STC 7 to send the :Res~ t Descriptor RjD
to the Sys tem lC) .
e2 (b) ~he LCP steps from STC 4 oYer to STC 14 if the last word -transferreci at STC 4 is to be :~ollowed by an ending code in the A33 digi ts o* a word. If the LCP
progresses throu~h STC 14 without recei~ring the TER?I level, the ending code i~ trans:f`erred to the Sys tem 10, ancl the LCP steps over to STC 12 to send a long;.i tu~linal parity word I~PW. ïf the TERM l.evel is llOW receiv ed at -the STC 12, the LCP takes no action ~lpon its receipt, but steps to STC 7 to send a Resul t Descriptor R/D to the System lOo e2 (c) Xf a transmlssion from the per~pheral terrninal ~it 50 consists of a single cha:racter (ending code)7 then 23 ~t STC 4, the ICP enables the set-tîng of ths character end flip-:lop (C~IARENF) and steps over to s~rc 1~ to send a ~: ~c>ngitlldiIlal pari ty word LPW. At ;,TC :12, i ~ the TERM level ~s ~ow received~ the LCP will re~main in STC 12 for an additional s trobe time . If during the second strobe time 7 ~. ~
2S : the T~M level i.s ~till acti~e 9 th.is i.ndicates that only he first half of the word contain ing the endi~g code was tran~ferred and the System M. mory .~ddress was :no t incremented to the n~3xt word a~lclres5. ~he LCP steps ove~ to STC 7 to send a Res~llt :i:)escriptor R/D to the Sy~sterQ lt:~ If the ~ f , _ 14~ ~

le~el is inactive ~uring ~he second strobe time, this 'ndicates thal the Syste~ Memory Acldress ~as incremented to the next word add-~ess and requires decrementing. The set sta-te of the character end fl.ip-flop (CHARE~F? ~n~ the i.r.active s~ate of the terminate leve:L ¦T~RM~ cause the LCP
to step o~er to STC 9 to initiate decre~enting of -the System ~Ie~ory Address~ From STC 9, the LCP steps o~er to STC '7 to send a Result Descriptor R/D tQ the System 10.
Frror Conditions: ~urlng ~he COU'Se of a "~ead" operation, c~rtain error co~ditions may occur ~hich ~ill be acted uyon by the LCP, as follows:
(a) Access Error: after trans~itting the emer~ency request (EM~REQ) le~el~ if the LCP has not received a reco~nection to the System 10 prior to recei~ing a s~cond : ~ 15 character in the UART 3 , the UART 31 generates " level calle~
overrun error level ~oE3. T~e OE le~eI callses the enabIing of the access error flip-flop (ACC~,RF) and of the end flip~"
. ~ flop (E~DF). The LCP then initiates a request for ~ reco~lectl.on to the SysteI~ 10 ~o terminate the Read oper~ion .~ 20 and to send an error Result Descriptor R/.~ to the Syste~. 10.
(b) T~rm.inal Vertical Parit~ Error~ d~lring ~ransf0r of : ~ data from the U~RT 31 to the LCP buffer ~50~ t;he pca~ity ;~ ~ error le~el (PE) is generated by the UART 31~ the -terml~lal : ~er~ical parity error fIip-~lop (IYPE~F~ is set to in~ica-te : 2$ existence of` a Yertical~pari-ty error. This flip-~lop~T~FEXF~
ha~ a l~ogic state which i9 controlled by an outp~-t fro~ ~he : LCP vertica~ parity generator/chec~er 4S~ or ~rom the parity : ~rror outpu-t:of the UART 31 ~FIG. 6D). '~le set state of the flip-flop ind.icates t~t a vertical parity error occurred .. . .

:
;; :
~ _ ~41 --t during the transfer o~ data between the LCP and the peripheral terminal unit 50. This ~lip~flop is located on a Terminal Cont~ol Card.
~c~ Block Check Character Erro~. during the trans~er of data ~FIG. 6D~ from the U~RT 31 to the LCP bu~er 2~o~, if the block check character OK level CBCCOKI is nok active a~ter the block check character has been check~d, the block check character error Elip-~lop ~BCCERF) is set to indicate the existence o a block check charactex error. The BCCOK
level is pro~ided by decoder 34 of the block check charac-ter register 33 in FIG~ ~D.
~rite Flip-Read Operation:
This operation is essentiall~ a Write operation follow~
ed by a Read operation . . Basically the previous discussion regarding the "Write" oparation and the l'Read" operation o~
..
¦ FIGS~ 7B and 7C are applicable here. ~he receipt of a Command Descriptor C~D ~or t~e "write ~lip read" operation into the OP code and the variant registers 42 and 43 ~FIG.
i 6D) respectiveLy, causes a "Write" operation to be initia-! ~ ~ed and a F1IP level ~lip Level) to be ~enerated~ Data i~ transerred rom the System 10 to the peripheral term-~ înal unit 50 durin~ the "Write" portion G~ the operationO
~hen an ending code is recognized on the terminal bus 47 during data transfer ~rom the LCP to the peripheral term~
inal unit $0 at STC l~ ~IG. 7C) then the end code le~el ~EDCODE~ is generated. The EDCODE level enabla~ the set-ting o the end flip~flop (END~) indicating that the data ~ :
transfer is complete, The set state of the end flip-~lop ~ (ENDF~ and the generation o~ the F~IP level enable the ., : 30 setting o~ the read ~lip-~lop ~READ~, ~: -:
~ ~1~2~
''~ :

..

J . . _ the terminal xecei~e ~lip~lop CT~EcFl~ and the even ~lip-flop i~EVNF~, the resetting of the write ~lip-flop ~W~XTF~, the terminal busy ~lip-~lop ~TRM~3SYF~, and the presetting of the buf~er address to MADR 255. With thase actions the LCP is conditioned to xeceive data from ~he peripheral term-inal unit 50, without reconnectirlg to the System 10 to receive addition~l instructions.
To initi~te ~he "Read" portion o the ~rite-~lip Read operation, the LCP do~s not reconnect to the System 10. As pex FIG. 7E, ~rom STC l, the LCP steps over to STC 3 to await a transmission from the peripheral terminal unit 50.
Receipt of the first chaxacter ~om the pexipheral terminal ~ unit 50 causes the DR le~el (Pata Received) in the UART 31 j to be acti~er enabling the setting o~ the reset UART ~lip-~lop (RSUARTF) and the terminal busy ~ flop ~T~MBSYFl.

The setting of the terminal busy flip-flop causes the LCP
. ~ . , .-................ to return to STC l to receive the data. The "Read" operation progresses through to completion, sub~ect to the same cond~
itions discussed previsollly or a regular Read operation.
¦ 20 Test Operation: The "test operation" proYides the System 10 I with the capability for determining the operational status ¦ of the LCP without requiring a.transfer of data to or from - ~ the System ~emory 10m. Located on a data flow card is a test ~lip-flop ~TESTFl. The logic state of this 1ip-flop :: is controllea by output levels fro~ the OP code register 42, : ~ FIG~ 6~ The set state indicates ~hat a test ins~ruction was received fxom the System 10. In FIG. 7E, at STC 11, with the test 1ip-flop i'TESTF~ set, the LCP has no require~
;j ment tij step 'to STC 6 to receive a Vescriptor hink D~L.
`J 3~ It steps :: : ~143-;~
.

1 .
,;

5~ .

instead to STC 7 to return a Result llescriptor R/D to the System 10. From STC 7, the LCP stfrffps o-ver -to STC 15, and then STC 3 (idle) ? -~here it remains until another Command Descriptor C/D is recei~ed. Undffar normal conditions, the ;. 5 Refsult Descriptor ~/D sent to the.System lO ~ff~r a "test operation" wlll ha~frff~f all bits equal to zero. ''rh~ef System 10 will recognize, by th~.is condition, that the lCP is oper~tional.
'Test Enableff Operation: The recefipt of a Command Descriptor : C/D cefntaininfg a 'lte~ enable" instI~uction conditions the LfCP
so that the pe~ipheral terminal unit 50f can initiate a co~munication ~ith the System lO. The perip~eral terminal unit:50 initiates a request for co~mun~cation by sending ~n inqui.f.~ character (ENQ) to the LCP. Upon rcffceipt of the ; inquiry character ~EN'~2), the "test enable" operation is ~ 1$ terminated and the SySteM inltiatefs a "Read'7 operat-~on to reo~ei~0~data from the peripheral ~ermlnal unit 50.~ If the:
terminal unit~sends any~other character but an ~NQ inqulry character, t~e:character~;will not be recogni3ed and the LCP
will take no~aotion. 'The "test enablff~f~ operation operates 20 ~ in referance to FIG. 7E~ as follows:
~,! A t sffrc 3, upvn receipt of a "test enabffle" instl~ction the variant~ reglster ~].ip-~lop ~Off~ 3 ~YAR3F) is set. The~
"~AR (l-4) Fi':represents~the~4 vari~lt register levels.
Ihese~ are~ ge~-erated on the Data:FloY Card by outputs of`~thé ~ :
:25~ variant regi9ter 43~ FIG.:6D. :The;logic state of thesff~f le~els is~dependent~upon the numerical ~alue contained;in the variant digit l;of~the~Com~d Descrip;tor;C/D. 'Ihe settlng of VAR3 inhibits the:~setting of~:the~tefft:flip-flQp~TESTF) ~f~utf allo-~s f~
the~read~flip-flop (REA~F~ to bfef:s2tff '~he LCP steps over 'o 44 ~
.

STC ll to receive the ~ommand Descriptor longitudinal parity word LPW from the S~stem lO, and then steps over to STC 6 to receive the Descriptor Link D~L from the System. At STC 6, because the "Read" flip-flop (READ~) is set,- the LCP
disconnects from the System lO and steps over to STC 1 to receive an înquiry character (ENQ) from the peripheral .
termi~al unit 50. At STC l,(unless an inquiry character ~ENQ) is received immediately) the LCP steps o~er to STC 3 to await a transmission from the peripheral terminal unit 50.
When the terminal unit transmits, the terminal bus~ flip-~lop ~: ~T~M~SYF) is set) causing the LCP to step over to STC l to ~¦
receiYe the inquiry character (ENQ~. When the ENQ is ",r recei~ed, the set state of the variant register level, V~R3F, inhibi-ts the LCP from stepping o~er to STC 4 and also inhibiting the transfer of the character-to the System lO.
O. ~
Instead the LCP steps oYer to STC 7 to return a Res~llt Descriptor R/D to signify to the System lO that the "test enable" operation is complete. :
Conditional Cancel Operation: The "conditional cancel operatioIl" provides the System lO with a capabilit~ to cancel a preYiously sent Command Descriptor C/D containing a "Read"
op.eration. Referring to FIG. 7E, if the LCP has i~itiated a Read" or a "Write flip Read" operation, but the cxpected data transfer fro~ the peripheral terminal unit 50 is not . ~
25: in progress, the LCP will remain at STC 3 awaiting a possibl.e : I'conditional cancel" instruction. If a co~ditional cancel instruction is now~recei~ed 9 the "Read" operation is ~: :
. : cancellecl and the cancel flip-flop (C~CF) is set. This : canc:ellat.ion will not be effectuated unless the LCP is at . : . : . .
.i, ~ , :

STC 3. The LCP thel1 s-teps o~er to STC ll t,o rece~ve a Command De~c~i.ptor longitudinal parity word LPW Prom the System lO. The set state of the cancel fllp-flop C~C~
i~hihit~ the LCP from steppin.g to STC 6. :.~u~stead, the LCP
- 5 steps over to STC 7 to retu~n a Resu.lt Descriptor R/D to the System lO, indicating that the conditional cancel operation is completed.
Echo Operatlon: The "echo operation~ is a maintenance aid ~o trouble shooting o~ the LCP. This operation begins with a ~Writel' operation in which data is tr~nsferred from System Merncr~ lm o~er to the LGP buffer 2500. This is followed by a 'iRe~d~' o~eratioI1 in ~hich the same data is transferred back to System Memory lO . Assu~ing~ for example, that less tnan a full bu~fer load of data will be transferred and that the operation wlll be terminated ~y receipt of an ending cocle in the last chara.cter position of a word; and sinse the t'echo operation" lS essentially a Write operation fol10wed by a Read opera-t1c>n, the following discussion will invol~e onl~ those LCP actions which are unique to the ec11o operation. ~Read and the ~rlte operatiQrls were pre~iously discussed in co~lection with FIGS~ 7B and 7C). Now referring to FIG 7E, at STC 67 and with the echo flip-flop ~EC~IOF). set, ~; ~ the LCP steps o~er to STC 8 to accept data from the System lO~
.: Beginning at STC 8, the LCP operates as pre~iously discussed : 25 : during a regu.l.ar "W~ite" operation up to the point that the LGP recei~s an ending oode and then steps over to STC 12.
At~STC 12~ although no data is to be transferred ~rom the LCP
~: : to the peripheral t~rminal unlt 50, -the LCP disconnects from ~: the System lO by stepping momentarily o~er to STC l. When .

~. ' :
, ~ - 146 ~
,1 disconnected at STC 1, the LCP initiat~s a request for reconnection to the S~stem l0 by enabling the setting of:
the ~CP request flip-flop tLCPRQF); the I/O send ~lip-flop (IOSF); and by the presetting of ~he buffer address to MADR
253, (Descriptor 1ink, FIG.6C). The LCP then steps over to STC 5 to send the Descriptor Link D/L to the System l0. At STC 5, the ~CP transfers the Descriptor Link D/L to the System l0. The set state of the echo flip-flop (ECHOF) then causes the LCP to step over to STC 4 to return data in the ¦ ~ l 10 buffer 25oo back to the System Memory l0m. Beginning at STC
! 4, data is transferred from the LCP over to the System l0.
The actions performed by the LCP are as thosP previously des-i cribed during a regular "Read" operation up to the point that the I,CP identifies an ending code on the terminal bus 47 and then steps over to STC 12. At STC 12, the Read operation is completed and the set stat of ~he echo flip-flop~ECHOF) ~causes the LCP to step over to STC 7 to return a Result Des-criptor R/D over to the System l0. Return of Result Descr;~-tor RjD: PIG. 7D is a slmplified logic flow diagram regard-ing the return of tbe Result Descriptor R/D. ThP LCP s~eps over to STC 7 to return a Result Descriptor R/D to the System l0 under any of the following conditions listed as a, b, c, d:
::, . : . : . : .
a~ At STC 12 or STC 9 when a "Read" or an echo operation is completed.
bo At STC 5 when a "Write" operation is completed.
c. At STC ll when any one of the following conditions ~, occur:
cl) A descriptor error occurred;

~ 30 : ~
::' ~

`

~c2) A test operation is specified by the Co~nand Descriptor C/D beillg executed;
(c3) The conditional cancel-~fLip flop (C~NCF) is set.
d. At STC 6 if a vertical or a lon~itudinal parity error has occurred.
At STC 7, if t~e transmit flip-flop (X~IITF3 is not set, it is set at t}liS time to activate the LCP Read m~dule. The terminal bus m~ltiplexor select A le~el (SL~I) and the terminal bus m~ltiplexor select B level (SL~) ~re both t ac~ive, which allo~s the terminal bus multiplexor network -(24X2 of ~IG. 6~) to select a word made up of Result Descriptor levels for transmission to the System 10. ~e~
the Result Descr~ptor word i5 placed in the data latches~49, it is also applied to the LPW register 24W to generate an LPW
for the Result Descriptor transfer. The LCP then steps over , to STC 15 to send the R/D LPW to the System lOa STC 15, the te~ninal bus multiplexor select ~ level (SLAR~I) is illactive and the terrninal bus mul-tiplexor select B le~el (SLBR~i) is acti~e 9 which allows the terminal bus multiplexor net~ork (24 2 of ~IG. 6D) to select outputs of the LP~ register 24W for transmission to the System lO~
(The SI~R~I is u.sed in conjunction with the SL.~I to select ~ne of four inputs -to the terminal bus multiplexor networ~).
These are generated on the S~stem Logic Card from outputs of ~5 ~the STC decoder 5~ of ~IGo 6D. -The LCP transfers the LPW, ~; resets selected logic levels to a beginning state, and then :
~teps over to STC 3. The LCP remains at STC 3 until another ~ Command Descriptor C/D is recei~ed~
t ~ , . . .

~; , ' '' .

In summar~ the LCP operates in two "modes't -~ the "off-line" mode and the "on-line" mode.
Off-line mode: ~
Operation of the LCP/~rrninal Unit combination in an off line mode is for the purpose of performing maintenance funGtions. In the field, a ~ariety of operations can be ~ performed to veri~y the condition of t~le LCP or for simple :~ trouble shooting. These operations can be car-ried out without effecting the normal operation of other LCP's in the :~ lO same Base ~odule~
. . . .
:~ On-line mode:
-~ .
The two basic operations controlled by the LCP in the on~line mode operations are (l) a Write operation . . in which data is received from the System by the LCP and ::15 which data is transferred to the peripheral ter.minal unit;
~ and (2) a Read operation in wh1ch data is received from the -~ : terminal uni.t by ~CP and is transferred to the System ~lemory .
m- : ~
In addition to these basic operations~ the lCP can ~ change from a "Write" t~o a "Readt' operation wlth a single ;~ ins-truction, and can also perform selected test operations.
; The followlng items represent the specific operations ~hictn tile LCP can perform by means of program instructions from :~
$he Main~S~stem lO. This is~done by r~leans of Cornmand 25~ ;~ Descriptors:(C/D) and~herein follows a brief summary of ,: , ::what is accomplished by each operation.
Table~II here below summarizes-the specific operations ~: :
~ which the;1CP can~perform: ~

~: . ~ : :: : ~

~ ~ :

T~BLE XII
a. Wrlte d. T~e;t b. Read e. Test ~able c. Write Flip Read f. Conditional Cancel g. ~C~10 Command Descriptors~
~h0 Command Descriptors ~C~D) are in~tructions from ths Main System lO to the ~CP regarding cer-tain operati.ons to be performed~ The followin~ items will su~arize briefly the .10 Co~nand D~scriptors asscciated with each of the'instructions (o~ Table XII) from the ~ain System 10:
(a) Write:
The ~'~rite" Co~unancl Descriptor i5 an instr~ction to transfer data from Sys~em Memorv 10m to the peripheral te~ninal unit desired, for example, such as peripheral terlnina.l . unit 50. ~he LCP accepts data from the Syste~ lO unt.il the LCP buffer 250 ~ for e~ample, is ~11, or unt.i~ th0 data ~ran~fer is stopped by the receipt of an "ending code1' or a ~terminate" sig~al from the Main S~fstem 1~. When the LCP
buffer 25 0 is ~ull, or when an "erlding cvde" is recei~ecl, the LCP t.ransfer3 the contents of ~he buffer 25 0 to the .
peripheral~te7~inal U~lit 50. Tha "l~ritel' Cc?l~an~ Descrip~tor is i~entif~ed as sho~n i~ Table XIII belo~
I ~; : : TABL~ XIJ - (Wr.ite C/D) . , -Dats Lines ~it Val~e A8 ~ ~
: A~ 0 ~ OP Diglt 3 ~8 0 ~7~ J
B2 ~ 0 ~ Variant Digit 1 ~1 (~ ) (b) Read:
The ~'Read`' Co~land Descrip~or i~ an in~truction tct transfer dat~ from the peripher~l ter~inal unit lnvol~ed, : such as unit 50, over to th`e System MemGrY 10m. 'rhe LCP
~ir~t accepts dat~ from the ~eripheral terminal unit 50 ulltil the LCP bl~f~er 25 is.fu11, or until the data transfer is stopped by the receipt ~f an 'le~lding code" from the peripheral terminal unit. When the LCP buffer 25 is full, ~or when t~e ending code is received~, the LCP
transfers ~he cont2nts of the buffer 250~ over tc~ the : System Memory lOm, unless the Main S~stem 10 sends a :~ : "terminate" s~nal tv stop the Read operation ~eoau~e System Memo~ space i~ not aYailable to store any mc~re clQta. I~, :
after initiating a Read operation~ the LCP receivea no dQta for ~ period:~f one second, the LCP ~'times out" and sends a~Result Descrlptor (R/D) to~the Ma~n System lO.~ The one~
se¢ond timine interval oan~be~inhibit~d by ~tt~ng a~bit (Bl)~of~the variant dlg~t 1 of the Command Desorlpt~or ~qual to l. TabLe XIV below::shows~the "Read"~C/~
20~ TABLE~ IV :- (Read~/D) Data Lines ~L__ V~luc A4 ~ 3 3P Dlgit Z~5~ A~ 0~ ~ 3 B2 ~ ;;see~ ~arian~ Dlglt 3;:~ n~te Bl~is;~equQ:l to l,~-the~one-second time out ~eriod~
allo~ed~ o the t~i~ina~;;un~- to; respond, is inhibite,~

~ ri~a ~ e~
; The ~Write flip P~e~d" Co~and ~e~criptor is an instr~cGiorLto the LC~ to accomplish a Write operation, at t~e conclusion of whic.h an i~i~ediate Read operation is perfoI~ed withou-t any inte~ention from the ~fa:Ln System lO. Data is accepted from the Main System lO and transferred to the peripheral terminal unlt until an "endin~ code" is received, Upon receipt of the snding code from the ~ain System 10 ~ the LCP
transfers the ending code to the peripheral te~mlnal unit and then chQnges to the Reacl Mode. The DCP then accepts da-ta from the peripheral terminal unit ancl transfers it to the System ~lemory l~m until an encling code is recei~ecl from t,h~
peripher~l terminal units, or until a terminate si~nal is recei~ed from the Main System lO. If 9 after beginning of the Read portion of the operation, thc LCP recel~es no data for a period of on~-second, then the LCP "times out'7 ancl sen~s a ~e~sult De~criptor (R/-D) to the ~lain System lO, Of course9 the orle-second time i.nterval can be i~libited lf desired, by settinvr the bit Bl of the variant di~it l o~
the Co~manfl Descriptor equal to oneO Table ~V below illustrates the l'Write flip Read"-Co~nand Descriptor.
TABLE ~ : (Write flip Read C/D) Data in~s al~e : : A8 O ) ~ ~5 A4 1 ~ OP Digit .,~, A.l o ~2 ~ O ~ariant Digit .Bl Sef,`
no-te If Bl is equa:L to ls t~e one~econd time-out period, ,` allowed ~o the ter~linal unit to respoIId~ i9 inhi~itedO

. .

~52 -(d) Test: !
The "test" Co~and Descriptor is an instruction to ths LCP to indicate its "operational status" b~ returning a Result Descriptor ~R/D) to the Maîn System 10. If the LCP
is present and aYailable, the Result :Descriptor wili be equal to all "O's'i. ~able XVI belo~ shows the Test Command Descriptor:
~ : ~Test C/D) pata ~ine~ Dl~it_Value A4 ~ OP Digit Al o . . B8 ? - ~-B2 ~ Variant Digit 1 ~1 0 e) Te~t Enable:
The "test enable" Command Descriptor is an instruction to th~ LCP to monitor incoming data from the peripheral terminal unit, and upon receipt o~ an Inquiry Character (ENQ), to fo~m and transmit a Result Descriptor (R/D) to the System 10. This instruction is used to allow the peripheral ter~inal unit to initiate a communica~ion with the Main h ~5 ` System 10~ Table XVII below illustrates this Command Descriptor.
., ~ .. .... ~, . .. . _ .. .. ,, . .. . _ ___ . __ __ _. . _ ___ ___ ._. . . _ _ . _ . ..... . _ .. . .

.
.. . . . : - . ., - . . . : -, :
:, .
' . : ' ' , : - :: , ; : :
., : : .

T~ XVII ~ ~Tes-t E~able C/D) D~ta I.,~Ml~g O
A4 0 ~ ~P Digit Al 0 O
B4 l ~ ' B2 0 ~ Variant Digit Bl see J
note If ~l is equal to l, -the one-secoI1d time-out per.iod5 allowed tci the terminal unit to respond3 is inhibited.
~f) Conditional Cancel:
~ Tbe "Conditional Cancel't Command Descriptor is an ~ instruction to t~e LCP to in~ tiat~ cancellation o~ another ; Command Descriptor under certain condi-tion~. When the Conditional Cancel Co~nand Descriptor is received by the LCP, and, i~ data i3 not bein~ received from the peripheral ~20~ terminal unit during the apylicab1e~portion of a Read ; ope~ation, then the previous Command Descrip~or will be cancellecl~ This C/D is shown ~n Table XVIII:
T~B1E XVIII : (Condîtional Ca~oel C/D) ., : ~
Data Lines ,lt Value A2 l ~ OP Digit f`' A~ 0 30~ ~ B? ~ ~ ~ ~ariant Digit l ,;fis~ t~

(~) Echo The "Echo" Con~and Descriptor is an ins-truction to the I,CP to acc~pt a ~-ull buf'far of data (or less~ ~rom the Main Syste~1 lO and then to return t~e sa~1~ data back to the Malr Syste~l lO to be storecl. This pr~ide~3 a maintenance check and ~rouble shooting diagnosis cycle for the System-DCP
operations. Table XIX ill~strates -th;is Echo Com~rland Descriptor.
T4BI,E X_ : (Echo C/~
, ~ata Lines ~ 1uc A4 ~ OP Digit Al l B8 0 ~ .
~ O ~ Variallt Digit l Bl O
Having de~cri~ed a digital data processing system invo}Ying a plurality of I/O Subsystems for managing data transfer operations and including certain modular unibs ~
such as the ~ine Control Prooessor, t~e Base kIodule, the : Input-Output Translator ~d the ln~errelatiollships thereo~, the ~ollowing ¢laims are made:
: .

: , . :

:

; ~ ~

~ ~ 155 ~-i,i - .. , ~ . ~ .. .

Claims (13)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:-

1. A peripheral controller-processor for storing, controlling and monitoring the transfer of data between central processing unit of a main system and a selected peripheral terminal unit communicating with said main system, said peripheral controller-processor comprising:
(a1) first transmitting means for transmitting stored digital data to said peripheral terminal unit;
(a2) second transmitting means for transmitting stored digital data to the said main system;
(b1) first receiving means for receiving digital data from said main system for temporary storage within said peripheral controller-processor;
(b2) second receiving means for receiving digital data from said peripheral terminal unit for temporary storage within said peripheral controller-proc-essor;
(c) error-checking means for accuracy checking of each transmission of data transmitted and for each transmission of data received, said error check-ing means including checking signals for longitud-inal word parity, vertical parity, and block-check character parity, said error checking means including:
(c1) result descriptor logic means for developing signals reflecting the status of a given instruc-tion task received from said main system and also for generating signals representing the detection of any error condition;
(d) digital translation means for optionally trans-lating data from a data buffer memory to be acceptable to the main memory or peripheral-controller;
(e) a first, second, and third multiplexor;
(e1) said first multiplexor receiving data from said first receiver means, and/or said second receiver means and/or said third multiplexor;
(e2) said second multiplexor receiving data from said first multiplexor and/or from said longitudinal parity signal of said error-checking means;
(e1a) said first multiplexor including selection means responsive to control signals for selecting whether the data received will be accepted from the main system or from the peripheral unit;
(e2a) said second multiplexor including control means to select its input directly from said first multiplexor or from said longitudinal word parity checking signals;
(e3) said third multiplexor receiving data from a data buffer memory and/or from said longitudinal word parity checking means and/or from said digital data translator;
(f) a data buffer memory for receiving and storing digital data received from said second multiplexor, and for providing temporary data storage;
(f1) said buffer memory including:
(f1a) memory space for storing at least one full block of message data for later transmittal to said main system or to said peripheral unit;
(f1b) memory space for storing a descriptor-link identifier word generated from said main system, to identify each data transfer operation task initiated by said main system;

(f1c) memory space for storing an instruction word received from said main system;
(f1d) memory space for storing a result descriptor word generated by result-descriptor logic circuitry for later transfer to said main system;
(g) processor-logic means for receiving data transfer instruction words from said main system and execu-ting said instructions without further interfer-ence to said main system, said processor-logic means including:
(g1) means for executing read, write and test opera-tions independently of the processor of the main system, said logic means also executing error checking operations on digital data received by said peripheral controller-processor.

2. The peripheral controller-processor of claim 1 wherein said error checking means includes:
a longitudinal parity word circuit for receiving the complement of each word received by said peripheral controller-processor, said longitudinal parity word circuit operating to store a received digital word signal and add to it the complement of that word signal so that if the transfer has been accurate, the output of said longitudinal parity word circuit will be all zeros, and no inhibition of data transfer will occur, no error signal will be generated.

3. The peripheral controller-processor of claim 1 wherein said error-checking means includes:
block check character circuitry for receiving each character of a message block from said peripheral terminal unit and performing a binary addition of all characters in the mesage block to establish a sum which is compared for error with another sum independently generated in said peripheral unit for the same characters in the same message block.

4. In a digital system for the transfer and control of digital information between a plurality of peripheral units and a central main system of a processor and main memory, a plurality of input-output interface control units, designated as Line Control Processors for providing data-transfer control between each of the plurality of peripheral units and the main system, each of said Line Control Proce-ssors comprising:
(a) processor-logic means for execution of instruction words received by said Line Control Processor from said Main system;
(b) result descriptor logic circuitry responsive to error checking means within said Line Control Processor, for generating a result descriptor word signal, to said main system, representing error conditions, completion of data transfer, or incompletion of a specific data transfer task;
(c) means for receiving and error checking the accuracy of information data and instruction-data received from said peripheral unit or from said main system, said means for error checking including:
(i) a block check character register and decoder to signal said result descriptor logic circuitry if data transferred from said peripheral unit is inaccurate or in error;
(ii) a longitudinal parity word register and encoder to check longitudinal parity of words of data trans-mission from said peripheral unit or from said main system and to generate signals to said result descrip-tor logic circuitry representative of accuracy or error;

(iii) a vertical parity word generator and checker to check vertical parity of words transmitted from said peripheral unit and/or said main system in order to signal said result descriptor logic circuitry as to accuracy or error of transmission;
(iv) an OP-code encoder to check validity of OP code signals received from said main system and to convey signals to said result-descriptor logic circuitry to signal the validity or invalidity of the OP-code transmitted.
(d) register and decoder means for developing status condition signals used for controlling the sequence of instruction steps to be carried out by Line Control Processor including means for conveying said signals to said main system, said signals representing the steps completed in execution of an OP-code instruction;
(e) flow-logic means connected to said processor-logic means to sense the operational steps executed by said processor-logic means in correspondence therewith, to convey sensing signals to said register and decoder means;
(f) input-multiplexor means to provide input data to a data buffer memory from said main system or from said peripheral unit;
(f1) first control means directed by said processor-logic, said control means switching said input-multiplexor to receive data from either said main system or said peripheral unit;
(g) second control means directed by said processor-logic for switching said output-multiplexor to send data either to said main system or to said peripheral unit;

(h) a data buffer memory for storing at least two block lengths of message data and having means for transmitting one block of message data to said main system while simultaneously receiving a block of message data from a peripheral unit/ or transmitting a block of data to a peripheral unit while simultaneously receiving a block of data from said main system, and wherein said data buffer memory includes additional storage space for storing:
(i) an instruction word received from said main system to determine the execution sequence of said processor-logic;
(ii) a descriptor link word received from said main system to identify the instruction-task and the specific Line Control Processor involved in that task;
(iii) a result-descriptor word received from said result-descriptor logic circuitry to specify the condition or each instruction-task as to its completion, incompletion or error condition.

5. In a digital system for the transfer and control of digital information between a main host system, which includes a central processor with main memory having an input/output translator interface unit, and a plurality of remote peripheral terminal units wherein each peripheral terminal unit is connected to said main host system indivi-dually via a corresponding Line Control Processor, a Line Control Processor comprising:
(a) a data buffer memory for holding at least two block-lengths of message data and including dedicated sections of memory for control-data, said control data sections including memory space for holding:
(a1) an input/outputcommand word generated from said main system;

(a2) a descriptor-link word generated from said main system for identifying the particular input/output command to which the buffer data applies;
(a3) a result-descriptor word for subsequent signal-ing to the main system the completion status from each input-/output command, as to whether it is complete, incomplete or in error;
(b) processor-logic means for executing the instruc-tion/command words received from said main host system for controlling the transmission of data between said Line Control Processor and said peripheral terminal unit and said main host system;
(c) status count signal generation means, for devel-oping status condition signals in said Line Control Process-or, to control the sequence of steps required to carry out input/output operations according to a predetermined line discipline;
(d) flow control logic means, connected to said processor-logic means, for controlling said status count signal generation means;
(e) result-descriptor logic means for generating signals indicative of accurate completion, incompletion or error in data transfer operations;
(f) error-detection means for monitoring each data transfer operation and including;
(f1) vertical parity checking means;
(f2) longitudinal parity word checking means, (f3) block check character means to check accuracy of transfer of each complete block of data transferred, said error detection means providing signals to said result-descriptor logic means.

6. The Line Control Processor of claim 5 wherein said status count signal generation means includes:
(c1) status count signals to signal the main host system that a particular peripheral device is available to the system;
(c2) status count signals to request a descriptor link from the main host system before the said Line Control Processor will begin an operation;
(c3) status count Signals to signal the main host sys-tem that the Line Control Processor had disconnected and no longer needs access to the main host system;
(c4) status count signals to signal the main host system that said Line Control Processor is requesting connection to the main host system and including means for the Line Control Processor to transmit the descriptor-link to the main host system;
(c5) status count signals to signal a Write operation when the buffer memory is empty;
(c6) status count signals to signal said host system that the memory buffer can only accept one more word before filling its buffer space;
(c7) status count signals to signal to the main host system that the Line Control Processor has a full buffer of data to transmit and including means for transmitting data from said buffer memory to said main host system until the buffer memory is empty of stored data.

7. In a system involving a plurality of remote peripheral terminal units, each peripheral terminal of which is connected with its own specific peripheral-controller, wherein a plurality of said periphal-controllers are organ-ized into groups designated as base modules, such that each base module has its own message level interface bus connecting it, via a main system interface unit designated as an input-output translator, to a central main system having a main processor and main memory, and wherein said input-output translator provides means to connect and disconnect selected peripheral-controllers with main memory without interrupting the main processor and further provides means to formulate an I/O data-transfer task command and to formulate a descriptor-link word to identify each particular data transfer task for each particular peripheral-controller, a peripheral-controller for operation in said system, said peripheral-controller comprising:
(a) means for receiving information data and instruc-tion-data from a peripheral unit or from said main system;
(b) buffer memory means for temporarily storing said information-data and said instruction-data, said buffer memory means including:
(b1) memory space for storing at least one complete block of message data;
(b2) memory space for storing an instruction word received from said main system;
(b3) memory space for storing said descriptor-link identifier word generated from said main system, to identify each data transfer operation task initiated by said main system pertaining to said peripheral-controller;
(c) processor-logic means for execution of instruction data received from said main system;
(d) register and decoder means for developing status condition signals for controlling the sequence of instruc-tion steps to be carried out by said peripheral-controller according to a predetermined sequence, and for conveying signals to said main system representing the steps completed in the execution of said instruction-data;
(e) flow-logic means for providing signal information to said register and decoder means, said flow-logic means sensing each operational step in the execution of an instruction, and conveying the sensed signals to said register and decoder means.

8. The peripheral-controller of claim 7 which further comprises:
means to interchange data with a peripheral unit at the speed rate capability of said peripheral unit while said peripheral-controller is disconnected from said main system, and connected to said peripheral unit;
means to independently interchange data with said main system at the speed rate capability of said main memory while said peripheral-controller is disconnected from said peripheral unit and connected to said main system.

9. The peripheral-controller of claim 7 which further comprises:
means to receive and store an instruction-word from said main system and convey said instruction-word to said processor-logic means for execution without further atten-tion from said main system;
means to generate result-descriptor signals for trans-mittal to said main system when said instruction word has been fully executed, said means including:
result-descriptor logic responsive to an end-of-block message character transmitted when each data transfer block is completed.

10. The peripheral-controller of claim 7 wherein said descriptor-link identifier word stored in said buffer memory means includes informational data as to:
(i) the location in the input-output translator which stores the memory addresses to be used by the peripheral-controller;
(ii) whether or not code translation is required in the input-output translator;
(iii) the direction flow of data transfer which is to be accomplished;
(iv) whether a data transfer to memory is to be inhibited.

11. The peripheral-controller of claim 10 wherein said informational data as to location which stores memory address-es to be used further includes:
(v) unique address data which identifies a particular peripheral-controller;
(vi) unique address data which identified the base module in which a particular peripheral-controller resides.

12. The peripheral-controller of claim 8 which further includes:
means responsive to signals from said main system or to signals from said peripheral unit or to signals from said peripheral-controller to abort execution of an instruction word or a data transfer and to signal this aborted transfer to the said main system.

13. The peripheral-controller of claim 9 wherein said buffer memory means further includes:
memory space for storing a result-descriptor word generated by said result-descriptor logic circuitry for later transfer to said main system.