Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
  • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
  • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
  • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
  • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
  • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
  • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
  • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
  • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
  • G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Definitions

• a contactless smart card includes (Figure 1):
• the address in memory 16 is given by the content of one or more registers mentioned above and the same is true of the data to be written in memory
• the logic block 14 may be required to perform an operation of reading a data item in the memory 16 and to carry out a processing on this data item.
• the data read in the memory after processing or not by the logic block 14, is transmitted to the radio frequency interface 12 which supplies modulation signals applied to the antenna 10 with a view to their transmission to the remote reader.
• the binary signals which are emitted by the remote reader, and which must therefore be analyzed by the logic block 14, are in the form of frames of binary digits "1" or "0" having formats defined by standards.
• figure 2-a is an example of frame format according to standard IS014443-3 while figure 2b is an example of frame format according to standard IS015693-3.
• the frame according to standard IS014443-3 begins (references 20 and SOF) with a start of frame of ten to eleven binary digits "0" followed by two "1" and ends (references 22 and EOF) with an end of frame of ten to eleven "0” followed by a "1".
• the start SOF is followed for example by a byte 24 indicating the read command, then by n bytes (reference 26) corresponding to the address in memory 16, and by two error control bytes (reference 28) more known by the acronym CRC for the English expression "Cyclic Redundancy Check”.
• the frame according to ISO 15693-3 begins with a start of SOF frame, 30 and ends with an end of EOF frame, 32.
• the start of SOF frame is followed for example by a request byte 34, then byte 36 of Command, n bytes 40 of data and two bytes 38 of CRC.
• the logic block 14 To detect a frame, the logic block 14 must analyze the sequence of binary signals supplied by
• An object of the present invention is therefore to provide a circuit for detecting data frames and the formatting of the latter, the processing time of which is substantially reduced.
• FIG. 1 is a simplified block diagram of a contactless smart card
• FIGS. 4a, 4b, 4c and 4d are signal diagrams showing the synchronization of the data
• FIG. 5 is a diagram of the circuit for detecting and shaping the data frames according to the invention
• FIG. 6 is a diagram of the states of the state machine for sequencing the operations of detecting and shaping the byte frames
• FIG. 8 is a diagram of a logic circuit for obtaining the complement of the SDA signal.
• the circuit according to the invention is based on the knowledge of the number of bytes in the frame being analyzed, knowledge which is given at the start of the frame by the operation to be carried out, that is to say by the first bytes of the frame, for example by one, two or three bytes.
• circuits 62 to 76 which supply control signals for the state machine 60
• the ZERO signal and the STARTBIT signal pass to logic level "1" after a delay of 1.2 microseconds corresponding to the period of a second clock signal CK at the frequency 847 KHz, a frequency which is approximately eight times higher than that of the first CLK106 clock signal.
• an LDBYTE signal for loading the DATA value
• a DECBYTE signal for counting down. It provides on a first output terminal a BYTE signal which is applied to an input terminal of the state machine 60 and on a second output terminal a CRCVALID signal which indicates that the bytes being received are CRC bytes .
• the STARTBIT signal goes to value 1 while the ZERO signal goes to logic value "1" and remains in this state.
• the state machine changes to STATE-2 (circle 102) at the next CLK106 clock pulse.
• the INCPTR, RSTSTOP and RSTBIT signals pass to logic level "1".
• the value of the first eight bits is sufficient.
• the state machine goes to STATE-6 (circle 106) so that the signal LOABYTE ⁇ 1 loads the value of DATA (number of bytes of the frame) in the down-counter 72. If PTR is different from the value "1", the DATA code is not loaded into the down-counter 72.
• the state machine goes to STATE-7 on the next pulse from CLK106.
• the down-counter 72 is decremented by one by the signal DECBYTE ⁇ 1 and bit counter 68 is reset to zero by signal
• the invention proposes to invert the CRC bytes when they are detected on reception, which is made possible by the fact that the invention makes it possible to identify bytes on the fly in advance, including CRC bytes.
• the comparator comprises (FIG. 9) three D type flip-flops 130, 132 and 134, an EXCLUSIVE OR circuit 136 and an AND circuit 138.
• the input terminal D of the flip-flop 130 receives the digits of the identifier ID as they are received while the input terminal D of the flip-flop 132 receives the digits of the serial number SN read in series in memory 16.
• the clock input terminals CK of the two flip-flops receive a clock signal CLK which corresponds to that used for reading from memory 16.
• the reset input terminal R receives the signal POR because it is reversed.
• the output terminal Q of each flip-flop 130 or 132 is connected to an input terminal of the EXCLUSIVE OR circuit 136 whose output terminal is connected to an inverted input terminal of the AND circuit 138.
• the other input terminal of the AND circuit 138 is connected to the output terminal Q of the flip-flop 134 whose input terminal D is connected to the output terminal of the AND circuit 138.
• the flip-flop 134 is set to state 1 by the signal POR applied to the inverted input terminal P.
• the clock input terminal CK of flip-flop 134 is such that the change of state takes place on the falling edge of the clock signal CLK and not on the rising edge as for flip-flops 130 and 132.
• the operation of the serial comparator of FIG. 9 is such that the output terminal Q of the flip-flop 134 provides a status signal "0" when the compared figures are the same and a status signal "1" when the compared figures are different.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Communication Control (AREA)
• Synchronisation In Digital Transmission Systems (AREA)

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• 2000
  • 2000-10-23 EP EP00971483A patent/EP1330781A1/de not_active Withdrawn
  • 2000-10-23 US US10/399,817 patent/US7003407B1/en not_active Expired - Lifetime
  • 2000-10-23 WO PCT/FR2000/002946 patent/WO2002035466A1/fr active Application Filing
  • 2000-10-23 JP JP2002538376A patent/JP2004512754A/ja active Pending

Non-Patent Citations (1)

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