EP0457819A1 - Masquage des defaillances dans des memoires a semi-conducteurs - Google Patents

Masquage des defaillances dans des memoires a semi-conducteurs

Info

Publication number
EP0457819A1
EP0457819A1 EP19900903208 EP90903208A EP0457819A1 EP 0457819 A1 EP0457819 A1 EP 0457819A1 EP 19900903208 EP19900903208 EP 19900903208 EP 90903208 A EP90903208 A EP 90903208A EP 0457819 A1 EP0457819 A1 EP 0457819A1
Authority
EP
European Patent Office
Prior art keywords
address
bits
tile
addresses
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19900903208
Other languages
German (de)
English (en)
Inventor
Stephen Charles Anamartic Limited Olday
Gordon Blair Anamartic Limited Neish
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anamartic Ltd
Original Assignee
Anamartic Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anamartic Ltd filed Critical Anamartic Ltd
Publication of EP0457819A1 publication Critical patent/EP0457819A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/86—Masking faults in memories by using spares or by reconfiguring in serial access memories, e.g. shift registers, CCDs, bubble memories

Definitions

  • Another object is to allow the memory to be addressed in blocks of varying block sizes, namely a basic, minimum block size and larger block sizes which are multiples by a power of two of the basic size but which all present a block-like aspect ratio.
  • the higher order bits are alternated. These alternated bits cause the memory to be accessed in a series of rectangular blocks referred to as "tiles".
  • the un-permuted lower order bits access the locations within a tile row by row as in conventionally accessed memory chips.
  • the alternation of the higher order bits leads to a different pattern of accessing the tiles.
  • Figure 4a shows some of the conventions of Figure 4 in more detail
  • Figure 6 is a block diagram of a wafer scale integrated circuit which uses the invention.
  • the command set of GB-A 2 177 825 is extended to include commands ACLOAD, ACONE, ACZERO and STSP.
  • ACLOAD (address counter load) sets the counter 12 into its shift register mode. Thereafter a succession of ACONE (address conter one) and ACZERO (address counter zero) commands shift 1 and 0 bits respectively into the counter 12 until it has been filled with the required start address.
  • ACLOAD can then be cleared with another command CLR-FUN (clear function), and either the READ or WRITE command asserted to allow data to be read from the RAM via RECV or written to the RAM via ZMIT, essentially as in GB-A 2 177 825.
  • the counter 12 can be started and stopped by STSP, which is a toggle cammand, to control the read or write operation.
  • the counter 12 is separate from a refresh counter which runs continuously.
  • Transferring the memory tile map from the WDT EPROM 24 to the RAM 26 means that, if a tile on the wafer develops a hard fault, it can be taken out of the memory tile map currently in use, i.e. the computer 38 can effectively update the map taken from the EPROM 24. Also, access to the RAM 26 will be more rapid than to the EPROM 24.

Landscapes

  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Une mémoire à accès sélectif, adressable par ligne et colonne, est adressée par une source d'adresses binaires définissant un espace d'adresses linéaire via les décodeurs de lignes et de colonnes sensibles à des groupes respectifs de bits de la source d'adresse pour adresser respectivement des lignes et colonnes individuelles de la mémoire. Les bits sont permutés entre la source d'adresse et les décodeurs de sorte qu'au moins les bits de poids fort de la source d'adresse soient appliqués en alternance à des décodeurs de ligne et de colonne. L'accès à la mémoire se fait ainsi dans des blocs rectangulaires appelés carreaux, qui, en raison de l'imbrication des bits, sont disposés en une configuration à carreaux se décalant en alternance dans le sens des lignes et dans le sens des colonnes.
EP19900903208 1989-02-13 1990-02-13 Masquage des defaillances dans des memoires a semi-conducteurs Withdrawn EP0457819A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8903180 1989-02-13
GB898903180A GB8903180D0 (en) 1989-02-13 1989-02-13 Fault masking in semiconductor memories

Publications (1)

Publication Number Publication Date
EP0457819A1 true EP0457819A1 (fr) 1991-11-27

Family

ID=10651586

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19900903208 Withdrawn EP0457819A1 (fr) 1989-02-13 1990-02-13 Masquage des defaillances dans des memoires a semi-conducteurs

Country Status (3)

Country Link
EP (1) EP0457819A1 (fr)
GB (1) GB8903180D0 (fr)
WO (1) WO1990009634A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9305801D0 (en) * 1993-03-19 1993-05-05 Deans Alexander R Semiconductor memory system
JPH1116365A (ja) * 1997-06-20 1999-01-22 Oki Micro Design Miyazaki:Kk アドレスデコーダおよび半導体記憶装置、並びに半導体装置
US6137318A (en) * 1997-12-09 2000-10-24 Oki Electric Industry Co., Ltd. Logic circuit having dummy MOS transistor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755810A (en) * 1985-04-05 1988-07-05 Tektronix, Inc. Frame buffer memory
GB2184268B (en) * 1985-12-13 1989-11-22 Anamartic Ltd Fault tolerant memory system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9009634A1 *

Also Published As

Publication number Publication date
WO1990009634A1 (fr) 1990-08-23
GB8903180D0 (en) 1989-03-30

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Legal Events

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