EP0408653A1 - Porte dielectrique pour transistor a effet de champ a film mince - Google Patents

Porte dielectrique pour transistor a effet de champ a film mince

Info

Publication number
EP0408653A1
EP0408653A1 EP89904998A EP89904998A EP0408653A1 EP 0408653 A1 EP0408653 A1 EP 0408653A1 EP 89904998 A EP89904998 A EP 89904998A EP 89904998 A EP89904998 A EP 89904998A EP 0408653 A1 EP0408653 A1 EP 0408653A1
Authority
EP
European Patent Office
Prior art keywords
layer
dielectric
thin film
gate dielectric
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP89904998A
Other languages
German (de)
English (en)
Other versions
EP0408653A4 (en
Inventor
Anthony W. Catalano
Ralph C. Kerns
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Solarex Corp
Original Assignee
Solarex Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Solarex Corp filed Critical Solarex Corp
Publication of EP0408653A1 publication Critical patent/EP0408653A1/fr
Publication of EP0408653A4 publication Critical patent/EP0408653A4/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT

Definitions

  • the present invention relates to a thin film transis ⁇ tor device, and more particularly, to an improved gate dielec ⁇ tric for a thin film transistor.
  • Thin film transistors generally comprise source and drain electrodes interconnected by a central layer of semiconductor material having a thickness less than l ⁇ .
  • the device operates by creating a conducting channel beneath a source electrode and a drain electrode.
  • the current flow between the electrodes is controlled by the application of a voltage to a gate which is adjacent to, but insulated from, a portion of the semiconductor material.
  • a positive bias is applied to the gate electrode, negative charges accumulate in the otherwise low conductivity layer of semiconductor material.
  • the conductivity of the semiconductor material layer is increased, and a source-drain current can be made to flow under the appropriate bias.
  • the gate dielectric mate ⁇ rial is patterned to form a central portion over a planar por ⁇ tion of the gate region and to cover any exposed gate edges.
  • atomic level defects in the dielectric material or at the dielectric/ semiconductor interface can occur causing charges to become trapped in the dielectric layer. Any charge trapped in the dielectric layer or at the dielectric/semiconductor inter ⁇ face can degrade performance of the thin film transistor and give rise to hysteresis in the performance and other time depen ⁇ dent phenomenon that limit the usefulness of the device in
  • charge leakage lowers the on/off source-drain current ratio of the device.
  • pinholes can occur which can .cause short circuits to occur if a pinhole is under the source or drain.
  • a gate dielectric mate ⁇ rial for a thin film transistor which effectively prohibits charges from becoming trapped in the dielectric layer or at the dielectric/semiconductor interface and which is free of pin ⁇ holes. It would further be desirable to have a dielectric mate ⁇ rial with a high dielectric constant for good electrical isola ⁇ tion characteristics thereby permitting high electric fields to be applied to the semiconductor thus improving performance and permitting high voltages to be switched. And it would also be desirable to have a gate dielectric material comprised of a thin film material thereby maintaining the thin aspect of the overall thin film field effect transistor.
  • the invention comprises a dielectric for a gate of a thin film field effect transistor, comprising a first layer of an insu ⁇ lating thin film crystalline or amorphous material formed on the gate and a second layer of silicon nitride formed on the first layer.
  • Fig. 1 is a cross-sectional diagram illustrating a gate dielectric for a thin film field effect transistor in accordance with an embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT
  • the transistor is formed on a substrate 10 of a suit ⁇ able material, such as glass.
  • a gate electrode 12 is deposited on the substrate 10.
  • the gate electrode 12 is formed of a suit ⁇ able metal, such as nichrome or molybdenum.
  • a first layer of gate dielectric material 14 is comprised of insulating thin film material is deposited on the gate electrode 12 and the substrate 10 by a process of atmo ⁇ spheric chemical vapor deposition using a 5 to 6 percent (atom ⁇ ic) solution of SiH in N2 and O2.
  • the first layer of gate dielectric material 14 may be comprised of silicon dioxide (Si ⁇ 2).
  • the first thin film layer is deposited at about 540°C to form a layer of gate dielectric material 14 approximately 800 to 2,500 angstroms thick when measured from the gate electrode 12 to the top of the first layer of gate dielectric material 14.
  • the first layer of gate dielectric material 14 may also be comprised of tantalum pentoxide (Ta2 ⁇ s) or silicon dioxide or a compound of silicon and nitrogen having a chemical formula SiN x , where x is a number in the range of 0.1 to 1.33 and is prefereably equal to 1.33.
  • the device can be further improved by exposing the first layer of gate dielectric material 14 to a plasma etch using a solution of CF4-O2 or NF3 in order to remove any contam ⁇ ination due to atmospheric exposure, oxidation, or moisture.
  • second layer of gate dielectric material 16 is deposited on the first layer of gate dielectric material 14.
  • the second layer of- gate dielectric material 16 is silicon nitride and is approximately 1,000 angstroms thick when measured from the gate electrode 12 to the top of the gate dielectric material 16.
  • the first layer of gate dielectric material 14 of in ⁇ sulating thin film material is chosen to provide a high dielec ⁇ tric constant.
  • silicon dioxide has a dielectric constant equal to 4 and tantalum pentoxide has a dielectric material constant equal to 25.
  • the second layer of dielectric 16 should also have a high dielectric constant, but it is pri ⁇ marily chosen in order to eliminate pinholes which could occur in the first layer 14 and to provide a clean interface to the subsequent semiconductor layer.
  • Silicon nitride for example, appears to cover up any pinholes that may occur in the first layer of dielectric material 14.
  • any charge leakage which could cause charges to become trapped in the first layer 14 thereby lowering the on/off source-drain current ratio is pre ⁇ vented.
  • the device of the present invention achieves an on/off source-drain current ratio equal to about 10' and a breakdown voltage which is greater than 100 volts, as opposed to a break ⁇ down voltage in prior thin film transistors of from 20 to 40 volts.
  • a semiconductor layer 30 is deposited over the second gate dielectric layer 16, the first gate dielectric layer 14, the gate electrode 12, and over the substrate 10 preferably by using a glow discharge plasma of silane method.
  • This method of deposition which is well known to those in the art as glow dis ⁇ charge, is described in U.S. Patent No. 4,064,521, which is hereby incorporated herein by reference.
  • Semiconductor layer 30 is preferably hydrogenated amorphous silicon (a-Si:H) which pro ⁇ vides desirable properties for a thin film field effect transis ⁇ tor such as would be known to one of ordinary skill in the field of thin film transistor fabrication.
  • n+ conductivity type semiconductor material 32 is deposited over the semiconductor layer 30, which can also be comprised of hydrogenated amorphous silicon. N-type conduction occurs when a material has been doped to create excess charge carriers which thereby increase the on-current flow.
  • a source electrode 18 and a drain electrode 20 are deposited over the layer 32.
  • the source electrode 18 and the drain electrode 20 are acid etched and then patterned.
  • Source electrode 18 and drain electrode 20 are spaced apart and layer 32 is subjected to a plasma etch leaving a portion of the semiconductor layer 30 exposed which partially overlays the sec ⁇ ond layer of gate dielectric material 16, the first layer of gate dielectric material 14, and the gate electrode 12.
  • the source electrode 18 and drain electrode 20 are preferably alumi ⁇ num, however, magnesium, molybdenum, nichrome, or other suitable conductive metals, mixtures of these metals, or alloys of these metals may be used.
  • the double-layer gate dielectric of the present inven ⁇ tion prevents pinholes from occurring in the gate dielectric material and prevents charge leakage which could give rise to undesirable time dependent phenomenon and which could lower the on/off source-drain current ratio. Moreover, both layers of dielectric material are chosen to obtain high dielectric con ⁇ stants, thereby achieving a high breakdown voltage.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

Un transistor à effet de champ à film mince utilise une double couche de matériau diélectrique, la première couche (14) étant constituée d'un cristallin ou d'un matériau amorphe isolant et la deuxième (16) d'azoture de silicium. La première couche comporte une constante diélectrique élevée et la seconde élimine les trous qui pourraient se former sur la première couche.
EP19890904998 1988-03-31 1989-03-14 Gate dielectric for a thin film field effect transistor Ceased EP0408653A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17626488A 1988-03-31 1988-03-31
US176264 1988-03-31

Publications (2)

Publication Number Publication Date
EP0408653A1 true EP0408653A1 (fr) 1991-01-23
EP0408653A4 EP0408653A4 (en) 1991-10-16

Family

ID=22643652

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19890904998 Ceased EP0408653A4 (en) 1988-03-31 1989-03-14 Gate dielectric for a thin film field effect transistor

Country Status (2)

Country Link
EP (1) EP0408653A4 (fr)
WO (1) WO1989009494A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013692A (en) * 1988-12-08 1991-05-07 Sharp Kabushiki Kaisha Process for preparing a silicon nitride insulating film for semiconductor memory device
US5580815A (en) * 1993-08-12 1996-12-03 Motorola Inc. Process for forming field isolation and a structure over a semiconductor substrate
US5918147A (en) * 1995-03-29 1999-06-29 Motorola, Inc. Process for forming a semiconductor device with an antireflective layer

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0027184A1 (fr) * 1979-10-15 1981-04-22 Rockwell International Corporation Structure de dispositif SOS et procédé de fabrication
DE3306535A1 (de) * 1982-02-25 1983-09-15 Sharp K.K., Osaka Duennfilmtransistor mit isoliertem gate
WO1984004418A1 (fr) * 1983-05-02 1984-11-08 Ncr Co Dispositif de memoire remanente a semi-conducteur
JPS60109285A (ja) * 1983-11-17 1985-06-14 Seiko Instr & Electronics Ltd 薄膜トランジスタ
DE3539794A1 (de) * 1984-11-13 1986-05-22 Sharp K.K., Osaka Duennfilm-transistor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3922774A (en) * 1972-05-01 1975-12-02 Communications Satellite Corp Tantalum pentoxide anti-reflective coating
JPS59205712A (ja) * 1983-04-30 1984-11-21 Fujitsu Ltd 半導体装置の製造方法
JPS60160173A (ja) * 1984-01-30 1985-08-21 Sharp Corp 薄膜トランジスタ
US4639087A (en) * 1984-08-08 1987-01-27 Energy Conversion Devices, Inc. Displays having pixels with two portions and capacitors
US4698787A (en) * 1984-11-21 1987-10-06 Exel Microelectronics, Inc. Single transistor electrically programmable memory device and method
JPH0686863A (ja) * 1992-09-07 1994-03-29 Ace Denken:Kk パチンコゲーム機

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0027184A1 (fr) * 1979-10-15 1981-04-22 Rockwell International Corporation Structure de dispositif SOS et procédé de fabrication
DE3306535A1 (de) * 1982-02-25 1983-09-15 Sharp K.K., Osaka Duennfilmtransistor mit isoliertem gate
WO1984004418A1 (fr) * 1983-05-02 1984-11-08 Ncr Co Dispositif de memoire remanente a semi-conducteur
JPS60109285A (ja) * 1983-11-17 1985-06-14 Seiko Instr & Electronics Ltd 薄膜トランジスタ
DE3539794A1 (de) * 1984-11-13 1986-05-22 Sharp K.K., Osaka Duennfilm-transistor

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IEEE TRANSACTIONS ON ELECTRON DEVICES. vol. ED-34, no. 5, May 1987, NEW YORK US pages 1079 - 1083; MARK S. RODDER et al: "Hot-Carrier Effects in Hydrogen-Passivated p-Channel Polycrystalline-Si MOSFET`s" *
PATENT ABSTRACTS OF JAPAN vol. 9, no. 263 (E-351)(1986) 19 October 1985, & JP-A-60 109285 (SEIKO DENSHI KOGYO K.K.) 14 June 1985, *
See also references of WO8909494A1 *

Also Published As

Publication number Publication date
EP0408653A4 (en) 1991-10-16
WO1989009494A1 (fr) 1989-10-05

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