EP0364679A1 - Appareil synthétiseur de fréquence - Google Patents

Appareil synthétiseur de fréquence Download PDF

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Publication number
EP0364679A1
EP0364679A1 EP89114052A EP89114052A EP0364679A1 EP 0364679 A1 EP0364679 A1 EP 0364679A1 EP 89114052 A EP89114052 A EP 89114052A EP 89114052 A EP89114052 A EP 89114052A EP 0364679 A1 EP0364679 A1 EP 0364679A1
Authority
EP
European Patent Office
Prior art keywords
frequency
frequencies
phase
synthesis device
offset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP89114052A
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German (de)
English (en)
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EP0364679B1 (fr
Inventor
Bruno Fognini
Helmut Heinz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Schweiz AG
Original Assignee
Siemens Albis AG
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Filing date
Publication date
Application filed by Siemens Albis AG filed Critical Siemens Albis AG
Publication of EP0364679A1 publication Critical patent/EP0364679A1/fr
Application granted granted Critical
Publication of EP0364679B1 publication Critical patent/EP0364679B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/12—Indirect frequency synthesis using a mixer in the phase-locked loop

Definitions

  • the present invention relates to a frequency synthesis device according to the preamble of claim 1.
  • Phase-controlled control loops are often used for frequency synthesis in frequency synthesis devices.
  • Figure 79e on page 82 shows a phase-controlled control loop with a variable frequency divider and a mixer that is suitable for generating high frequencies.
  • a variable or fixed offset frequency and a fixed reference frequency are fed to the phase-controlled control loop.
  • the phase noise of such an arrangement is dependent on the division ratio of the variable frequency divider and assumes a minimum value at the division ratio one.
  • An improvement of this circuit known from the Hewlett-Packard Journal (February 1981) consists in keeping the division ratio of the frequency divider constantly equal to one and in feeding the variable control circuit with two variable frequencies.
  • the supplied offset and reference frequencies must also have no auxiliary waves.
  • the offset and reference frequencies are each fed to a bandpass filter to eliminate the interfering spurious waves.
  • this solution is very expensive.
  • the object of the invention is therefore to improve the known circuit. This object is achieved by the measures specified in the characterizing part of patent claim 1. Advantageous embodiments of the invention are specified in further claims.
  • Advantages of the frequency synthesis device according to the invention are the reduced circuit structure with simultaneously increased spectral purity of the output signals; the bandpass filters mentioned are eliminated, the phase noise is reduced and the frequency spectrum of the output signal is free of disturbing spurious waves.
  • the frequency synthesis device shown there contains a phase-controlled control circuit PLL, consisting of a phase detector PD, an amplifier module, a low-pass filter, a mixer M1 and a voltage-controlled oscillator VCO, to which two signals s os and s RG1 with the frequencies f os and f RG1 are fed .
  • a phase-controlled control circuit PLL consisting of a phase detector PD, an amplifier module, a low-pass filter, a mixer M1 and a voltage-controlled oscillator VCO, to which two signals s os and s RG1 with the frequencies f os and f RG1 are fed .
  • the frequency f RG1 arises in the first reference frequency generator RG1 by division from a reference frequency f Bz and optionally takes one of five values.
  • the value of the frequency f RG1 is selected via a multiplexer MU1.
  • the frequency division takes place in a divider T1 with the division factors X1 ... X5.
  • harmonic vibrations can also occur in the signal s RG1 .
  • the signal s RG1 is supplied to an input of the phase detector PD of the phase-controlled control circuit PLL without prior filtering.
  • the frequency f RG2 (with the division factors Y1 ... Y4) arises in the same way, the value of which is selected via a multiplexer (MU2).
  • the signal SRG2 which also contains harmonic vibrations in addition to the basic frequency f RG2 , is fed to a single-sideband mixer M os in an offset stage OS, at whose second input there is a signal s OR with the offset reference frequency f OR .
  • the offset reference frequency f OR is also superimposed on the harmonic vibrations contained in the signal s RG2 .
  • the signal s os is fed unfiltered to an input of the mixer stage M1 in the phase-controlled control circuit PLL.
  • the frequencies f RG1 and f M1 assume the same value.
  • the phase-controlled control loop is designed as a tracking filter. It thus acts as a shiftable bandpass with steep edges and a small bandwidth B TF , which is given by the loop bandwidth of the phase-controlled control loop PLL. Frequencies f res that are outside the bandwidth B TF of the tracking filter are consequently blocked.
  • the structure and operation of such a tracking filter are explained in more detail in the book mentioned at the beginning, page 55.
  • the second measure to eliminate the interference frequencies is to choose the reference frequencies f RG1 and f RG2 in such a way that all resulting frequencies f res without f sA (ie in formula (2) f res with m, n ⁇ + 1) according to the condition lie outside the bandwidth B TF of the tracking filter. If higher attenuation values are required for the interference frequencies, the resulting value for 1/2 B TF can be multiplied by an additional factor (>1); ie disturbing spurious waves are further outside the bandwidth B TF of the tracking filter and are more strongly damped or completely suppressed.
  • the reference frequency generators RG1 and RG2 not only generate the selected reference frequencies f RG1 and f RG2 , but also their multiples.
  • the resulting frequency grid with the closest line or sub-wave spacing is emitted by the reference frequency generator RG1 when the lowest frequency f RG1min is generated .
  • the minimum line spacing of this frequency grid which is fed to the tracking filter, therefore corresponds to the value of the frequency f RG1min .
  • Formula (2) also contains all mixed products that result from mixing the different frequency grids.
  • the auxiliary shafts are only blocked if the required line spacing is never undershot.
  • the frequency grid of f res has a minimum line spacing which corresponds to the frequency f RG1min .
  • the smallest possible line spacing of the output frequency f sA from the next secondary lines or secondary waves consequently corresponds to the value of the frequency f RG1min .
  • the tracking filter suppresses the resulting spurious waves.
  • the number of frequency channels can be increased by supplying the offset reference frequency f OR and the mixed product (f or - f RG2 ) to the output of the offset stage OS, for example via a multiplexer, in addition to the frequency (f or + f RG2 ).
  • the number of frequency channels K max can be increased as desired or an entire frequency band can be covered by a rasterized or variable change in the offset reference frequency f OR .
  • the signal may a frequency multiplication stage are supplied to A s which f SA with a desired factor multiplies the frequency and feeds the output of the frequency synthesizer.
  • the minimum period of time that the described frequency synthesizer requires for a frequency change corresponds approximately to the settling time of the phase-controlled control loop to a new frequency. Shorter switchover times are made possible in that the outputs of two or more frequency synthesis devices according to the invention, which cover identical or different frequency channels, are interconnected via a multiplexer. The output of the frequency synthesizer, which generates the current output frequency f sA , is selected by the multiplexer. In the further frequency synthesis devices, the frequencies required in the future will be set and kept ready so that they can be selected immediately by the multiplexer.
  • the input of the voltage-controlled oscillator VCO can be controlled directly via a digital-to-analog converter, via which the desired frequency f sA is selected digitally.
  • Frequencies that do not correspond to the adjustable frequency channels can be generated with reduced quality (secondary waves and increased phase noise) by feeding the signal s M1 to a frequency divider that has a division ratio of one in normal operation and a corresponding division ratio not equal to one to generate the desired additional frequencies Has.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
EP89114052A 1988-10-18 1989-07-29 Appareil synthétiseur de fréquence Expired - Lifetime EP0364679B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH387688 1988-10-18
CH3876/88 1988-10-18

Publications (2)

Publication Number Publication Date
EP0364679A1 true EP0364679A1 (fr) 1990-04-25
EP0364679B1 EP0364679B1 (fr) 1994-11-02

Family

ID=4265385

Family Applications (1)

Application Number Title Priority Date Filing Date
EP89114052A Expired - Lifetime EP0364679B1 (fr) 1988-10-18 1989-07-29 Appareil synthétiseur de fréquence

Country Status (3)

Country Link
US (1) US5019785A (fr)
EP (1) EP0364679B1 (fr)
DE (1) DE58908588D1 (fr)

Families Citing this family (20)

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Publication number Priority date Publication date Assignee Title
US5084681A (en) * 1990-08-03 1992-01-28 Hewlett-Packard Company Digital synthesizer with phase memory
JP2674295B2 (ja) * 1990-10-05 1997-11-12 日本電気株式会社 速度変換回路
US5317202A (en) * 1992-05-28 1994-05-31 Intel Corporation Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle
US5329260A (en) * 1992-07-17 1994-07-12 Ii Morrow Inc. Numerically-controlled modulated oscillator and modulation method
US5351015A (en) * 1993-02-03 1994-09-27 Silicon Systems, Inc. Time based data separator zone change sequence
DE4324527A1 (de) * 1993-07-21 1995-01-26 Siemens Ag Anordnung zur Frequenzaufbereitung für zwei Frequenzbänder
WO1995030202A1 (fr) * 1994-05-03 1995-11-09 Payne, Nicholas, William, Prideaux Synthetiseur numerique de frequences
JP3467880B2 (ja) * 1994-12-26 2003-11-17 ソニー株式会社 クロック信号発生装置
TW337054B (en) 1995-09-28 1998-07-21 Toshiba Co Ltd Horizontal synchronous signal oscillation circuit
JP3695819B2 (ja) 1996-01-16 2005-09-14 株式会社東芝 信号処理回路及びこれを用いた再生装置
KR100193862B1 (ko) * 1996-03-19 1999-06-15 윤종용 안정된 주파수를 얻기 위한 주파수변환기
JP4319259B2 (ja) * 1996-07-02 2009-08-26 株式会社東芝 アクティブ・ワイドレンジｐｌｌ装置、位相ロックループ方法及びディスク再生装置
US6137995A (en) * 1998-12-08 2000-10-24 Motorola, Inc. Circuit and method of generating a phase locked loop signal having an offset reference
FR2791213B1 (fr) * 1999-03-16 2001-05-25 Sagem Dispositif et procede d'emission dans un telephone mobile
SE517967C2 (sv) 2000-03-23 2002-08-06 Ericsson Telefon Ab L M System och förfarande för klocksignalgenerering
US6297703B1 (en) * 2000-09-01 2001-10-02 Motorola, Inc. Method and apparatus for producing an offset frequency
US6556051B2 (en) * 2000-10-04 2003-04-29 Via Technologies, Inc. Apparatus for providing both supports including synchronous dynamic random access memory (SDRAM) module and double data rate (DDR) DRAM module
US6965224B1 (en) * 2003-05-16 2005-11-15 Cisco Technology, Inc. Method and apparatus for testing synchronization circuitry
JP2005129993A (ja) * 2003-10-21 2005-05-19 Sony Corp 周波数合成装置及び周波数合成方法
US8221343B2 (en) 2005-01-20 2012-07-17 Flowcardia, Inc. Vibrational catheter devices and methods for making same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1177697B (de) * 1961-09-22 1964-09-10 Fernseh Gmbh Verfahren zur Gewinnung einer Frequenz, die von einer konstanten gegebenen Frequenz um einen konstanten im Vergleich zu ihr geringen Betrag abweicht
FR92133E (fr) * 1966-07-20 1968-09-27 Adret Electronique Générateur de signaux électriques sinusoïdaux du type dit synthétiseur de fréquence
GB2015277A (en) * 1977-11-30 1979-09-05 Plessey Co Ltd Frequency synthesizer
EP0147897A2 (fr) * 1983-12-27 1985-07-10 North American Philips Corporation Boucle d'asservissement de phase capable d'engendrer plusieurs signaux de fréquence stable

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GB238710A (en) * 1924-09-05 1925-08-27 Gordon Fraser An improved spindle and rove-stopping assembly for spinning frames and like textile machinery
US4070634A (en) * 1974-06-17 1978-01-24 Navidyne Corporation Phase comparison systems employing improved phaselock loop apparatus
JPH0752838B2 (ja) * 1985-03-20 1995-06-05 株式会社日立製作所 集積回路
JPS63238714A (ja) * 1986-11-26 1988-10-04 Hitachi Ltd クロック供給システム
EP0288007A3 (fr) * 1987-04-20 1990-03-28 Anritsu Corporation Appareil générateur de signaux utilisant un circuit à boucle d'asservissement de phase
US4878027A (en) * 1987-08-03 1989-10-31 Hewlett-Packard Company Direct frequency synthesizer using powers of two synthesis techniques
US4839603A (en) * 1987-09-24 1989-06-13 Unisys Corporation Multiple-loop microwave frequency synthesizer using two phase lockloops

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1177697B (de) * 1961-09-22 1964-09-10 Fernseh Gmbh Verfahren zur Gewinnung einer Frequenz, die von einer konstanten gegebenen Frequenz um einen konstanten im Vergleich zu ihr geringen Betrag abweicht
FR92133E (fr) * 1966-07-20 1968-09-27 Adret Electronique Générateur de signaux électriques sinusoïdaux du type dit synthétiseur de fréquence
GB2015277A (en) * 1977-11-30 1979-09-05 Plessey Co Ltd Frequency synthesizer
EP0147897A2 (fr) * 1983-12-27 1985-07-10 North American Philips Corporation Boucle d'asservissement de phase capable d'engendrer plusieurs signaux de fréquence stable

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN, Band 9, Nr. 185 (E-332)[1908], 31. Juli 1985; & JP-A-60 55 730 (NIPPON DENKI K.K.) 01.04.1985 *
THE RADIO & ELECTRONIC ENGINEER, Band 50, Nr. 3, März 1980, Seiten 122-126, Institution of Electronic and Radio Engineers, London, GB; G.A. WARWICK et al: "The fequency shifting synthesizer" *

Also Published As

Publication number Publication date
US5019785A (en) 1991-05-28
EP0364679B1 (fr) 1994-11-02
DE58908588D1 (de) 1994-12-08

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