EP0364590A1 - Verfahren und schaltung zur löschung einer flüssigkeitskristallanzeige - Google Patents

Verfahren und schaltung zur löschung einer flüssigkeitskristallanzeige Download PDF

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Publication number
EP0364590A1
EP0364590A1 EP89900891A EP89900891A EP0364590A1 EP 0364590 A1 EP0364590 A1 EP 0364590A1 EP 89900891 A EP89900891 A EP 89900891A EP 89900891 A EP89900891 A EP 89900891A EP 0364590 A1 EP0364590 A1 EP 0364590A1
Authority
EP
European Patent Office
Prior art keywords
drive circuit
gate
bus drive
gate bus
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP89900891A
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English (en)
French (fr)
Other versions
EP0364590B1 (de
EP0364590A4 (en
Inventor
Masaru Yasui
Noriyoshi Uenishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hosiden Corp
Original Assignee
Hosiden Electronics Co Ltd
Hosiden Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62331765A external-priority patent/JP2655328B2/ja
Priority claimed from JP33176487A external-priority patent/JPH01170989A/ja
Application filed by Hosiden Electronics Co Ltd, Hosiden Corp filed Critical Hosiden Electronics Co Ltd
Publication of EP0364590A1 publication Critical patent/EP0364590A1/de
Publication of EP0364590A4 publication Critical patent/EP0364590A4/en
Application granted granted Critical
Publication of EP0364590B1 publication Critical patent/EP0364590B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • the present invention relates to a method and a circuit for erasing a display of an active matrix type liquid crystal display cell having a capacitive storage effect.
  • Fig. 1 shows a liquid crystal display panel 10 in which display pixels 12 are arranged in the form of a matrix (with m rows and n columns) and their display electrodes 12a are connected to drains of TFTs (Thin Film Transistors) 13, respectively.
  • the TFTs 13 have their sources and gates connected to those of perpendicularly intersecting source buses 14 1 to 14 n and gate buses 15 which correspond to them, respectively.
  • the display pixels 12 each include a counter electrode (also referred to as a common electrode) 12b disposed opposite the display electrode 12a.
  • a source bus drive circuit 16 is provided for driving the source buses 14 1 through 14 n .
  • the source bus drive circuit is supplied with a pixel clock PCK, a horizontal synchronizing signal Hs and a control signal M for converting the power supply voltage into an AC form, such as shown in Fig. 2, and pixel data (a binary code representing logic "1" or "0") D which is applied in the horizontal direction in synchronism with the pixel clock PCK, though not shown.
  • the pixel data D of one row are sequentially loaded into a shift register 16a in synchronism with the pixel clock PCK, and in correspondence to the pixel data D, signals S 1 to S n to be displayed on the pixels of one row of the liquid crystal display panel 10 are simultaneously provided on the source buses 4 1 to 4 n upon each occurrence of the horizontal synchronizing signal Hs.
  • the source bus drive circuit 16 operates on the DC voltages E 1 , E 2 and E 3 and a common potential EG (zero volt) from the main body of the liquid crystal display device.
  • the liquid crystal display panel 10 is also supplied with the common potential EG from the main body of the display device and the counter electrodes of the respective pixels are each supplied with a voltage corresponding to the voltage E 2 .
  • the common potential EG zero volt
  • the voltages E 1 , E 2 and E 3 are selected such that E 1 > EG > E 2 > E 3 , for instance.
  • a gate bus drive circuit 17 drives the gate buses 15 1 to 15 m high-level one after another upon each occurrence of the horizontal synchronizing signal Hs, thereby turning ON the TFTs of one row from the first to the mth row in a sequential order.
  • the source bus drive signals S 1 to S n are applied to the corresponding pixels, respectively.
  • the gate bus drive circuit is made up principally of an m-stage shift register 18 and a gate bus driver 19.
  • a vertical synchronizing signal Vs (Fig. 2E) is applied, as a start signal, to a data terminal D of the first-stage shift register, and the horizontal synchronizing signal Hs is applied to a clock terminal CK of each stage.
  • Pulses which result from sequential delaying of the start signal for the horizontal synchronizing signal period, are provided from output terminals Q of the respective stages to the gate bus driver 19.
  • the input pulses are converted in level, providing on the gate buses 15 1 to 15 m gate bus drive signals G 1 to G m (Fig. 2F) each of which has a voltage level V 1 or V 3 depending on whether the input pulse from the corresponding stage is high- or low-level.
  • pixel data for one field which have logic "0" for erasing displays of respective pixels are provided from the main body of the device, and upon each occurrence of the horizontal synchronizing signal Hs, voltage E 2 signals for m rows are simultaneously applied from the source bus drive circuit 16 to the source buses 14 1 through 14 n and the gate buses 15 1 through 15 m are sequentially driven high-level by the gate bus driver 17, whereby the display of one field is cleared. That is, clearing of one field display needs a time mT H (where T H is the cycle of the horizontal synchronizing signal) at the shortest. This is not preferable because, for example, when the liquid crystal display panel 10 is used with a computer, the higher the display-clearing frequency, the longer the time for which the computer is occupied.
  • An object of the present invention is to provide a liquid crystal display erasing method which permits clearing of a display on a liquid crystal display panel in a markedly shorter time than in the past.
  • Another object of the present invention is to provide a liquid crystal display erasing circuit which permits clearing of a residual image in a short time upon turning OFF the power supply of a display device and prevents shortening of liquid crystal and lowering of its reliability.
  • pixel data for clearing the display corresponding to display elements of one row, is applied to a source bus drive circuit, by which all source buses are simultaneously driven to the voltage level corresponding to the above-mentioned pixel data for a predetermined period of time, during which all outputs of a gate bus drive circuit are simultaneously held at an active level by an erasing signal.
  • a power holding circuit is provided for holding power of the operating power supply to the gate bus drive circuit for a predetermined period of time after turning OFF of the power supply of the display device.
  • means is provided for detecting the turning OFF of the power supply of the display device, and by its detecting signal, the outputs of the gate bus drive circuit are simultaneously held at the active level for a predetermined period of time.
  • Fig. 3 there is shown an embodiment of the present invention as being applied to the liquid crystal display elements of Fig. 1, the parts corresponding to those in Fig. 1 are identified by the same reference numerals and no detailed description will be given of them.
  • the source bus drive circuit 16 and the liquid crystal display panel 10 are identical with those in Fig. 1.
  • the shift register 18 in the gate bus drive circuit 17 is made up of cascade-connected presettable D-type flip-flops, which are adapted so that their preset terminals P can be supplied with a clear signal CL at the same time.
  • the clear signal CL is created in accordance with an operator's instruction or under control of a program in a computer connected to the display device.
  • pixel data D of logic "0" for clearing the display, corresponding to one row of the display panel 10 is provided to the source bus drive circuit 16, from which source bus drive signals S 1 through S n of voltage corresponding to the above-mentioned pixel data, i.e. voltage E 2 equal to the voltage of the common electrodes 12b, are simultaneously applied to the source buses 14 1 through 14 n within one horizontal synchronization cycle.
  • the clear signal CL is provided to the preset terminal P of each stage of the shift register 18 in the gate bus drive circuit 17 as depicted in Fig. 3.
  • the duration T of the clear signal CL needs only to be equal to or longer than one cycle of the horizontal synchronizing signal Hs.
  • the Q output of each stage of the shift register 18 goes to a high level for the time T and the outputs G 1 through G m of the gate bus driver 19 also go to the high level. (In general, this level needs only to be high enough to activate the TFTs 13 of the liquid crystal display panel 10.) Thus all the TFTs 13 are simultaneously rendered ON during the time T. Consequently, the source bus drive signals S 1 through S n for clearing the display are supplied to all pixels with m rows and n columns, by which display images are cleared all at once within the time T.
  • Fig. 4 illustrates another embodiment of the present invention, in which an OR circuit 20 is provided between the shift register 18 and the gate bus driver 19 in the gate bus drive circuit 17 in Fig. 1.
  • Each OR gate of the OR circuit 20 is supplied at one input with the output of the corresponding stage of the shift register 18 and at the other input with the clear signal CL, and the output of each OR gate is applied to the gate bus driver.19.
  • the gate bus driver 19 yields high-level signals G 1 through G m all at once during the duration T of the input clear signal CL. Consequently,.display images can be cleared all over the display screen within one cycle of the horizontal synchronizing signal Hs as is the case with the embodiment shown in Fig. 3.
  • the source bus drive circuit 16 and the display panel 10 are identical with those in Fig. 1, and hence are not shown.
  • Fig. 5 illustrates another embodiment of the present invention in which the clear signal CL in the embodiment of Fig. 1 is produced upon turning OFF of the power supply of the display device main body.
  • the source bus drive circuit 16 and the liquid crystal display panel 10 are identical with those in Fig. 1, and hence are not shown.
  • a large-capacity capacitor 22b is charged via a diode 22a with the power supply voltage V 1 (which is the same as the voltage V 1 in the prior art example depicted in Fig. 1) which is applied from the liquid crystal display device main body to a terminal 21, and at the same time, the voltage V 1 is provided to the gate bus drive circuit 17.
  • the diode 22a and the capacitor 22b constitute a power holding circuit 22 which holds and supplies power to a load for a predetermined period of time after turning OFF of the power supply of the display device main body.
  • the output voltage V 1 ' of the power holding circuit drops below the input voltage V 1
  • the output of the power holding circuit 22 is also applied to a power circuit 23, wherein a voltage V 2 1 is created as a substitute for the source voltage V 2 which is supplied from the device main body in the prior art, and the voltage V2 is provided to the gate bus drive circuit 17.
  • Other voltages are the same as those used in the prior art example.
  • the gate bus drive circuit 17 is supplied with the voltage V 3 (which is a low-level voltage of the gate bus drive signal G i and is used to turn OFF the TFT 13), and though not shown, the source bus drive circuit 16 is supplied with voltages E 1 , E 2 and E 3 from the display device main body and the counter electrodes 12b of the liquid crystal display panel 10 are supplied with the voltage E 2 .
  • the supply of these voltages V 1 , V 3 , El, E 2 and E 3 is stopped when the power supply of the display device main body is turned OFF.
  • the voltage drop of the voltage V 1 is detected by a voltage drop detector 24, and at a time point t 2 when the voltage V 1 has dipped, for instance, 20% below a reference value, the voltage drop detector 24 changes to a low level its output V B held at a high level until then (Fig. 6B).
  • the output V B of the voltage drop detector 24 is applied to the output side of the power holding circuit 22 via a capacitor 25 and a resistor 26.
  • the junction F between the capacitor 25 and the resistor 26 is connected to an input terminal of an inverter 27.
  • the voltage V F at the junction F drops at the time t 2 and then gradually approaches, with a time constant CR (where C and R are the capacitance of the capacitor 25 and the resistance of the resistor 26, respectively), the output voltage V 1 ' of the power holding circuit 22 (Fig. 6C).
  • the inverter 27 To the inverter 27 are applied, as its operating voltages, the voltages V 1 ' and V 2 ' . After the time point t 2 the voltage V2 also drops to the common potential with a gradually decreasing time constant, together with the voltage V 1 ' . Since the threshold level V th of the inverter 27 is set to a level intermediated between the voltages V 1 ' and V 2 1 as depicted in Fig. 6C, the inverter 27 yields a high-level output V CL as the clear signal for a period of time T (t 2 -t 4 ) during which the input voltage V F to the inverter 27 is lower than the threshold level V th (Fig. 6D).
  • the waveform of the output V CL from the inverter 27 is substantially the same as that of the voltage V 1 ' in the time interval between t 2 and t 4 but is nearly equal to the waveform of the voltage V 2 ' except that time interval.
  • the pulse width T of the output clear signal CL from the inverter 27 is set to a value a little greater than the time during which the voltages E 1 , E 2 , V 1 and V 3 supplied to the liquid crystal display panel drop to the common potential when the power supply is turned OFF. That is, T > ( t 3 - t 3 ).
  • the output clear signal CL from the inverter 27 is applied to the preset terminal P of each stage of the shift register 18, and the Q output from each stage is rendered high-level (nearly equal to the voltage V 1 ' ) during the time T, and consequently, the outputs G 1 through G m of the gate bus driver 19 are also made high-level (which level needs only to be high enough to activate or turn ON the TFTs 13, substantially equal to the voltage V 1 ' in this instance). All the TFTs 13 of the liquid crystal display panel 10 described previously in conjunction with the prior art example are simultaneously turned ON during the time T, and consequently, the display electrode 12a of each pixel 12 is electrically connected via the TFT to the source bus driver 16b.
  • the source bus driver 16b is arranged so that the potential at its output terminal goes to the common potential EG at substantially the same time as the operating voltages E 1 , E 2 and E 3 drop to the common potential. That is, the source bus driver is designed so that the source bus driver signals S 1 through S drop to the common potential within the time T.
  • the display electrode 12a and the counter electrode 12b (the latter being supplied with the voltage E 2 ) are both supplied with the common potential within the time T, and charges stored in each pixel capacitance in accordance with the display being provided are entirely discharged by the end of the time T.
  • the time T includes the time necessary for discharging the charges stored in the pixel capacitances.
  • the gate bus drive circuit 17 in Fig. 5 may also be replaced with the circuit shown in Fig. 4. While the source bus drive circuit 16 in Fig. 3 has been described to drive the source buses 14 1 through 14 n in such a manner as to provide a binary or ON-OFF display in response to a binary pixel signal as is the case with the prior art example shown in Fig. 1, it is also easy for those skilled in the art to construct the source bus drive circuit 16 so that a half tone display may be provided using an analog video signal which has a half tone pixel level.
  • display images can be cleared within one cycle of the horizontal synchronizing signal, which is as short as 1/m (where m is the number of rows forming the display screen) of the one-field time needed in the past. Consequently, the display panel of the invention, when used as a display of a computer, is very advantageous in that the time for which the computer is occupied for clearing display images can be reduced accordingly.
  • the turning OFF of the power supply of the liquid crystal display device is automatically detected and the detection signal is used to hold the TFTs of the liquid crystal display elements in the ON stage for a predetermined period of time so that charges stored in the pixel capacitances can be discharged in a short time. This ensures clearing of residual images in a short time and prevents the reduction of the life of the liquid crystal and lowering of its reliability.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP89900891A 1987-12-25 1988-12-23 Verfahren und schaltung zur löschung einer flüssigkeitskristallanzeige Expired - Lifetime EP0364590B1 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP62331765A JP2655328B2 (ja) 1987-12-25 1987-12-25 電源オフ時の液晶表示消去方法
JP331764/87 1987-12-25
JP33176487A JPH01170989A (ja) 1987-12-25 1987-12-25 液晶表示消去方法
JP331765/87 1987-12-25
PCT/JP1988/001308 WO1989006416A1 (en) 1987-12-25 1988-12-23 Method of erasing liquid crystal display and an erasing circuit

Publications (3)

Publication Number Publication Date
EP0364590A1 true EP0364590A1 (de) 1990-04-25
EP0364590A4 EP0364590A4 (en) 1992-06-03
EP0364590B1 EP0364590B1 (de) 1995-06-14

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Application Number Title Priority Date Filing Date
EP89900891A Expired - Lifetime EP0364590B1 (de) 1987-12-25 1988-12-23 Verfahren und schaltung zur löschung einer flüssigkeitskristallanzeige

Country Status (3)

Country Link
EP (1) EP0364590B1 (de)
DE (1) DE3853998T2 (de)
WO (1) WO1989006416A1 (de)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0764932A2 (de) * 1995-09-07 1997-03-26 SAMSUNG ELECTRONICS Co. Ltd. Schaltung zum Löschen einer Anzeige, Flüssigkristallanzeigegerät mit dieser Schaltung, und Verfahren zu ihrer Ansteuerung
EP0881622A1 (de) * 1997-05-27 1998-12-02 International Business Machines Corporation Flüssigkristallanzeige mit aktiver Matrix und Schaltung zum Löschen der Anzeige bei Stromabschaltung
US5945970A (en) * 1996-09-06 1999-08-31 Samsung Electronics Co., Ltd. Liquid crystal display devices having improved screen clearing capability and methods of operating same
FR2783342A1 (fr) * 1998-09-15 2000-03-17 Lg Philips Lcd Co Ltd Appareil et procede d'elimination d'image residuelle pour un dispositif d'affichage a cristal liquide
WO2003052730A1 (en) * 2001-12-15 2003-06-26 Koninklijke Philips Electronics N.V. Active matrix liquid crystal display device with power down procedure
DE19828384B4 (de) * 1997-06-25 2004-01-29 Boe-Hydis Technology Co., Ltd. Flüssigkristallanzeige
KR100559216B1 (ko) * 1998-09-03 2006-06-13 비오이 하이디스 테크놀로지 주식회사 액정표시소자의 잔상제거회로
KR100734275B1 (ko) * 2005-10-04 2007-07-02 삼성전자주식회사 전원 전압 제거 감지 회로, 전원 전압 제거 시 잔상을제거하는 디스플레이 장치 및 방법
CN100367327C (zh) * 2003-09-28 2008-02-06 统宝光电股份有限公司 残留影像消除电路
KR100852170B1 (ko) * 2002-03-18 2008-08-13 삼성전자주식회사 액정표시패널 구동회로 및 이의 구동 방법
DE10138089B4 (de) * 2000-08-04 2011-05-12 Sharp K.K. Flüssigkeitskristall-Anzeigeeinrichtung
CN103714776A (zh) * 2012-09-28 2014-04-09 乐金显示有限公司 有机发光显示器和擦除其图像残留的方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5063706B2 (ja) * 2007-12-27 2012-10-31 シャープ株式会社 シフトレジスタおよび表示装置
US11210986B1 (en) * 2020-08-03 2021-12-28 Novatek Microelectronics Corp. Display driving apparatus and method

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EP0035382A1 (de) * 1980-02-29 1981-09-09 Fujitsu Limited Bausteinartig erweiterbare Anzeigevorrichtung und Anzeigebaustein dafür
JPS585792A (ja) * 1981-07-03 1983-01-13 株式会社日立製作所 液晶マトリクス表示装置
US4380008A (en) * 1978-09-29 1983-04-12 Hitachi, Ltd. Method of driving a matrix type phase transition liquid crystal display device to obtain a holding effect and improved response time for the erasing operation
JPS61162029A (ja) * 1985-01-11 1986-07-22 Sharp Corp 液晶駆動回路
JPS62165630A (ja) * 1986-01-17 1987-07-22 Seiko Epson Corp 電気光学装置の駆動方法

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JPS534853U (de) * 1976-06-29 1978-01-17
US4380008A (en) * 1978-09-29 1983-04-12 Hitachi, Ltd. Method of driving a matrix type phase transition liquid crystal display device to obtain a holding effect and improved response time for the erasing operation
EP0035382A1 (de) * 1980-02-29 1981-09-09 Fujitsu Limited Bausteinartig erweiterbare Anzeigevorrichtung und Anzeigebaustein dafür
JPS585792A (ja) * 1981-07-03 1983-01-13 株式会社日立製作所 液晶マトリクス表示装置
JPS61162029A (ja) * 1985-01-11 1986-07-22 Sharp Corp 液晶駆動回路
JPS62165630A (ja) * 1986-01-17 1987-07-22 Seiko Epson Corp 電気光学装置の駆動方法

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PATENT ABSTRACTS OF JAPAN vol. 010, no. 369 (P-525) 10 December 1986 & JP 61 162029 A (SHARP KK) 22 July 1986 *
PATENT ABSTRACTS OF JAPAN vol. 12, no. 006 (P-653)9 January 1988 & JP-A-62 165 630 ( SEIKO EPSON CORP. ) 22 July 1987 *
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Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0764932A3 (de) * 1995-09-07 1997-05-02 Samsung Electronics Co Ltd
US5793346A (en) * 1995-09-07 1998-08-11 Samsung Electronics Co., Ltd. Liquid crystal display devices having active screen clearing circuits therein
EP0764932A2 (de) * 1995-09-07 1997-03-26 SAMSUNG ELECTRONICS Co. Ltd. Schaltung zum Löschen einer Anzeige, Flüssigkristallanzeigegerät mit dieser Schaltung, und Verfahren zu ihrer Ansteuerung
US5945970A (en) * 1996-09-06 1999-08-31 Samsung Electronics Co., Ltd. Liquid crystal display devices having improved screen clearing capability and methods of operating same
EP0881622A1 (de) * 1997-05-27 1998-12-02 International Business Machines Corporation Flüssigkristallanzeige mit aktiver Matrix und Schaltung zum Löschen der Anzeige bei Stromabschaltung
DE19828384B4 (de) * 1997-06-25 2004-01-29 Boe-Hydis Technology Co., Ltd. Flüssigkristallanzeige
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KR100852170B1 (ko) * 2002-03-18 2008-08-13 삼성전자주식회사 액정표시패널 구동회로 및 이의 구동 방법
CN100367327C (zh) * 2003-09-28 2008-02-06 统宝光电股份有限公司 残留影像消除电路
KR100734275B1 (ko) * 2005-10-04 2007-07-02 삼성전자주식회사 전원 전압 제거 감지 회로, 전원 전압 제거 시 잔상을제거하는 디스플레이 장치 및 방법
CN103714776A (zh) * 2012-09-28 2014-04-09 乐金显示有限公司 有机发光显示器和擦除其图像残留的方法
CN103714776B (zh) * 2012-09-28 2016-02-10 乐金显示有限公司 有机发光显示器和擦除其图像残留的方法

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DE3853998D1 (de) 1995-07-20
DE3853998T2 (de) 1995-11-23
EP0364590B1 (de) 1995-06-14
WO1989006416A1 (en) 1989-07-13
EP0364590A4 (en) 1992-06-03

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