EP0350091B1 - Ladungsgekoppelte Anordnung mit geneigtem Kanal - Google Patents

Ladungsgekoppelte Anordnung mit geneigtem Kanal Download PDF

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Publication number
EP0350091B1
EP0350091B1 EP89201655A EP89201655A EP0350091B1 EP 0350091 B1 EP0350091 B1 EP 0350091B1 EP 89201655 A EP89201655 A EP 89201655A EP 89201655 A EP89201655 A EP 89201655A EP 0350091 B1 EP0350091 B1 EP 0350091B1
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EP
European Patent Office
Prior art keywords
cell
electrode
channel
charge
lateral direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP89201655A
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English (en)
French (fr)
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EP0350091A3 (en
EP0350091A2 (de
Inventor
Kei-Wean Calvin Yang
John Edward Taggart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Inc
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Tektronix Inc
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Publication date
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Publication of EP0350091A2 publication Critical patent/EP0350091A2/de
Publication of EP0350091A3 publication Critical patent/EP0350091A3/en
Application granted granted Critical
Publication of EP0350091B1 publication Critical patent/EP0350091B1/de
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66946—Charge transfer devices
    • H01L29/66954—Charge transfer devices with an insulated gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76833—Buried channel CCD
    • H01L29/76841—Two-Phase CCD

Definitions

  • the invention relates to a charge-coupled device (CCD) cell according to the precharacterizing part of claim 1.
  • a CCD cell of the above type is disclosed by EP-A-0 111 347 which shows a two-part electrode for each clock phase.
  • the potential under each of said two parts is essentially constant in the channel direction as shown in Fig. 2 of the present application.
  • a similar CCD-cell is disclosed by US-A-3.796.932.
  • the prior art cell comprises a single electrode, under the entire width in the lateral direction thereof the substrate potential is continuously graded so as to provide an electric field for propelling charge carriers in the lateral direction.
  • This prior art cell has the disadvantage that charge carriers may unintentionally tunnel from one cell to a next adjacent cell, which may even cause backflow of charge carriers during clock phase changes. This may cause interference with charges under adjacent electrodes or degradation of information gradient along several cells in the lateral direction and a decrease of a signal to noise ratio and charge transfer efficiency, in particular at low charge levels.
  • charge carriers beneath an electrode may be further than one-half electrode width from the next cell, which causes these charges have longer distances to travel, which increases the propagation time through the CCD or which decrease the operating frequency thereof.
  • a further prior art CCD cell is disclosed by US-A-4.035.906.
  • This prior art cell has a stepped electrode, one part of which having a smaller distance to the substrate than a second part of the electrode, seen in said lateral direction.
  • This prior art cell has disadvantages similar to those of a cell with a stepped channel dopant density described hereinafter with reference to fig. 2.
  • a two-phase, charge-coupled device (CCD) 10 comprises an array 12 of closely spaced polysilicon electrodes aligned along a lateral path on a silicon dioxide insulation layer 14 grown on the surface of a p-type silicon semiconductor substrate 16.
  • FIG. 1 is exaggerated in vertical dimension in order to illustrate structural detail. Electrodes of array 12 are isolated one from another by extensions of insulation layer 14. A portion of substrate 16 under array 12 is doped to form an n-type channel region 18 between n+ input and output diffusion regions 20 and 22.
  • Channel region 18 preferably provides a buried channel for conducting charge carriers in a lateral direction under the electrode array 12. However in alternative embodiments of the invention, channel region 18 may provide a surface channel.
  • Charge-coupled device 10 is surrounded by a p+ guard ring diffusion region 24 covered by a field oxidation layer 26.
  • An n+ floating diffusion region 28 intersects channel region 18 near the output diffusion region 22.
  • Metallic contacts 30, 32, and 34 extend through insulation layer 14 to provide connections to diffusion regions 20, 28 and 22, respectively.
  • the electrodes of array 12 include a "sample gate” electrode 36, a "sample well” electrode 38, a sequence of CCD cell electrode pairs 40, and a “last gate” electrode 42.
  • An additional “reset” electrode 44 lies above the portion of channel region 18 between diffusion regions 28 and 22.
  • Each CCD cell electrode pair 40 along with the portion of insulation layer 14 and substrate 16 therebelow, comprises a separate "cell” 50 of the charge-coupled device. Many such cells are included in the charge-coupled device.
  • Charge-coupled device 10 samples an input signal applied to contact 30 above input diffusion region 20 and stores a packet of charge in channel region 18 under sample gate electrode 36. The amount of stored charge is proportional to the voltage of the input signal. The charge packet thereafter shifts laterally from cell-to-cell through channel region 18 to floating diffusion region 28. Contact 32 above floating diffusion region 28 is suitably connected to an amplifier 46 producing an output voltage proportional to the charge in the floating diffusion region. The charge packet thereafter shifts from floating diffusion region 28 to output diffusion region 22 via the channel region 18 therebetween. Output diffusion region 22 is connected to a constant voltage source VOD that removes the charge packet from the output diffusion region.
  • VOD constant voltage source
  • Sampling of the input signal applied to contact 30 and shifting of the resulting charge packet through channel region 18 to output diffusion region 22 are controlled in a well-known manner by a set of phased clock signals SG, SW, P1, P2, LG and RESET.
  • the SG, SW, LG and RESET clock signals are applied to electrodes 36, 38, 42 and 44 respectively.
  • the P1 and P2 clock signals are applied to electrode pairs 40 of alternate CCD cells 50.
  • the present invention relates to an improved CCD cell 50.
  • a typical two-phase CCD cell of the prior art is first described.
  • the prior art CCD cell 50′ includes a polysilicon electrode pair 40a′ and 40b′ insulated from a doped n-type channel region 18′ in a silicon substrate by a silicon dioxide insulation layer 14′.
  • electrodes 40a′ and 40b′ are interconnected for receiving the same clock signal P1 or P2.
  • the "+" symbols in channel region 18′ represent the relative dopant density in the channel in the direction of carrier flow.
  • the dopant density in the channel region under each electrode 40a′ and 40b′ is uniform in the lateral direction, but the dopant density under electrode 40b′ is much higher than the dopant density under electrode 40a′.
  • the "stepped" channel dopant density causes a stepped built-in channel potential preventing charge carriers in the channel under electrode from flowing to the left.
  • FIG. 3 illustrates how charge carriers are shifted through three adjacent prior art CCD cells of FIG. 2.
  • a simplified sectional view of the three cells (cells 1-3) is illustrated at the top of FIG. 3.
  • clock signals P1 and P2 180 degrees out of phase with one another, drive electrodes of adjacent cells in an alternating fashion.
  • clock signal P1 is applied to electrodes of cells 1 and 3 while clock signal P2 is applied to electrodes of cell 2.
  • FIG. 3 includes a plot 60 of tne built-in channel potential of each cell as a function of distance along the lateral path of carrier flow in the channel.
  • the "built-in” channel potential is the relative potential of the channel when no clock signals are applied to the gates and no charge packets are stored at any point in the channel. As seen in FIG. 3, the built-in channel potential is constant and relatively high under one electrode of each cell (i.e., electrodes 70, 72 and 76) and constant but relatively low under the other electrode of each cell (electrodes 68, 74, and 78).
  • FIG. 3 also includes plots 61-63 of relative channel potential as a function of lateral distance along the channel at three different times T1 - T3 during movement of a charge packet through the charge-coupled device.
  • clock signal P1 is asserted and clock signal P2 is deasserted.
  • Clock signal P1 drives channel potentials across cells 1 and 3 below their built-in levels, while the channel potentials across cell 2 remain at their built-in levels.
  • Cell 1 currently stores a packet of charge carriers 66 under electrode 68.
  • the high potential gradient between areas of the channel under electrodes 70 and 68 of cell 1 and between the channel under electrode 72 of cell 2 and the channel under electrode 68 of cell 1 produce electric fields preventing carriers 66 from leaving the "potential well" under electrode 68.
  • clock signal P2 is asserted and clock signal P1 is deasserted.
  • clock signal P1 drives down channel potentials of cell 2.
  • Carriers 66 drift and diffuse from the channel area under electrode 68 of cell 1 through the channel under electrode 72 of cell 2 and into the channel under electrode 74.
  • clock signals P1 and P2 again switch states, thereby driving channel potentials of cells 1 and 3 low while permitting channel potentials in cell 2 to rise. Thereafter the carriers drift and diffuse from cell 2 through the channel under electrode 76 of cell 3 and into the channel under electrode 78.
  • FIG. 3 shows carriers 66 at time T3 flowing from cell 2 to cell 3 while clock signal P1 is asserted.
  • the "charge transfer efficiency" of a charge-coupled device is the ratio of charge transferred to a CCD cell from its neighbor cell during a clock phase to the initial charge stored by its neighbor cell at the beginning of the clock cycle. As the frequency of operation of a charge-coupled device increases, charge transfer efficiency decreases because less time is available for charge movement during each clock phase. A high charge transfer efficiency is necessary, particularly in charge-coupled devices having many cells, to prevent substantial degradation of charge packets passing from cell-to-cell through the charge-coupled device. The charge transfer efficiency of a charge-coupled device therefore limits the frequency of operation of a charge-coupled device.
  • FIG. 4 illustrates an improved buried channel CCD cell 50 in accordance with the present invention.
  • the CCD cell 50 is generally similar to the prior art CCD cell 50′ of FIG. 2 except that while the prior art cell 50′ has a substantially constant dopant concentration under electrode 40b′, cell 50 of the present invention has a graded dopant concentration under the corresponding electrode 40b.
  • FIG. 5 is similar to FIG. 3 but illustrates channel potentials and charge carrier packet 84 movement through three adjacent CCD cells of FIG. 4.
  • the built-in channel potential of the cells is illustrated by plot 80. Note that the built-in channel potential is uniformly high under the first electrode of each cell (i.e., electrodes 87-89) but relatively low and "tilted” under the other electrode of each cell (i.e., electrodes 91-93).
  • FIG. 5 also includes three plots 81-83 showing channel potential at times T1-T3 during lateral movement of charge packet 84 through the charge-coupled device channel in response to clock signals P1 and P2 in a manner similar to that described hereinabove with reference to FIG. 3.
  • the channel region under electrodes 91-93 of cells 1, 2 and 3 of FIG. 5 have tilted potential gradients in the lateral direction and each tilted potential gradient generates an electrical field applying a lateral force on charge carriers within the channel regions under electrodes 91-93.
  • the electric field increases carrier drift rate in the lateral direction.
  • the increase in carrier drift rate is particularly noticeable during latter stages of a clock phase when carrier concentration and clock-induced potential gradients between neighboring cells are reduced.
  • the additional electrical field provided by the tilted potential gradient helps to sweep the last few carriers out of a cell during latter portions a clock phase when other carrier driving forces are low. Tilting the channel potential of each cell substantially improves charge transfer efficiency at higher clock frequencies.
  • FIGS. 6-11 illustrate steps of a method for fabricating the buried channel CCD cell 50 of FIG. 4 having graded channel doping causing a tilted channel potential.
  • the insulation layer 14 is grown on silicon substrate 16, and the channel region 18 of the p-type silicon substrate 16 is initially doped by implanting dopant ions such as P31+ at a controlled depth in the substrate (FIG. 6).
  • a first polysilicon cell electrode 40a is formed on insulation layer 14 and additional dopant ions are implanted into the portion of channel region 18 not under electrode 40a. Electrode 40a acts as a self-aligned implantation mask (FIG. 7).
  • a mask 96 formed by photolithographic technique is placed above one end of electrode 40a and above an adjacent portion of insulation layer 14. P31+ ions are again implanted in the substrate to increase dopant concentration in the portions of the channel not under electrode 40a or mask 96 (FIG. 8).
  • Mask 96 is then removed and replaced with a similar mask 97 (FIG. 9) laterally extending farther from electrode 40a.
  • the dopant concentration of the portion of channel region 18 still unmasked is further increased by additional ion implantation.
  • Mask 97 is thereafter removed and replaced with yet another mask 98 (FIG. 10), laterally extending still farther from electrode 40a. Additional ions are again implanted in unmasked portions of channel region 18.
  • the last mask and the portion of insulation layer 14 not under electrode 40a are removed (FIG. 11).
  • the insulation layer 14 is then regrown on the exposed surface of the substrate as well as over the upper surface of electrode 40a, and an additional electrode 40b is formed on insulation layer 14 to provide the resulting cell as illustrated in FIG. 4.
  • the built-in channel potential of a CCD cell is a function not only of the dopant concentration in the channel region, but also of dopant depth, of the thickness of the channel region, of the thickness of the insulation layer between the electrode and substrate, and of the work function of the electrode. Accordingly, those skilled in the art will understand that the built-in channel potential of a cell can be tilted by grading the dopant depth in the channel region, by grading the thickness of the insulation layer, by grading the thickness of the channel region, or by providing a cell electrode having a graded work function.
  • FIG. 12 illustrates a CCD cell 100 in accordance with an alternative embodiment of the invention wherein the built-in potential is graded under electrode 40b by grading the thickness of the insulation layer 14.
  • the thickness of insulation layer 14 may be graded by repetitively masking and oxidizing progressively larger portions of the substrate 16 under electrode 40b before the electrode is formed.
  • FIG. 13 illustrates a CCD cell 102 in accordance with another alternative embodiment of the invention wherein the built-in potential is graded under electrode 40b by grading the work function of electrode 40b. This may be accomplished by forming electrode 40b in several sections, each section having a different work function. The separate sections of electrode 40b along with electrode 40a are all connected to the same clock signal by a metallic layer (not shown).
  • a graded channel potential can also be obtained by providing graded clock signal potentials ro the electrodes.
  • yet another alternative embodiment of the invention has a sectioned electrode as in FIG. 13. However, the electrode sections are not interconnected and have similar work functions. To provide a tilted channel potential, a separate clock signal is applied to each electrode 40b section, each clock signal being of the same phase but having a different voltage magnitude.
  • FIG. 14 is a sectional view of a portion of a four-phase, charge-coupled device including seven cells 120.
  • Each cell 120 includes only a single electrode 122 and the portions of insulation layer 124 and substrate 126, including a channel region 128, therebelow.
  • Four clock signals P1-P4 applied to alternate cell electrodes are asserted sequentially.
  • FIG. 15 illustrates a single cell 120 in accordance with the invention suitable for use in the charge-coupled device of FIG. 14.
  • the built-in potential gradient in channel region 128 is tilted throughout the entire length of the cell under electrode 122 by grading the channel dopant concentration over the entire length of the cell.
  • the tilted channel potential gradient generates an electric field accelerating all charge carriers within tne channel in the lateral direction.
  • FIG. 16 illustrates channel potentials and charge carrier packet movement through six adjacent CCD cells similar to the cell of FIG. 15 arranged in a four-phase, charge-coupled device.
  • the cell electrodes 122 are illustrated in diagrammatic form across the top of FIG. 16.
  • Clock signal P1 is applied to the electrode of cells 1 and 5
  • clock signal P2 is applied to electrodes of cells 2 and 6
  • clock signal P3 is applied to the electrode of cell 3
  • clock signal P4 is applied to the electrode of cell 4.
  • the built-in channel potential of each cell 1-6 is illustrated by plot 132. Note that the built-in channel potential is tilted in the lateral direction under the full length of each electrode 122 of each cell.
  • FIG. 16 illustrates channel potentials and charge carrier packet movement through six adjacent CCD cells similar to the cell of FIG. 15 arranged in a four-phase, charge-coupled device.
  • the cell electrodes 122 are illustrated in diagrammatic form across the top of FIG. 16.
  • Clock signal P1 is applied to the electrode of cells 1
  • 16 also includes three plots 134-136 of channel potential as a function of lateral distance at times T1-T3 during movement of charge packets 138 and 140 through the charge-coupled device channel in response to clock signals P1-P4.
  • clock signal P1 is asserted and clock signals P2-P4 are deasserted.
  • the channel potentials in cells 1 and 5 are low and cells 1 and 5 store charge packets 138 and 140.
  • clock signal P2 is asserted
  • channel potentials in cells 2 and 6 are driven low and potentials in cells 1 and 5 are high. Charge packets 138 and 140 move to cells 2 and 6.
  • the channel potential gradient in each cell is flat over substantially all its length in the direction of lateral carrier flow.
  • a resulting electric field applies a lateral force on charge carriers within the channel region increasing carrier drift, thereby substantially improving charge transfer efficiency particularly at a higher clock frequencies.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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Claims (7)

  1. . Zelle für eine zweiphasige ladungsgekoppelte Anordnung jener Art, die ein Halbleitersubstrat (16) mit einer Isolierschicht (14), die über dem Substrat gebildet ist, und eine Elektrode (40), die über der Isolierschicht gebildet ist, umfasst und ein Einbaupotentialgefälle in einer seitlichen Richtung aufweist, wobei das Substrat einen Kanalbereich (18) umfasst, der sich zusammen mit der Elektrode in seitlicher Richtung erstreckt, um in Antwort auf ein zur Elektrode geführtes elektrisches Signal Ladungsträger unter die Elektrode zu leiten, wobei die Elektrode (40) zwei Teile (40a, 40b) umfasst, welche durch Ausbreitung der erwähnten Isolierschicht (14) voneinander isoliert sind, und welche miteinander verbunden sind, um das gleiche Taktsignal zu empfangen, und wobei die Zelle einen ersten Kanalbereich unter einem ersten Teil (40a) der Elektrode mit einem im wesentlichen homogenen Einbaupotential in seitlicher Richtung umfasst, das ein minimales elektrisches Feld in seitlicher Richtung erzeugt, sowie einen zweiten Kanalbereich unter einem zweiten Teil (40b) der Elektrode umfasst, dadurch gekennzeichnet, dass der erwähnte zweite Teil ein in seitlicher Richtung kontinuierlich abgestuftes Einbaupotential aufweist, um ein Ladungsträger in seitlicher Richtung antreibendes elektrisches Feld zu erzeugen.
  2. Zelle nach Anspruch 1, dadurch gekennzeichnet, dass der erste und zweite Kanalbereich zwischeneinander einen Einbaupotentialunterschied aufweisen.
  3. Zelle nach Anspruch 1, dadurch gekennzeichnet, dass der zweite Kanalbereich eine in seitlicher Richtung kontinuierlich abgestufte Dotierstoffkonzentration aufweist.
  4. Zelle nach Anpruch 1, dadurch gekennzeichnet, dass die Isolierschicht über dem zweiten Kanalbereich eine in seitlicher Richtung kontinuierlich abgestufte Dicke aufweist.
  5. Zelle nach Anspruch 1, dadurch gekennzeichnet, dass eine Arbeitsfunktion der Elektrode in seitlicher Richtung abgestuft ist, und zwar koextensiv mit dem zweiten Kanalbereich.
  6. Zelle nach Anspruch 1, dadurch gekennzeichnet, dass der Kanalbereich im wesentlichen unter einer Oberfläche des Substrats vergraben ist.
  7. Zelle nach Anspruch 1, dadurch gekennzeichnet, dass der erste Teil (40a) seitlich koextensiv mit dem ersten Kanalbereich und der zweite Teil (40b) seitlich koextensiv mit dem zweiten Kanalbereich ist.
EP89201655A 1988-07-07 1989-06-22 Ladungsgekoppelte Anordnung mit geneigtem Kanal Expired - Lifetime EP0350091B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/216,079 US4992842A (en) 1988-07-07 1988-07-07 Charge-coupled device channel with countinously graded built-in potential
US216079 2000-07-06

Publications (3)

Publication Number Publication Date
EP0350091A2 EP0350091A2 (de) 1990-01-10
EP0350091A3 EP0350091A3 (en) 1990-09-05
EP0350091B1 true EP0350091B1 (de) 1993-12-29

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EP89201655A Expired - Lifetime EP0350091B1 (de) 1988-07-07 1989-06-22 Ladungsgekoppelte Anordnung mit geneigtem Kanal

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EP (1) EP0350091B1 (de)
JP (1) JPH0258340A (de)

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JPH0728031B2 (ja) * 1989-02-11 1995-03-29 日本電気株式会社 電荷転送装置
JP2509740B2 (ja) * 1989-07-07 1996-06-26 株式会社東芝 電荷転送装置
KR930000720B1 (ko) * 1990-01-29 1993-01-30 금성일렉트론 주식회사 자기정열을 이용한 ccd 채널의 제조방법
EP0485125B1 (de) * 1990-11-09 1996-07-10 Matsushita Electronics Corporation Ladungsträgeranordnung, Verfahren zu ihrer Herstellung und Verfahren zu ihrer Steuerung
JPH04337670A (ja) * 1991-05-14 1992-11-25 Sony Corp Ｃｃｄシフトレジスタ
JP3042788B2 (ja) * 1993-03-19 2000-05-22 日本冶金工業株式会社 耐酸化性に優れたフェライト系ステンレス鋼
US5705836A (en) * 1995-05-22 1998-01-06 Dalsa, Inc. Efficient charge transfer structure in large pitch charge coupled device
US5793070A (en) * 1996-04-24 1998-08-11 Massachusetts Institute Of Technology Reduction of trapping effects in charge transfer devices
JP3011137B2 (ja) 1997-06-27 2000-02-21 日本電気株式会社 電荷転送装置およびその製造方法
JP3248470B2 (ja) * 1997-11-21 2002-01-21 日本電気株式会社 電荷転送装置および電荷転送装置の製造方法
US7719036B2 (en) * 2005-09-02 2010-05-18 Imagerlabs, Inc. Charge coupled device with high quantum efficiency
JP2016162788A (ja) * 2015-02-27 2016-09-05 ソニー株式会社 撮像素子、撮像装置、並びに、製造装置および方法

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JPH0258340A (ja) 1990-02-27
EP0350091A3 (en) 1990-09-05
US4992842A (en) 1991-02-12
EP0350091A2 (de) 1990-01-10

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