Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04W—WIRELESS COMMUNICATION NETWORKS
  • H04W84/00—Network topologies
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04W—WIRELESS COMMUNICATION NETWORKS
  • H04W8/00—Network data management
  • H04W8/22—Processing or transfer of terminal data, e.g. status or physical capabilities
  • H04W8/24—Transfer of terminal data
  • H04W8/245—Transfer of terminal data from a network towards a terminal
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
  • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
  • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
  • B41J2/435—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material
  • B41J2/447—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources
  • B41J2/45—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources using light-emitting diode [LED] or laser arrays
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F8/00—Arrangements for software engineering
  • G06F8/60—Software deployment
• • G—PHYSICS
  • G08—SIGNALLING
  • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
  • G08B3/00—Audible signalling systems; Audible personal calling systems
  • G08B3/10—Audible signalling systems; Audible personal calling systems using electric transmission; using electromagnetic transmission
  • G08B3/1008—Personal calling arrangements or devices, i.e. paging systems
  • G08B3/1016—Personal calling arrangements or devices, i.e. paging systems using wireless transmission
  • G08B3/1025—Paging receivers with audible signalling details
  • G08B3/1066—Paging receivers with audible signalling details with other provisions not elsewhere provided for, e.g. turn-off protection
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04W—WIRELESS COMMUNICATION NETWORKS
  • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
  • H04W88/02—Terminal devices
  • H04W88/022—Selective call receivers

Definitions

• This invention relates generally to the field of portable communication systems and in particular, to portable radio frequency receiver devices which contain reprogrammable memories capable of being selectively reprogrammed by received radio signals to alter the decoding and alerting characteristics of the receiver.
• the paging systems that support the operation of paging devices have grown from small on-site and one-city systems to very large wide area systems that can cover most of a state, or even an entire nation as evidenced by the nationwide paging systems used in Europe.
• the coding systems used in binary based signalling systems have evolved very rapidly as shown by the recent proposed plans to increase the bit rate of the standard POCSAG code from 512 bits per second to 1200 bits per second. This proposal occurred only a few years after the POCSAG code was adopted as a standard.
• Some reprogramrning capabilities have been provided for communication devices such as mobile radio telephones in that certain personalizing characteristics of the radio can be encoded in an electrically erasable PROM which can be field programmed.
• the radio unit is connected to some sort of field test fixture which overrides the internal commands to cause reprogramrning of the information, generally in a specific reserved memory area. While such developments enable a much broader utilization of devices in communication systems, direct access to the device is required to enable any changes to be made.
• Such prior art developments fail to recognize that an ideal communications system would enable a transmission station to exercise complete control over all of the characteristics of the plurality of receiver devices to which it is capable of broadcasting. Since a large proportion of communications systems are one-way (i.e. paging systems), this would enable the central transmission station or terminal to control the total message throughput capability of the plurality of receivers operating in its system.
• a goal of the present invention is to solve some of the problems associated with the rapid changes taking place in the paging business by providing a system in which a receiver can be modified by over-the-air commands.
• the goal is to provide a system in which a receiver device can be totally reconfigured via over-the-air commands and data transmissions in terms of the signalling system it can decode and the features and options it can provide.
• the new selective call receiver design is flexible enough to provide for a total change of the signalling system and correspondingly the operating characteristics of all of the receivers operating within the system, as well as providing the means for changing the features and options in any subset of the selectable receiver units.
• the transmission station or terminal would now have the capability of identifying individual receivers and then designating which coding system a receiver can receive.
• the transmission station operator by knowing the types of messages that are transmitted to various collections of receivers, can select the best coding system format mix for various users to maximize the throughput operation of his communication system.
• the present invention will enable the terminal operator to take advantage of the ever-increasing technological advances with respect to coding systems and the advancements particularly in digitally formatted communication systems. Rather than having thousands of receivers in the field with limited capability, as new technological aspects become available, the terminal operator could selectively address appropriate receivers and make whatever changes are necessary to update and maximize the communication message capability of the established communication system.
• a communication receiver which can decode signals transmitted by radio frequency propogation.
• a programmable controller uses instructions in a reprogrammable memory to decode and process the signals, and to output the information contained in the signals in a useable form.
• the controller also responds to predetermined signals by decoding and processing information on new decoding and operating instructions, and stores the data in a temporary memory.
• Logic circuitry responds to subsequent predetermined signals to enable selective reprogramrning of the reprogrammable memory to alter the decoding characteristics of the receiver.
• the device acts as a conventional communications receiver.
• data transmitted from a remote terminal location to a selected receiver will be loaded into its temporary memory and subsequently transferred to the reprogrammable memory to achieve the alteration of the decoding and operational characteristics of the receiver.
• the present or currently programmed message coding format is used to transmitt reprogramrning data to provide altered characteristics or features for the operation of a receiver while retaining the present message coding format.
• Another embodiment of this invention provides the receiver with the capability of receiving an entirely new coding format, temporarily storing and checking it for errors and, in response to a transmitted command, entirely replacing the former message decoding format with the new format.
• FIG. 1 is a functional block diagram of a receiver employing the present invention which is capable of being reprogrammed by signals received over a radio frequency communication link.
• FIGS. 2A, 2B, and 2C comprise descriptive diagrams of the POCSAG signal coding format and code word structure that is widely used in the paging art.
• FIGS. 3A and 3B comprise descriptive diagrams showing how the POCSAG address code word format can be used to selectively address a given receiver and to effect changes in the selected receiver device.
• FIG. 3C is a table listing that portion of the POCSAG address code word designated as function bits and their utilization in a receiver device employing the present invention to change information in the address code memory.
• FIGS. 3D and 3E show descriptive diagrams of the POCSAG qode word and data transmission sequence for reprogramrning the address code memory in an individual unit.
• FIG. 3 is a table of the function bit portion of the POCSAG reserved code word #1 of FIG. 3E and its utilization in a receiver device employing the present invention.
• FIG. 4 is a map of the reprogrammable address memory showing the correlation between the function bit table of FIG. 3F and the addressable memory regions in the code memory .
• FIGS. 5A and 5B comprise descriptive diagrams showing a transmission of reserved POCSAG code word #2 followed by data words to a population of receivers to alter the coding system of the entire addressed population.
• FIG. 5C is a table listing of the functions assigned to the function bit patterns of reserved code word #2 shown in FIG. 5B for changing information in reprogrammable program memory.
• FIG. 5D comprises a descriptive diagram showing the POCSAG reserved code word #2 structure signal transmission for batch #1 of FIG. 5A for initiating a change of the signalling system.
• FIG. 5E comprises a descriptive diagram showing the message code word structure signal transmissions for batch #2 of FIG. 5A for effecting a change of the signalling system.
• FIG. 6 is a map of the reprogrammable program memory showing the correlation between the table of FIG. 5C and the addressable memory regions.
• FIGS. 7A and 7B comprise descriptive diagrams of the message transmission format used in the Golay Sequential Code.
• FIG. 7C is a descriptive diagram showing the structure of the several types of Golay Sequential Code (GSC) signals.
• FIG. 7D is a descriptive diagram showing the relative bit timing for the various signal components of the GSC transmissions.
• FIGS. 8A and 8B comprise descriptive diagrams of the GSC coding format as used for the transmission of information to an individual receiver device employing the present invention.
• FIG. 8C is a table listing the GSC signalling codes that may be used to change the information relating to the addresses or features contained in the address code memory of an individual receiver device.
• FIGS. 8D and 8E comprise descriptive diagrams of the GSC signalling sequence used to effect a change in the information in the address code memory of an addressed receiver unit.
• FIG. 8F is a table listing the combinations of the GSC reserved words 1 and 2 used to effect changes in various regions of the address code memory shown in FIG. 4.
• FIGS. 9A and 9B comprise descriptive diagrams of the GSC transmission sequence of reserved words 3 and 4, reserved words 5 and 6 and data blocks used to effect a change in the reprogrammable program memory of all units in a designated group.
• FIG. 9C is a table listing the combinations of GSC reserved words 5 and 6 used to effect changes in various regions of the reprogrammable program memory shown in FIG. 6.
• FIGS. 10A-E comprise a program flow chart showing the detection of POCSAG address code words and data words by a receiver employing the present invention including the logical branching to the appropriate portions of the flow chart based upon the detection of function bits, reserved words and program change data.
• FIGS. 11A-E comprise a program flow chart showing the detection of GSC address words and data blocks by a receiver employing the present invention including the logical branching to appropriate portions of the flow chart based upon detection of the possible combinations of address words, reserved words and program change data.
• the central transmission station or terminal is normally capable of using several different signalling formats to transmit information to a large population of paging receivers.
• the transmission may consist of various address signals which activate a predetermined alerting device to indicate to a pager user that a message has been received, the transmission of numeric signals to indicate a telephone number or other encoded message to which pager user is to respond, or the transmission of alphanumeric messages so that unique messages may be sent to to an addressed receiver.
• Such transmissions may be directed to one or more receivers by individually or collectively addressing them.
• several different types of signalling systems are intermixed on a time multiplexed basis.
• FIG. 1 is a functional block diagram of a receiver device employing the present invention.
• An antenna 30 is shown coupled to a receiver 32.
• Receiver 32 detects and demodulates signals transmitted from a remote location over a radio frequency communication link.
• ' receiver 32 may use any of a number of frequency tuning techniques including crystal channel elements or digitally synthesized frequency dividers and employ any of a number of modulation/demodulation formats including amplitude modulation or frequency modulation.
• FM frequency
• any of a number of types of other receivers may be used for generating an appropriate detected RF signal for analysis.
• the output of receiver 32 is coupled to an analysis and decoding system block 34 shown enclosed by broken lines. More particularly, the output of receiver 32 is coupled to an microcomputer controller 36. While the term microcomputer is utilized, it will be appreciated by those skilled in the art that a number of custom programmable logic circuits could be utilized to achieve the same controlling function as will be described in greater detail later. For purpose of describing the preferred embodiment, the implementation of the receiver device employing the invention will be by firmware stored in a memory portion of the microcomputer based controller. Microcomputer 36 includes a common bus line designated 38 which is used to couple it to a variety of additional devices. Any of a number of microcomputers would be suitable but a preferred device is a MC146805C4 or MC68HC11 microcomputer manufactured by Motorola, Inc.
• microcomputer 36 is coupled through common bus line 38 to a reprogrammable non-volatile system change program memory 40, a reprogrammable non-volatile reserved word memory 42, a permanent receiver unit identification memory 44, a reprogrammable non-volatile receiver system program memory 46, a temporary memory 48, and a reprogrammable non-volatile address code memory 50.
• Microcomputer 36 is also coupled to a memory programming logic element 52 containing programming control logic which in turn is coupled to reprogrammable paging system program memory 46, reprogrammable address code memory 50, reprogrammable system change program memory 40, and reprogrammable reserved word memory 42.
• microcomputer 36 is coupled to an annunciator to generate an alerting sequence to inform the user upon receipt of a message. While the term annunciator is used, it is intended that such device may be audible, visual, tactile or any combination of such stimulus devices to inform the user of the receipt and/or content of the message.
• the output of receiver 32 is coupled to microcomputer controller 36 which controls the overall decoding operation for whichever message encoding format is to be utilized at any given time.
• the function of the microcomputer controller 36 is to take the derived selective call message information from receiver 32 and process it according to a predetermined decoding format.
• a microcomputer controller may be utilized as the main decoding tool.
• the receiver is' an FSK receiver and the microcomputer controller is taking the derived binary digit levels from the discriminator output portion of the receiver and is processing them according to a predetermined digital word decoding format.
• the microcomputer controller 36 is responsive to the information contained in reprogrammable non-volatile system program memory 46, and executes the signal decoding algorithms contained therein.
• Memory 46 would contain all of the software information needed to allow the microcomputer to process and decode information encoded according to a predetermined signalling format.
• Reprogrammable non-volatile address code memory 50 is used to store the address code sequences that uniquely identify a receiving device and information to designate its characteristics and features
• reprogrammable non-volatile reserved word memory 42 is used to store address code sequences associated with a change in the address(es) or options of the individual unit, or in the signalling system.
• the microcomputer acts to compare received signal sequences with the sequences stored in memories 50 and 42 to determine if the selective call code signal(s) that address the individual unit have been received or if a system or unit change command has been received.
• the microcomputer controller will respond in the normal manner according to the information contained in address code memory 50 to activate annunciator 54 and alert the pager user that a message had been received.
• This sequence of operation is well known in the art and indeed U.S. Patent No. 4,518,961 describes such a microcomputer system.
• the microcomputer controller When a system or unit change command signal is received, the microcomputer controller responds by storing the new data in the temporary memory 48 and then transferring the data to the appropriate non-volatile memory.
• Address code memory 50 is more commonly referred to as the code plug and such a device is included with most paging receivers to carry information as to the specific address or addresses of the selective call unit and may also contain such things as information determining the alerting sequence mode or other features that will be initiated upon the receipt and detection of an address of the individual unit.
• Temporary memory 48 is used to provide for the reliable reprogramrning of the paging device.
• memory programming logic device 52 under the control of microcomputer controller 36 is used for accessing the non-volatile memories 40, 42, 46, and 50 for the purpose of reprogramrning then with data stored in temporary memory 48.
• the microcomputer When predetermined sequences of the control signals contained in address code memory 50 and reserved word memory 42 are received, the microcomputer begins to execute the instructions contained in system change program memory 40 and acts to decode subsequent data transmission that define a new signalling format.
• the data is first stored in temporary memory 48 and is transferred into memories 40, 42, 46, and 50 after the correctness and completeness of the data has been verified.
• a permanent unit I.D. memory 44 is provided so that regardless of the status or utilization of any paging code format, the receiver always has an identifiable permanent address.
• microcomputer controller 36 Upon receipt of predetermined reserved word signals which correspond to the information contained in reserved system word memory 42 and can be arbitrarily represented in any coding system, microcomputer controller 36 begins executing the program instructions contained in the system change program memory 40 to process subsequent data transmissions. This data, which is transmitted in the format of the paging code currently being broadcast, constitutes the new program instructions to be used to decode a new signalling format or new information for code memory 50. In this operating mode, the microcomputer controller 36 loads the received data into temporary memory 48, then checks the data for errors, and loads the data into the appropriate non-volatile memories.
• the data that represents the instructions for decoding the new signalling system are programmed into the paging system program memory 46, the data corresponding to the new system change instructions are programmed into the system change program memory 40, and the data corresponding to the new reserved word signals are programmed into the reserved word memory 42.
• the new address signal(s) for the unit are derived from the permanent unit I.D. memory using an algorithm contained in the transmitted data, and the new address signal(s) are programmed into address code memory 50.
• an algorithm need not be transmitted. Rather, the new information may be transmitted directly.
• the reprogramrning of the various non-volatile memories for the decoder is accomplished by means of the memory programming logic 52.
• the microcomputer controller 36 directs the memory programming logic to set up a specific memory for reprogramrning and then sequentially inputs the data to the selected memory via the bus 38.
• the memory programming logic acts to enable the programming mode of the particular memory, and further prepares the memory to receive new data into a specified region of the memory map.
• the precise details of programming a non-volatile memory device, such as the EEPROM memory that is used in the preferred embodiment, are well known in the art and are not presented here.
• memory 42 is shown as a distinct memory, it is clear to those skilled in the art that it may be distributed in several locations, including paging system memory 46 and address code memory 50. Indeed, all of the memories shown in FIG. 1 could be physically incorporated into one memory device.
• a third method is to transmit the data several times with error correction algorithms and have the receiving device evaluate the received data and information and repeat the decoding process only for that portion of the transmission that appears to be in error. All of the three suggested error correcting are well known in the art (see, for example, "Error Control Techniques for Digital Communication", Arnold Michelson and Allen Levesque, 1985, John Wiley & Sons) and any of them may be used effectively.
• the final step of the system change procedure outlined above involves the derivation of new address signal(s) from the permanent unit I.D. memory.
• the information stored in the I.D. memory is processed in accordance with a transmitted algorithm to derive the address signal(s) assigned to that unit in the new signalling system.
• the unit I.D. information is stored as a binary sequence
• the algorithm used to derive the new address signal(s) is a binary transformation algorithm that might consist of multiplying the binary unit I.D. number by one or more binary sequences to obtain the new encoded address signals.
• the procedures for accomplishing such unit I.D. to signal code word transformation are well known in the art (see Chapter 4 of Michelson, et al., op. sit) and the mathematical details of the transformation procedure will not be presented.
• FIGS. 2A, 2B, and 2C show the standard message coding format for the paging system commonly known as POCSAG.
• Each transmission is at a normal bit rate of 512 bits per second and consists of a preamble code portion (not shown) followed by one or more batches of selectively arranged code words in eight predetermined time slots called frames.
• the preamble code initiates the asynchronous operational sequence and is immediately followed by a synchronization code word.
• Each batch is delineated by a synchronization code word, and the information in all batches following the first synchronization code word is transmitted synchronously.
• Each code word is a 32 bit data sequence which contains information for synchronization, for addressing an individual pager, or for transmitting data to an addressed pager.
• each batch of information begins with a 32 bit synchronization code word which is an invariant predetermined binary sequence.
• a batch that contains only address signals comprises a synchronization code word and sixteen address code words which are subdivided into the eight separate time sequence frames containing two address code words each.
• Subsequent address batches contain the same format of a 32 bit synchronization word followed by a total of 16 address code words.
• the address code words are grouped into eight frames numbered 0 to 7, and correspondingly, the entire pager address population is similarly divided into eight possible groups. Each pager address is allocated to one of the corresponding eight synchronous time frames according to the three least significant bits of its entire 21 bit address identity. Thus, all pagers having a unique address code word which ends in 000 would be positioned in frame 0, and similarly, all pagers having a unique address code word ending in 111 would be in frame 7.
• Address code words in the present format have a 32 bit structure and bit position 1 of an address code word is always 0 as shown in FIG. 2B. Bit position 1 of a data or message word is always 1 as shown in FIG. 2C.
• Bit positions 2-19 are the address information bits corresponding to the 18 most significant bits of the 21 bit address identity sequence assigned to an individual POCSAG pager unit. The three least significant bits are not transmitted since they merely serve to define the time frame in which the address code word must be transmitted and are therefore derivable from the frame position in a batch. Bit positions 20 and 21 comprise two function bits -which are used to select one function from the four possible functions assigned to the pager and would normally be used to activate different alerting sequences to the user. Bit positions 22 to 31 are parity check bits that are derived from the (31,21) BCH code format used to derive the POCSAG codewords, and the final bit position 32, is chosen to have a value that gives even parity for the entire code word.
• each pager ' s address code words must be transmitted in the specific time frame that is allocated to that unit.
• the pagers are sometimes referred to as being in groups which correspond to the frame designation.
• Each code word whether a synchronization code word or an address code word or message code word, follows the same 32 bit format in which the most significant bit is transmitted first.
• the structure of a message code word is shown in FIG. 2C.
• Message code words have 20 message bits, bit 2 to bit 21 inclusive, and these are followed by parity check bit patterns similar to those used for address code words.
• a message code word always starts with a 1, and the whole message always follows directly after the address code word that directs the message to a particular unit.
• the framing rules of the code format do not apply to message code words which occupy consecutive address positions until the message is completed and the next address code word is transmitted.
• Each message displaces at least one address code word or idle code word, and the displaced address code words are delayed and transmitted in the next available appropriate frame.
• message code words may continue into the next batch, the normal batch structure is maintained, i.e., the batch will consist of 16 code words, preceded by a synchronization code word.
• the transmission of address signals is
• an idle code word is transmitted.
• the idle code word is a valid address code word, which must not be allocated to pagers. It, like the synchronization code word, is an example of another reserved word in POCSAG.
• the 21 bit binary sequence used for pager identity in this coding system allows for two million combinations of possible addresses for pagers.
• FIGS. 3A and 3B, along with FIG. 3C, are descriptive diagrams that show how the present invention can be used in conjunction with the POCSAG system.
• FIG. 3A shows two batches of POCSAG code words.
• frame 3 of the first batch the address of an individual pager is shown followed immediately by the data 60 for features, options or perhaps address changes to the information contained in address code memory 50.
• This information may encompass the remainder of frame 3, frame 4, frame 5, frame 6, and a portion of frame 7 as shown generally. While it may be appreciated that changing to another decoding system would occupy perhaps more time than the frame positions for 4 through 7, what is shown is a less extensive change for the purpose of illustrating the transmission of information to an individual receiver device to alter information in its code memory.
• FIG. 3B shows the unique address code word which is sent in frame position 3 to address the individual pager and is identical in structure to the standard word format shown in FIG. 2B. Its position now in frame 3 is to indicate that an individual pager in frame or group 3 is being addressed.
• FIG. 3C is a table showing that the normal function bits (bit positions 20 and 21) in the standard POCSAG address code word may be utilized to provide either normal selective calling operation or to designate that a sequence is being initiated at the terminal to alter the programmed features, options or address(es) of the individual receiver and to activate the procedures for.changing a characteristic of the addressed unit.
• function bits 00, 01, and 10 may be utilized in their normal fashion to achieve various distinctive alerts which has been described as the generation of an annunciator signal pattern to designate to the receiver carrier that he has been addressed on a different address. For a numeric display or alphanumeric display pager, these function bits may cause the display of additional information along with an annunciation signal pattern to designate that a different message has been received.
• the function bits 11 are designated as the appropriate code to condition an individual pager to receive the re-programming sequence from the terminal to activate a change in the features, options or address information in the code memory using the present POCSAG signalling system.
• the advantage of a receiver device employing the present invention is that the pager user need have no knowledge that a change is occurring and that it is not necessary for him to intervene in any way. Rather, the terminal takes complete control of the reprogramrning operation of the pager. Thus, whenever a pager receives its normal address but with function bits designated as 11, the pager will be conditioned for the change.
• FIGS. 3A, B, and C show the transmission of information to an individual pager for the purpose of changing the features, options, or address information contained in the code memory.
• FIG. 3D is a repetition of FIG. 3A to show timing sequence correspondence for FIG. 3E. It will be appreciated by those skilled in the art that there is some small probability for falsing on a unique address transmission which could lead to an incorrect determination that it is the intention that the terminal is to change information in the address code memory.
• the unique address bit information in combination with the appropriate function bits, serves only to enable the decoder to look for an immediately subsequently transmitted reserved POCSAG code word 1.
• This reserved POCSAG code word 1 will activate the procedure for receiving new features, options and/or data, and for subsequently overwriting the information that is contained in the address code memory. As shown in FIG. 3E, the code plug change data is transmitted immediately subsequent to the reserve POCSAG code word number 1. This new information will be stored in temporary memory 48 under the control of the microcomputer controller 36.
• the reserve POCSAG code word number 1 has a format similar to the sync code and other reserved words in the POCSAG code system, which is a unique combination of bit sequences not otherwise -used for addresses in the system.
• FIG. 3F shows that the function bit portion of the transmitted reserved POCSAG code word 1 may be used to designate which of several regions in the address code memory are to be overwritten with the appropriately transmitted data.
• the individual unit is addressed in a normal fashion with a function bit code designated 11 to indicate that the unit should look for the confirmation of a transmitter intended information change.
• the transmission of a reserved POCSAG code word 1 with the appropriate function bit information to designate the address code word memory region for change will then indicate in which region the information is to be changed. This is then followed by the data which is to replace information in the designated region of the code memory.
• -FIG. 3F shows in particular that function bits 00 in reserve POCSAG code word 1 are used to indicate that no change is to be made while the other combinations of the function bits designate specific regions in the code plug which are to be overwritten with the subsequent data.
• units may be designed with a common address such that addressing an entire group of pagers such as within a designated frame would be enabled by the appropriate function bits and followed by the appropriate reserved POCSAG code word to effect changing the information in code memory of more than one unit at a time.
• additional reserved words may be utilized to address all pagers and the repetition of such additional reserved code words in all frames would enable the entire population in the POCSAG system to be changed simultaneously.
• the number of regions capable of being designated is not limited to three as more than two bits of reserved POCSAG words may be used to designate regions.
• FIGS. 3A-F applies to reprogrammed changes in the code memory 50, as will be shown in greater detail later the inclusion of a different POCSAG reserved code word will allow a reprogramrning of paging system program memory 52 for the same individual unit.
• the same procedure of identifying an individual unit and employing the correct reserved code word will enable the central terminal to control the decoding characteristics of communication received by over-the-air reprogramrning.
• FIG. 4 shows in symbolic form the memory map of reprogrammable non-volatile address code memory 50.
• Code memory 50 is shown to be subdivided into several regions. While only three such regions are shown, it will be appreciated that any number of such regions may be utilized with appropriate coding in the reserved code word to designate them.
• the structure of each region of the the memory is shown to be eight serial locations, each capable of storing one byte of information. This structure is shown for the sake of convenience and it should be clear that any standard architecture of programmable memory would be appropriate to utilize for the present invention.
• Region 1 contains the various binary sequences of the first address code
• region 2 is the second address code
• region 3 contains, again in binary sequence form, information related to the features and options of the paging receiver which are designated by information in the address code memory. It will also be appreciated that the information stored at the sequential locations in the regions can be of longer length than one byte and that this description is only by way of example.
• the microcomputer controller 36 responds to the bit patterns stored in region 3 of the address code memory to activate or de-activate features and options contained in the program memory 46.
• a receiver operating in the POCSAG signalling system may be limited to alerting to only one function by the data stored in the features and options section of the code memory.
• a detailed memory map of the reprogrammable non-volatile reserved word memory, 42, is not shown, it is very similar to the address code memory shown in FIG. 4, and it will be obvious to those skilled in the art how this memory might be subdivided into regions.
• FIG. 5A shows the transmission sequence for two or more batches of information suitable for changing the decoding system used by a designated group or the entire population of POCSAG pagers.
• FIG. 5A shows that all pagers are addressed by the transmission of reserved POCSAG code word number 2 in all time slots, frames 0 through 7, to condition every unit to respond to the change.
• the use of reserved POCSAG code word number 2 in every frame signals the entire population of pagers to effect a change of all POCSAG pagers in one operation. It will also be clear that subsets of the entire population of pagers could be addressed to change their decoding algorithm by transmitting the system change signal in selected frames.
• FIG. 5B shows the general arrangement of the reserved POCSAG code word number 2 utilized to actuate the change in system. It should be noted that reserved POCSAG code word number 2 has a leading bit "0" so that it is to be interpreted as an address code word. This is similar in structure to reserved POCSAG code word number 1 shown in FIG. 3E.
• FIG. 5C now shows how the function bits for reserved word number 2 for changing the signalling code for POCSAG are used in a manner similar to that shown in FIG. 3F for the reserved code word 1 for changing the code memory command.
• FIG. 5C shows the standard POCSAG structure for reserved POCSAG code word number 2 of FIG. 5B but with the indicated function bits being used to direct the data to cause changes in designated regions in the system program memory 46. Specifically, function bits 00, 01, and 10 change designated regions in the program memory.
• portions of the POCSAG algorithms in this case may be modified by selectively reprogramrning various regions, as for example, new alert sequences including unique displays could be established, provisions for decoding multiple addresses could be established for the purpose of creating new groups, new bit rate timing could be established for faster transmission of information, and other similar changes.
• Function bits 11 as shown in FIG. 5C are used to indicate that the entire code signalling system, that is, the entire POCSAG decoding algorithm system, is to be changed.
• FIGS. 5D and 5E show in detailed form the structure of the code words which are transmitted in the frames to achieve changes in the system program memory 46.
• FIG. 5D shows that the first batch as indicated in the frame 0 portion of FIG. 5A includes two repetitions of reserved POCSAG code word number 2.
• both reserve code words have function bits designated as 11 to indicate to all POCSAG pagers, having their addresses in the 0 frame that an entire system change is about to occur. If it is an intention to change the entire population of POCSAG pagers to some modified coding system as shown, FIG. 5D would then include the repetition of two POCSAG reserve code word number 2 in each of the remainder of the frames of the batch. Thus, the entire population is addressed to respond to this change.
• FIG. 5E shows the second batch transmission shown in FIG. 5A in a more detailed form.
• the second sync code designated 66 all of the data necessary to cause the pager to decode a new coding system is transmitted in batch form in the format of POCSAG data words shown and described in FIG. 2C.
• all pagers are prepared to decode the data transmission since each has been appropriately addressed by reserved POCSAG code word number 2 and will continue to stay up and detect information as long as the message data bit is a binary "1" to designate that it is data for an addressed unit.
• FIG. 6 shows in schematic form the architecture or structure of system code memory 46.
• code memory 50 shown in FIG, 4 at least three regions have been designated, although it should be clear to those skilled in the art that more regions could easily be designated.
• Each region shown in FIG. 6 consists of 1,024 sequential bytes of program memory information. The regions are contiguous and continue the sequence of the information so that region 2 begins at the 1,025th byte of program memory and extends to the 2,048th byte. Region 3 similarly begins at the 2,049th byte of program memory and extends to the 3,072nd byte. Again, as a matter of an example, 3,072 bytes of program memory are deemed to be a sufficient allocation of memory locations to enable an entire system program for decoding transmitted information to be stored.
• FIGS. 7A, B, C and D show a binary message paging system developed by Motorola, Inc. and commonly known as the Golay Sequential Code, which normally transmits address information at 300 bits per second and employs two sequential binary words for each pager address.
• the format consists of selective call address signals followed by data or information for the addressed units.
• a word for this system has a (23,12) bit format and is derived from a BCH code.
• FIG. 7A shows a transmission sequence of a start code followed by a sequence of sixteen individual pager addresses which constitute a batch. This sequence is especially important to tone only operation.
• FIG. 7B shows another batch but now an individual address is immediately followed by various data blocks which would be appropriate for numeric or alphanumeric information transmission.
• each paging address in the Golay sequential system consists of two 23 bit binary words separated by a one-half bit interval and preceded by a 14 bit duration of a signal designated as a comma.
• the first and second words are generally designated as Word A and Word B.
• Two 23 bit paging address words which follow each other serially constitute the address code signal of a pager.
• the comma or pause interval of a specified duration is transmitted between each pair of 23 bit word address to form an inter-address gap.
• the code word format of this dual-word addressing system is generated from 12 information bits, and the combination of the information plus parity bits comprises the 23 bit word length.
• parity bits are added to information bits prior to transmission over a channel to allow some errors to occur and yet still ensure that one word will not be mistaken for another word. It is the convention in the G.S.C. system that the logic level of the one-half bit space between sequential address words is always opposite the logic level of the first bit of the second word in the two word address series.
• FIG. 7C also illustrates that the start code signal and the address code signals have the same transmission time as 8 GSC data words with this period being equal to 60.5 bits of the 300 bit per second address signalling rate.
• FIG. 7C further shows the detailed bit format of the data blocks which were shown in FIG. 7B.
• a different word format BCH (15,7) code is used to transmit data in the GSC system.
• FIG. 7D shows that the transmission bit rate is not always the same in the GSC system. While address word sequences are transmitted at a 300 bits/sec. rate, both comma and data blocks are transmitted at 600 bits/sec.
• FIGS. 8A and 8B are descriptive diagrams showing the appropriate coding sequence within the Golay Sequential Code to address a given receiver device for the purpose of changing characteristics stored in its address code memory. These figures may be compared to FIGS. 3A and 3B for the POCSAG code.
• FIG. 8A shows the sequence comprising the unique addressing signal followed by instructions 70 in a data block sequence which will alter the features or options or initiate an address change. This address and data block information would normally be followed by additional addresses which may cause alerting of other pager units or may also be followed by similar signalling sequences to change the characteristics of other receiver units.
• FIG. 8B shows an expanded view of the unique address signal comprising word A and word B that is characteristic of the Golay Sequential Code, and is identical to the address format that was described earlier in FIG. 7C.
• FIG. 8C shows a table listing how the various possible combinations of word A and word B of a unique address signalling code can be used to designate different functions for the Golay Sequential Code.
• word A, word B; word A, inverse word B; and inverse word A, word B which are to be used as normal, distinctive alerting functions.
• the function activated by the detection of inverse word A combined with inverse word B is a reserved address that is used for conditioning the pager for a change in features, options or address.
• FIGS. 8A-8C correspond generally to FIGS. 3A-3C for an individual pager in the POCSAG signalling system.
• a unique change confirmation signal is transmitted immediately after the address signals.
• a reserved pair of Golay words is transmitted to the pager(s) after it has been appropriately conditioned. This provides additional confirmation that a change is being transmitted, and reduces the change that a unit will be erroneously changed by the reception of a noisy signal.
• the transmission by the terminal to an individual pager to change features, options, or address would be initiated by a start code, followed by the appropriate inverse words A and B to address the particular pager and condition it for the change, followed by the GSC reserved words 1 and 2 to confirm that the terminal is to make the change.
• This sequence is then followed by the data for the feature changes which is in the form of data blocks as described earlier.
• FIG. 8E shows the code word sequence used to change the address code memory in greater detail.
• the inverse words A and B which condition the pager are preceded in normal fashion with a comma. This is then followed by comma and the two reserved GSC words to activate the changes in the code memory. Finally, in normal fashion, the information to make the change follows in data block format.
• FIG. 8F shows that by using normal and inverted code word transmissions, the combination of GSC reserved words 1 and 2 can be used to determine which of the several regions in the address code memory will be altered.
• FIG. 8F shows that if reserved word 1 and reserved word 2 are transmitted normally, that is treated as an invalid command and no change is intended to be made.
• Reserved word 1 and inverse reserved word 2 is directed towards a change in region 1; inverse reserved word 1 and reserved word 2 is directed to a change in region 2 and inverse reserved word 1 and inverse reserved word 2 are directed towards region 3.
• FIG. 8F with FIG. 3F for directing changes to the appropriate regions in the address code memory.
• the reserved word sequence indicates the region of the address code memory that is to be changed by the new data. The reader's attention is directed to FIG. 4 where the structure of the code memory was shown and described in detail.
• FIG. 9A shows, in a manner similar to that shown in FIG. 5A for the POCSAG code, how the Golay Sequential code can be used to effect a decoding change in either an individual unit or a suitably grouped number up to all units in the entire population of paging receivers.
• FIG. 9A shows a transmission sequence that begins with a start code and is followed by Golay reserved words 3 and 4, indicating that it is the intention to change all of the Golay sequential units.
• Golay reserved words 3 and 4 are used as a universal address or all call address for the entire population of GSC units.
• Reserved words 3 and 4 are similar in structure to GSC reserved words 1 and 2 used to designate specific regions of the code memory for change. Reserved words 3 and 4 function to activate all units to respond to the following system change information. So that no confusion should arise, reserved words 3 and 4 are merely used to indicate the common address for all units in Golay Sequential Code.
• GSC reserved words 5 and 6 are immediately transmitted to confirm that a correct system change is being initiated.
• the sense of the reserved words 5 and 6, i.e., "normal” or "binary inverse" also indicates which region of program memory is being changed.
• Reserved words 5 and 6 are immediately followed by the new programming information needed to change the operation of the units, which is transmitted in the format of the GSC data blocks described earlier.
• FIG. 9B shows the sequence of FIG. 9A in greater detail.
• GSC reserved words number 3 and number 4 are used as an all unit or entire population group call.
• GSC reserved words 5 and 6 operates in a manner that is similar to reserved word 1 and 2 for the code memory and confirms that a valid change is being transmitted.
• the information necessary to implement the system change is the transmitted ' in the GSC data block format.
• FIG. 9C shows, in a manner similar to FIG. 5C, how the possible sequences of GSC reserved words 5 and 6 are used to access various regions in the system program memory.
• the word 5 and word 6 combination is used to indicate a change in region 1; word 5 and inverse word 6, region 2; inverse word 5 and word 6, region 3; and inverse word 5 and inverse word 6 is the code for activating a total change in the signalling system.
• the regions as indicated in FIG. 9C are the same regions of system program memory 46 as were shown and described in detail for FIG. 6.
• the architecture of the system program memory 46, as described in FIG. 6, is the same and it is only the information which is stored in the program system memory which alters the operation of the pager.
• bit timing is established at block 310, after which the timeout timer is started at block 312 to establish a time period during which the sync word should be detected. During this time period, the system searches for the sync word, block 314. If the time period for locating the sync word expires without the sync word being found, block 316, then the search for bit sync is begun again. However, if the sync word is detected, then the system flow chart, through a continuation block designated A, proceeds to FIG. 10B.
• the timer is set up for address decoding during the appropriate frame at block 320.
• a wait is made for timeout, block 322, after which a search is made for the address at block 324. If an address is not detected, a search is made to detect a reserved word at 325 and the program proceeds through a continuation block designated B. If the reserved word is detected, the program proceeds through continuation block D. If an address other than a reserved word is detected, then the function bits are decoded as per block 326. The function bits are first examined at 328 to determine if they are 11 to indicate conditioning to accept a change in the code memory. If the function bits are identified to be 11, the program proceeds through continuation block designated C.
• the function bits are examined further to determine if a data message function or address was received as shown at block 330. If no data message function is present, then an alert signal is generated at block 332. However, if a message function is present, then the data message is stored in a message memory at block 334, after which an alert signal is generated at block 336. After the a ert signal has been .generated at either 332 or 336, the program proceeds through continuation block B.
• a timer is set up for the next sync word at block 340.
• the system waits for a timer timeout at block 342, and a new search for a sync word is initiated at block 344. If the sync word is detected, then the program proceeds through continuation block A to 320 in FIG. 10B. If the sync word is not detected, a sync word detect flag is read at block 346 to enable a determination to be made whether or not the sync word detect flag is set at decision block 348. If the sync word detect flag is not set, then the flag is set at block 350 and the program returns through continuation block A to set up the timer for address decoding, block 320 in FIG. 10B. If the sync word detect flag was already set, the routine branches to second miss of sync word block 352 and proceeds through a return continuation block ' designated RET which causes the program to return to a search for bit sync 308 in FIG. 10A.
• the next code address is compared to determine if reserve word 1 has been detected at 360. If reserve word 1 has not been detected, then the program returns through continuation block B to set up the timer for the next sync word 340 in FIG. IOC. If reserve word 1 has been detected, its function bits are examined at 362 to determine if they are equal to the 01 bit combination. If the function bits are identified to be 01, then data is stored in the temporary memory at 364. A test is made for the end of data at 366. If the end of data has not been detected, data continues to be stored in temporary memory.
• the process of decoding the new data for region 1 of the code memory begins at 368 followed by writing the new data into region 1 of the code memory at 370. After the new data is written into region 1, the program returns through continuation block B to set up the timer for the next sync word 340 in FIG. IOC.
• the function bits are tested for the 10 combination at block 372. If the function bits do equal the 10 combination, then data is stored in temporary memory at 374 and a test for end of data is performed at 376. If no end of data is detected, information continues to be stored in memory. When the end of data is detected, new data is decoded for region 2 of the code memory at 378, followed by writing the new data into region 2 of the code memory at 380. After the new data is written into region 2, the program then continues through continuation block B to set up the timer for the sync word at block 340 in FIG. IOC.
• the function bits are tested to determine if they equal the 11 combination at 382. If the function bits equal the 11 combination, program initiates storing data in temporary memory at 384, followed by the testing to determine the end of data at 386. If the end of data has not been detected, the program continues to store data in the temporary memory. Upon detection of the end of data, the new data is decoded for region 3 of the code memory at 388 and written into region 3 of the code memory at 390. The program then proceeds through continuation B to setting up the timer for the sync word 340 in FIG. IOC. If the test for function bits equal to the 11 combination shows that they are not detected, then by process of elimination, the function bits must equal the 00 combination and an error has been detected. The program continues to operate with the existing or unmodified address and options remaining in the code plug and returns through continuation point B to set up the timer for the next sync word at block 340 in FIG. IOC.
• the detected code address is compared to determine if reserve word 2 has been detected at 570. If reserve word 2 has not been detected, then the program returns through continuation block RET to search for bit sync at 308 in FIG. 10A. If reserve word 2 has been detected, its function bits are examined at 572 to determine if they are equal to the 00 bit combination. If the function bits are identified to be 00, then data is stored in the temporary memory at 574. A test is made for the end of data at 576. If the end of data has not been detected, data continues to be stored in temporary memory. When the end of data has been detected at 578, the process of decoding the new data for region 1 of the program memory begins at 578 followed by writing the new data into region 1 of the program memory at 580.
• the function bits are tested for the 01 combination at block 582. If the function bits do equal the 01 combination, then data is stored in temporary memory at 584 and a test for end of data is performed at 586. If no end of . data is detected, information continues to be stored in memory. When the end of data is detected, new data is decoded for region 2 of the program memory at 588, followed by writing the new data into region 2 of the program memory at 590.
• the function bits are tested to determine if they equal the 10 combination at 592. If the function bits equal the 10 combination, program initiates storing data in temporary memory at 594, followed by the testing to determine the end of data at 596. If the end of data has not been detected, the program continues to store data in the temporary memory. Upon detection of the end of data, the new data is decoded for region 3 of the program memory at 598 and written into region 3 of the program memory at 600.
• the program initiates storing data in temporary memory at 602, followed by the testing to determine the end of data at 604. If the end of data has not been detected, the program continues to store data in the temporary memory. Upon detection of the end of data, the new data is decoded for the entire program memory at 606 and written into the program memory at 608.
• FIGS. 10A to E show how the present invention operates in the POCSAG coding system.
• the paging device operates like a conventional selective calling receiver in that it can provide all of the features and options associated with the POCSAG code.
• the device can be reprogrammed via POCSAG format signals received over-the-air to modify the features, options and/or address signal(s) assigned to the unit, or to modify the signalling system the unit will decode. That is, the unit can be totally reconfigured by the procedures shown in FIG. 10E to operate in any new coding system, including the Golay Sequential Code.
• the operation of the present invention while in the Golay Sequential Code system can now be described.
• the GSC code format and transmission sequences were described in FIGS.
• system decoding block 34 of the receiver device is best described by means of program flow charts.
• the decoding system is first initialized at 402.
• the code plug memory is read for address information at block 404.
• the timer is set up at block 406, after which the system waits for a time-out at block 408.
• the timer is restarted in block 410 and the address flag is set to address number 1 at block 412.
• word 1 of the current address is loaded as seen at block 414.
• the program searches for word 1 in the received signal at decision block 416.
• word 1 is not detected, then the program proceeds through a continuation block B to FIG. 11B. If word 1 is detected at block 416, then flow continues to decision block 418 where a determination is made whether word 1 or its inverse has been detected. If word 1 is detected, then a detect flag is set for word 1 for the current address at 420. If instead the inverse of word 1 was detected at 418, then a detect flag is set for inverse word 1 for the current address at 422. With the appropriate flag set for the detection of word 1 or its inverse, the program proceeds through continuation block A to FIG. 11B. In FIG. 11B, entry is made through continuation block B to a decision block 424 which determines whether the address word that was searched for was a unique or unit address.
• word 2 has not been detected, the program proceeds to the decision block 424 to test as before whether this is a unique address and proceeds as previously described. If, however, word 2 is detected, then a determination is made at decision block 436 whether word 2 or its inverse has been detected. If word 2 was detected, then a detect flag for word 2 for the current address is set at block 438. If the inverse of word 2 has been detected, then detect flag for the inverse of word 2 for the current address is set at block 440. In either case, after the suitable detect flag has been set, the program proceeds through continuation block E to FIG. lie.
• FIG. 11C entry is made through continuation block E from FIG. 11B to a decision block 450 to determine whether a unique address has been detected. If a unique address has been detected, a determination is made at decision block 452 whether the address sequence is inverse word A, inverse word B. If the decision is yes, the program exits through a continuation block C to FIG. 11D. If the determination is that the received address sequence is not equal to inverse word A, inverse word B, then decision block 454 determines whether a message function has been received. If no message function has been received, an alert signal is generated at block 456 and the program continues through a continuation block labelled RET to the wait for time-out 408 block of FIG. 11A.
• a message function has been received at 454, then the received data message is stored at 458 and, subsequently, an alert signal is generated at 460.
• the program then proceeds through continuation block RET. If at decision block 450 no unique address is detected, then a determination is made at decision block 462 whether a reserved address has been detected. If no such reserve address has been detected, the program continues through continuation block RET. Continuation block labelled RET causes a return to the wait for time-out timer 408 block of FIG. 11A. If, however, a reserved address has been detected, the program continues through continuation block D.
• decision block 470 determines whether reserved address 1 has been detected immediately after unique address sequence inverse word A, inverse word B was received. If reserved address 1 has not been detected, then there is an error and a return to the operation with the existing addresses and options is made through continuation block labelled RET. If, however, reserved address number 1 is detected at 470, a determination is made in decision block 472 whether the address sequence for the reserved address number 1 is A inverse B at block 472. If the A inverse B word sequence has been detected, data is stored in temporary memory at block 474 and a determination is made in decision block 476 when the end of data occurs.
• decision block 670 determines whether reserved address 2 has been detected. It will be recalled that reserved address 2 is formed by reserved code words 3 and 4. If reserved address 2 has not been detected, then there is an error and a return to the operation is made through continuation block labelled RET. If, however, reserved address number 2 is detected at 670, a determination is made in decision block 672 whether the next immediate address sequence is word 5 word 6 at block 672. Word 5 and word 6 will be used to designate GSC reserved words 5 and 6. If the word 5 word 6 sequence has been detected, data is stored in temporary memory at block 674 and a determination is made in decision block 676 when the end of data occurs.
• the word sequence must be inverse word 5 inverse word 6 and the program initiates storing data in temporary memory at 702, followed by the testing to determine the end of data at 704. If the end of data has not been detected, the program continues to store data in the temporary memory. Upon detection of the end of data, the new data is decoded for the entire program memory at 706 and written into the program memory at 708.
• the device acts like a conventional selective calling receiver, and can decode and alert to one or more address signals. In addition, it responds to predetermined reserved signalling patterns by reprogramrning its operating control memories in accordance with instructions received over-the-air via the signalling channel.
• the reprogramrning mechanism can change the address(es) and options of a individual unit a group of units, and can also change the decoding scheme used in any number of units.

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