EP0322915A3 - Circuit tampon d'entrée de signal numérique ayant une construction simple et capable de garder des données - Google Patents
Circuit tampon d'entrée de signal numérique ayant une construction simple et capable de garder des données Download PDFInfo
- Publication number
- EP0322915A3 EP0322915A3 EP19880121853 EP88121853A EP0322915A3 EP 0322915 A3 EP0322915 A3 EP 0322915A3 EP 19880121853 EP19880121853 EP 19880121853 EP 88121853 A EP88121853 A EP 88121853A EP 0322915 A3 EP0322915 A3 EP 0322915A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- node
- buffer circuit
- input buffer
- signal
- digital signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/14—Dummy cell management; Sense reference voltage generators
Landscapes
- Logic Circuits (AREA)
- Static Random-Access Memory (AREA)
- Manipulation Of Pulses (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62332299A JPH01175314A (ja) | 1987-12-29 | 1987-12-29 | 入力インバータ回路 |
JP332299/87 | 1987-12-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0322915A2 EP0322915A2 (fr) | 1989-07-05 |
EP0322915A3 true EP0322915A3 (fr) | 1991-01-02 |
Family
ID=18253409
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19880121853 Withdrawn EP0322915A3 (fr) | 1987-12-29 | 1988-12-29 | Circuit tampon d'entrée de signal numérique ayant une construction simple et capable de garder des données |
Country Status (3)
Country | Link |
---|---|
US (1) | US4943738A (fr) |
EP (1) | EP0322915A3 (fr) |
JP (1) | JPH01175314A (fr) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0758594B2 (ja) * | 1988-12-27 | 1995-06-21 | シャープ株式会社 | ダイナミック型半導体記憶装置 |
JPH07106873A (ja) * | 1993-10-08 | 1995-04-21 | Kanebo Ltd | 電圧モニタ回路 |
JP3625930B2 (ja) * | 1995-10-26 | 2005-03-02 | 株式会社日立製作所 | 半導体集積回路装置 |
US6483386B1 (en) * | 2000-09-29 | 2002-11-19 | Cypress Semiconductor Corp. | Low voltage differential amplifier with high voltage protection |
US6819602B2 (en) * | 2002-05-10 | 2004-11-16 | Samsung Electronics Co., Ltd. | Multimode data buffer and method for controlling propagation delay time |
US7301370B1 (en) * | 2003-05-22 | 2007-11-27 | Cypress Semiconductor Corporation | High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion |
US7737734B1 (en) | 2003-12-19 | 2010-06-15 | Cypress Semiconductor Corporation | Adaptive output driver |
US7956641B1 (en) | 2005-04-28 | 2011-06-07 | Cypress Semiconductor Corporation | Low voltage interface circuit |
EP3217550B1 (fr) | 2016-03-11 | 2024-01-10 | Socionext Inc. | Circuits destinés à être utilisés dans des comparateurs |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4250412A (en) * | 1979-03-05 | 1981-02-10 | Motorola, Inc. | Dynamic output buffer |
EP0049988A2 (fr) * | 1980-10-10 | 1982-04-21 | Inmos Corporation | Transfert de données à grande vitesse pour une mémoire semiconductrice |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4096402A (en) * | 1975-12-29 | 1978-06-20 | Mostek Corporation | MOSFET buffer for TTL logic input and method of operation |
US4441039A (en) * | 1981-11-20 | 1984-04-03 | International Business Machines Corporation | Input buffer circuit for semiconductor memory |
FR2573211B1 (fr) * | 1984-11-09 | 1986-12-12 | Labo Electronique Physique | Comparateur synchronise |
-
1987
- 1987-12-29 JP JP62332299A patent/JPH01175314A/ja active Pending
-
1988
- 1988-12-29 EP EP19880121853 patent/EP0322915A3/fr not_active Withdrawn
- 1988-12-29 US US07/291,886 patent/US4943738A/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4250412A (en) * | 1979-03-05 | 1981-02-10 | Motorola, Inc. | Dynamic output buffer |
EP0049988A2 (fr) * | 1980-10-10 | 1982-04-21 | Inmos Corporation | Transfert de données à grande vitesse pour une mémoire semiconductrice |
Also Published As
Publication number | Publication date |
---|---|
US4943738A (en) | 1990-07-24 |
JPH01175314A (ja) | 1989-07-11 |
EP0322915A2 (fr) | 1989-07-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4028558A (en) | High accuracy MOS comparator | |
US4697112A (en) | Current-mirror type sense amplifier | |
EP0322915A3 (fr) | Circuit tampon d'entrée de signal numérique ayant une construction simple et capable de garder des données | |
US5469097A (en) | Translator circuit with symmetrical switching delays | |
US5896069A (en) | Cross coupled differential oscillator | |
US4606012A (en) | Sense amplifier | |
US5089726A (en) | Fast cycle time clocked amplifier | |
JPH04115622A (ja) | カレントミラー型増幅回路及びその駆動方法 | |
CA1259672A (fr) | Etage d'entree differentiel pour amplificateurs operationnels et recepteurs de ligne differentiels | |
US5550777A (en) | High speed, low power clocking sense amplifier | |
JPH05335917A (ja) | トランスファーゲート及びこれを用いたダイナミック型分周回路 | |
JPH0856142A (ja) | 高速コンパレータ回路 | |
JPH0513360B2 (fr) | ||
EP0242721A3 (fr) | Circuit générateur de signaux du type "boot-strap" | |
JP2695410B2 (ja) | 半導体集積回路装置 | |
JP3019437B2 (ja) | インバータ回路 | |
JP3326804B2 (ja) | コンパレータ回路 | |
JPH0347012B2 (fr) | ||
JPH0666656B2 (ja) | シユミツトトリガ回路 | |
JP2965581B2 (ja) | カウンタ用電流切換型回路 | |
JPH07109980B2 (ja) | 半導体集積回路 | |
KR950003281B1 (ko) | 교차 결합 증폭기 | |
KR0154747B1 (ko) | 저전력 레벨 컨버터 | |
JPH07262785A (ja) | センス回路 | |
EP0093482A1 (fr) | Dispositifs de mémoire semi-conductrice |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19881229 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): DE FR GB |
|
17Q | First examination report despatched |
Effective date: 19920811 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN |
|
18W | Application withdrawn |
Withdrawal date: 19931103 |