EP0308987A2 - Anzeigegerät - Google Patents

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Publication number
EP0308987A2
EP0308987A2 EP88115825A EP88115825A EP0308987A2 EP 0308987 A2 EP0308987 A2 EP 0308987A2 EP 88115825 A EP88115825 A EP 88115825A EP 88115825 A EP88115825 A EP 88115825A EP 0308987 A2 EP0308987 A2 EP 0308987A2
Authority
EP
European Patent Office
Prior art keywords
scanning
data
electrodes
signal
electrode drive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP88115825A
Other languages
English (en)
French (fr)
Other versions
EP0308987A3 (de
Inventor
Hideo Kanno
Hiroshi Inoue
Atsushi Mizutome
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of EP0308987A2 publication Critical patent/EP0308987A2/de
Publication of EP0308987A3 publication Critical patent/EP0308987A3/de
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen

Definitions

  • the present invention relates to a display apparatus, more particularly a display apparatus comprising a ferroelectric liquid crystal panel.
  • a liquid crystal display apparatus comprising scanning electrodes and data electrodes arranged to form a matrix and a liquid crystal disposed between the scanning electrodes and data electrodes to form a large number of pixels for image display
  • a driving method wherein a scanning signal is sequentially applied to the scanning electrodes and image signals are applied to the data electrodes in synchronism with the scanning signal.
  • a scanning selection signal defining at least two phases is serially applied to the scanning electrodes so as to apply a voltage to a pixel on a selected scanning electrode for providing a white (or black) state at the pixel in one phase and apply a voltage to a pixel on the selected scanning electrode for providing a black (or white) state at the pixel in another phase, and one frame or field of picture is formed by one vertical scanning.
  • a driving system is disclosed in U.S. Patent No. 4,655,561.
  • a scanning electrode drive circuit and a data electrode drive circuit of a nematic liquid crystal panel have been controlled by control signals including a vertical synchronizing signal VD, a horizontal synchronizing signal HD, and image or data signals as shown in Figure 4.
  • the vertical scanning signal VD is a signal for defining one frame scan (corresponding to one frame period) with a scanning selection signal and is periodically outputted.
  • the horizontal scanning signal HD is a signal for defining a period for one selection of a scanning electrode during which image signals corresponding to the number of data electrodes are serially transferred to the data electrode drive circuit.
  • a vertical synchronizing pulse VD when a vertical synchronizing pulse VD is applied, a first scanning electrode of the panel or screen is selected, and the scanning is started from the first scanning electrode and sequentially continued to the lowest scanning electrode, while horizontal synchronizing pulses HD are applied.
  • the scanning image data are transferred to the data electrode drive circuit so as to output one set of data signals in one selection period for a scanning electrode. The above operation is repeated 30 times per second (30 frames/sec; frame frequency: 1/30 sec) or more.
  • the frequencies of the VD, HD and image data signals are naturally increased correspondingly.
  • the 1H period required becomes about 80 ⁇ sec.
  • a ferroelectric liquid crystal is considered as a liquid crystal material for such a display panel
  • the resultant frame frequency becomes lower than 30 frames per sec and provides a scanning state which is noticeable to human eyes and is problematic in display.
  • the scanning electrodes are sequentially scanned and all the data electrodes are always supplied with data signals in synchronism with the scanning signal, so that a large power consumption is required.
  • U.S. Patent No. 4,655,561 further discloses a partial rewriting mode wherein a prescribed part of a picture is rewritten by driving only the scanning electrodes in the rewriting region.
  • the scanning electrodes subjected to partial rewriting must be controlled by a scanning start signal and a scanning finish signal, so that the circuit designing becomes complicated.
  • An object of the present invention is to provide a display apparatus which has solved the above-­mentioned problems of the conventional system and is capable of providing an apparently faster response and a lower power consumption of a display panel of a large area and a large number of pixels.
  • Another object of the present invention is to provide a display apparatus which allows for partial rewriting by using a mouse display, a cursor display and a multi-window display.
  • a display apparatus comprising:
  • Figure 1 illustrates an outline of a display apparatus including a display panel 1 and peripheral circuits used in the present invention.
  • the display panel 1 comprises data electrodes DL (e.g., 640 lines), scanning electrodes SL (e.g., 400 lines) and a ferroelectric liquid crystal hermetically disposed therebetween.
  • the data electrodes DL are supplied with data signals from a data electrode drive circuit 2
  • the scanning electrodes SL are supplied with data signals from a scanning electrode drive circuit 3.
  • the data electrode drive circuit 2 includes a shift register 4 receiving one line of image signal data shown in Figure 2 serially supplied to be displayed on the display panel 1; a line memory 5 receiving in parallel and memorizing the serial data for one line sent to the shift register 4; and a data signal supply circuit 6 for supplying data signals to the respective data electrodes DL according to the data for one line memorized in the line memory 5.
  • the scanning electrode drive circuit 3 includes an address data latch 7 for latching an address signal for designating one of the scanning electrodes SL; an address decoder 8 for selecting one of the scanning electrodes SL according to the address signal latched by the address data latch 7; and a scanning signal supply circuit 9 for supplying a scanning selection signal to one scanning electrode SL selected by the address decoder 8.
  • the display apparatus further includes an image memory VRAM 13 for memorizing image data for each of the bits corresponding to the pixels formed at the intersection of the data electrodes DL and the scanning electrodes SL on the display panel 1; a changeover directing signal line 10 for supplying a horizontal synchronizing signal; an address data line 11 for transferring output signals (VRAM output signals shown in Figure 2) from the image memory (VRAM) 13 to the display panel 1; a changeover switch 12 for determining either the shift register 4 or the address data latch 7 to which the VRAM output signals from the address data line 11 are to be sent depending on the signal (horizontal synchronizing signal) from the changeover directing signal line 10.
  • VRAM 13 for memorizing image data for each of the bits corresponding to the pixels formed at the intersection of the data electrodes DL and the scanning electrodes SL on the display panel 1
  • a changeover directing signal line 10 for supplying a horizontal synchronizing signal
  • an address data line 11 for transferring output signals (VRAM output signals shown in Figure 2) from the image memory (VRAM
  • the VRAM output signals include an address signal A for addressing a scanning electrode to which a scanning selection signal is to be sent, and image signals B for designating data signals to be supplied to the data electrodes for the respective data electrodes.
  • the address signal A is transferred to the address data latch 7, and the image signals B are set to the shift register 4.
  • the display apparatus further includes a CPU 14 by which the outputs from the image memory 13 are controlled. Particularly when partial rewriting data are generated in the image memory 14, the CPU 14 reads out the order of scanning electrodes to be addressed from the partial rewriting data corresponding to the rewriting liens and supplies the address signal A thereto.
  • Figure 2 is a time chart showing a directing signal 10S appearing on the changeover directing signal line 10 and VRAM output signals 11S appearing on the address data line 11.
  • the VRAM output signal 11S comprises an address signal A for designating one of the scanning electrodes SL.
  • the address data line 11 serially transfers VRAM output signals 11S which are image signals B serially outputted in the image signal scanning period, i.e., data signals each corresponding to one of the data electrodes DL.
  • a period called "dead time C" is placed, which is a very short time allotted as a process time for an external transfer apparatus.
  • the switch 12 When the directing signal 10S is at the high level, the switch 12 turns the address data line 11 over to the address data latch 7 side. As a result, the address signal A in the VRAM output signals 11S is latched by the address data latch 7, and a scanning selection signal is supplied to one of the scanning electrodes SL through the address decoder 8 and the scanning signal supply circuit 9.
  • the switch 12 turns the address data line 11 over to the shift register 4 side.
  • the image signals in the VRAM output signals 11S are supplied to the shift register 4 and sent through the line memory 5 to the data signal supply circuit 6, from which a white data signal and a black data signal are supplied to the respective data electrodes DL selectively depending on given data.
  • an address signal A sent to the scanning electrode drive circuit 3 and serial image signals B sent to the data electrode drive circuit 2 may be supplied to one address data line 11, so that the address signal A for addressing a selected scanning electrode is conveyed first, and subsequently thereafter the image signals B corresponding to the selected scanning electrode may be sent to the data electrodes.
  • a similar control may be repeated for the subsequent second, third, ..., scanning electrodes, whereby one picture may be formed.
  • the above-mentioned address signal A may be controlled by the CPU so that the address signal A is supplied to only scanning electrodes in the partially rewritten region. Further, such a partial rewriting scheme by applying a scanning selection signal only to a selected scanning electrode may also be applicable to a cursor display or mouse display on a display picture.
  • the directing signal 10S is synchronized with the horizontal synchronizing signal HD, and the high level of 10S is allotted to the horizontal fly-back time and the low level thereof is allotted to the image signal scanning period, with respect to time.
  • the image data 1, 2, 3, 4, ..., 640 serially supplied in one horizontal scanning period correspond to image data of data signals sent to the first, second, third, fourth, ..., 640-th data electrodes, respectively.
  • a liquid crystal material and a liquid crystal cell are required to have a memory characteristic.
  • the memory characteristic of a ferroelectric liquid crystal is supplemented.
  • a ferroelectric liquid crystal is disposed between upper and lower electrode plates 31 and 32, and is supplied with an electric field exceeding a certain threshold, a liquid crystal molecule thereof is oriented to a first stable state which is retained even after the removal of the electric field E.
  • a reverse electric field -E is applied, the liquid crystal molecule is oriented to a second stable state 34 which is also retained even after the removal of the electric field -E.
  • the respective orientation states are retained unless the electric field E or -E applied thereto does not exceed such a certain threshold value.
  • the orientation of a ferroelectric liquid crystal at an intersection of a data electrode DL and a scanning electrode SL can be changed by an electric field given by voltage applied to the data electrode and the scanning electrode and the resultant orientation is maintained even after removal of the voltages.
  • the present invention for effecting such a partial writing (rewriting) operation, it is possible to provide an apparently faster response speed to a ferroelectric liquid crystal panel of a large area and a large number of pixels using a ferroelectric liquid crystal which does not satisfy a desired response speed. Further, by partial writing (or rewriting) operation, the number of scanning electrodes to be scanned can be minimized, and the operation can be effected instantaneously, so that the power consumption can also be minimized. Further, according to the present invention, the use of a conventionally used vertical synchronizing signal can be omitted.
  • a display apparatus includes: a) a matrix electrode structure comprising a set of plural scanning electrodes and a set of plural data electrodes intersecting with the scanning electrodes; b) scanning electrode drive means for serially applying a scanning selection signal to the scanning electrodes and data electrode drive means for applying data signals in parallel; c) means for serially generating an address signal for addressing a scanning electrode to which the scanning selection signal is to be applied and image signals for directing data signals to be sent to the data electrodes to the respective data electrodes; and d) means for generating a signal for directing a changeover between a transfer of the address signal to the scanning electrode drive means and a transfer of the image signals to the data electrode drive means.
  • the display apparatus is particularly adapted for partial rewriting.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP88115825A 1987-09-25 1988-09-26 Anzeigegerät Withdrawn EP0308987A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP23892487A JPH06105390B2 (ja) 1987-09-25 1987-09-25 液晶装置の信号転送方式
JP238924/87 1987-09-25

Publications (2)

Publication Number Publication Date
EP0308987A2 true EP0308987A2 (de) 1989-03-29
EP0308987A3 EP0308987A3 (de) 1990-01-17

Family

ID=17037298

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88115825A Withdrawn EP0308987A3 (de) 1987-09-25 1988-09-26 Anzeigegerät

Country Status (2)

Country Link
EP (1) EP0308987A3 (de)
JP (1) JPH06105390B2 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0416172A2 (de) * 1989-09-08 1991-03-13 Canon Kabushiki Kaisha Datenverarbeitungssystem mit Anzeigetafel
US5353041A (en) * 1989-08-31 1994-10-04 Canon Kabushiki Kaisha Driving device and display system
US5359344A (en) * 1988-09-29 1994-10-25 Canon Kabushiki Kaisha Data processing system and apparatus
US6731264B2 (en) 1994-09-30 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Driver circuit for display device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4655561A (en) * 1983-04-19 1987-04-07 Canon Kabushiki Kaisha Method of driving optical modulation device using ferroelectric liquid crystal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4655561A (en) * 1983-04-19 1987-04-07 Canon Kabushiki Kaisha Method of driving optical modulation device using ferroelectric liquid crystal

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5657042A (en) * 1988-09-29 1997-08-12 Canon Kabushiki Kaisha Data processing system and apparatus capable of inhibiting the storage of image data during partial rewriting
US5646646A (en) * 1988-09-29 1997-07-08 Canon Kabushiki Kaisha Data processing system and apparatus processing scroll display data and cursor display data
US5818410A (en) * 1988-09-29 1998-10-06 Canon Kabushiki Kaisha Data processing system and apparatus having first and second graphic event data
US5784043A (en) * 1988-09-29 1998-07-21 Canon Kabushiki Kaisha Data processing system and apparatus with prioritized processing of first graphic event data and second graphic event data
US5359344A (en) * 1988-09-29 1994-10-25 Canon Kabushiki Kaisha Data processing system and apparatus
US5543817A (en) * 1988-09-29 1996-08-06 Canon Kabushiki Kaisha Data processing system and apparatus
US5677706A (en) * 1988-09-29 1997-10-14 Canon Kabushiki Kaisha Data processing system and apparatus
EP0706167A3 (de) * 1988-09-29 1996-11-20 Canon Kk Teil-Überschreibsystem in einer Anzeigeeinrichtung mit Speicherfunktion
US5574476A (en) * 1988-09-29 1996-11-12 Canon Kabushiki Kaisha Data processing system and apparatus with graphic event priority levels for storage and retrieval of different graphic event data
US5353041A (en) * 1989-08-31 1994-10-04 Canon Kabushiki Kaisha Driving device and display system
EP0416172A2 (de) * 1989-09-08 1991-03-13 Canon Kabushiki Kaisha Datenverarbeitungssystem mit Anzeigetafel
EP0416172A3 (en) * 1989-09-08 1992-03-11 Canon Kabushiki Kaisha Information processing system and apparatus
US5321811A (en) * 1989-09-08 1994-06-14 Canon Kabushiki Kaisha Information processing system and apparatus
US6731264B2 (en) 1994-09-30 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Driver circuit for display device
US7432905B2 (en) 1994-09-30 2008-10-07 Semiconductor Energy Laboratory Co., Ltd. Driver circuit for display device

Also Published As

Publication number Publication date
JPS6481995A (en) 1989-03-28
JPH06105390B2 (ja) 1994-12-21
EP0308987A3 (de) 1990-01-17

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