EP0256360B1 - Steuerbare Tunneldiode - Google Patents

Steuerbare Tunneldiode Download PDF

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Publication number
EP0256360B1
EP0256360B1 EP87110764A EP87110764A EP0256360B1 EP 0256360 B1 EP0256360 B1 EP 0256360B1 EP 87110764 A EP87110764 A EP 87110764A EP 87110764 A EP87110764 A EP 87110764A EP 0256360 B1 EP0256360 B1 EP 0256360B1
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Prior art keywords
semiconductor layer
layer
semiconductor
forming
material composed
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EP87110764A
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English (en)
French (fr)
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EP0256360A3 (en
EP0256360A2 (de
Inventor
Takao Hitachi Koganei-Ryo Kuroda
Akiyoshi Hitachi Shobu-Ryo Watanabe
Takao Miyazaki
Hiroyoshi Matsumura
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures

Definitions

  • the present invention relates to an ultrahigh speed transistor which utilizes tunneling. More particularly, it relates to a three-terminal tunnel FET in which a tunneling current is induced by applying an external gate field to a semiconductor layer held in a double heterojunction.
  • FR-A-1 533 811 discloses a three-terminal device of the FET type in which the electrical isolation between an input and an output is favorable, while the high speed of the tunneling is exploited.
  • Fig. 6(c) is a conceptual diagram of the current - voltage characteristic of the tunnel diode, in which V p and I p denote the values of a voltage and a current that produce the peak current with a forward bias, and V v and I v denote the values of a voltage and a current that produce a valley current, respectively.
  • the figure of merit of the tunnel diode in the application to microwaves etc. is expressed by I p /C j where C j indicates a junction capacitance. Decrease in C j necessitates to make the area of the junction as small as several ⁇ m2 or below. Assuming I p ⁇ 5 mA, however, a certain degree of junction area is required in order to avoid an excessively high current density.
  • a tunnel effect semiconductor device comprising a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, having free electrons and holes therein, said third semiconductor layer being disposed between, and having a narrower band gap than, the first and second semiconductor layers, so that the resulting band discontinuities form at a first boundary between the third semiconductor layer and the first semiconductor layer a first barrier to said holes in the valence band, and form at a second boundary between the third semiconductor layer and the second semiconductor layer a second barrier to said electrons in the conduction band, said holes and electrons forming respectively a two-dimensional hole gas at said first boundary and a two-dimensional electron gas at said second boundary and being separated by a distance small enough for enabling tunneling of carriers, a first contact region contacting said electrons, a second contact region contacting said holes, first and second electrodes formed on said first and second contact regions respectively, and a gate electrode controlling the internal electric field of the third semiconductor layer thereby controlling the tunneling of carriers which are permitted to flow between said boundaries.
  • said third semiconductor layer comprises a p+ -layer and a n+ -layer forming a p+/n+ junction therebetween, said junction producing the internal electric field of the third semiconductor layer.
  • said first semiconductor layer is doped with p-type impurities
  • said second semiconductor layer is doped with n-type impurities
  • said third semiconductor layer is undoped, said impurities producing the internal electric field of the third semiconductor layer.
  • FIG. 1(a) shows the structure of an FET which exploits the tunnel effect.
  • This transistor basically has such a structure that, on a semi-insulating substrate crystal 1, a very thin layer having a p+/n+ homo-junction (2, 3) which has a band gap smaller than that of the substrate and whose whole thickness is equal to the width of a depletion layer or so is formed, and that it is held in a double heterojunction defined by the substrate crystal 1 and a cap layer 4 which has a band gap greater than that of this layer having the p+/n+ junction (2, 3).
  • the p+-layer 2 and n+-layer 3 are respectively formed with contact regions 6 and 5 by diffusion, ion implantation or the like, and a drain electrode 9 and a source electrode 8 are formed on the respective contact regions.
  • a gate electrode 7 is formed on the cap layer 4.
  • Numerals 12 and 13 in the figure indicate a source - drain bias (V sd ) and a gate bias (V g ), respectively.
  • a two-dimensional electron gas layer 10 or 14 and a two-dimensional hole gas layer 11 or 15 are induced at the heterojunction boundaries of the double heterojunction structure, and the charges of these layers balance with the total quantities of the charges of ionized donors 16 and ionized acceptors 17 within the depletion layer of the p+/n+ junction, whereby an electrical neutral condition is held.
  • the two-dimensional electron gas 10 or 14 and the two-dimensional hole gas 11 or 15 join with the source electrode 8 in Fig. 1(a) and with the drain electrode 9 under very low series resistances, respectively.
  • the source - drain bias V sd and the gate bias V g are respectively applied to the source electrode 8 and the gate electrode 7 with reference to the drain electrode 9 as illustrated in Fig. 1(a).
  • Fig. 2(a) illustrates a situation in which a reverse tunneling current flows under a reverse bias
  • FIG. 2(b) illustrates a situation in which a forward tunneling current flows.
  • the reverse bias when the gate voltage is enlarged, the current increases monotonically, but with a forward bias, when the gate voltage is enlarged, decrease in the tunneling current occurs on the basis of the same principle as in the Esaki diode.
  • Such currents I sd do not depend very intensely upon the source - drain voltages V sd .
  • the speed at which the tunneling arises is on the order of picoseconds, so that a switching time of about 100 picoseconds can be achieved by optimizing the capacity and current value of the device.
  • leakage currents can develop through the p-n junctions between the n+-layer 3 and p+-contact layer 4 and between the p+-layer 2 and the n+-contact layer 5.
  • the influences of the leakage currents are negligibly small.
  • the width of the depletion layer is approximately 10 nm, and the internal electric field is approximately 1 x 106 V/cm. Accordingly, the sum of the thicknesses of the p+-layer and the n+-layer may be 10 to 15 nm.
  • the peak current density J p corresponding to the peak current I p of the tunnel diode stated before is approximately 102 A/cm2.
  • Fig. 7 shows another embodiment of the present invention. This embodiment is an improvement on the embodiment of Fig. 1(a). Although the leakage current between the source and drain is negligible in the embodiment of Fig. 1(a), it is more reduced to enhance characteristics in the present embodiment.
  • a buffer layer 71 is formed on a substrate crystal 82, and that a layer having a p+/n+ homo-junction (72, 73) which has a band gap smaller than that of the buffer layer 71 and which has a total thickness nearly equal to the width of a depletion layer is so formed as to be held in a double heterojunction defined by the buffer layer 71 and a cap layer 74 which has a band gap greater than that of the layer having the p+/n+ junction (72, 73).
  • an ion-implanted layer (n++) 75 is formed on the side of a source electrode 78 by, for example, the ion implantation of Si so shallowly that the n+/p+ boundary is not reached, while the cap layer 74 and the n+-layer 73 on the side of a drain electrode 79 are etched and removed down to the n+/p+ boundary by dry etching, and a p++-layer 76 is formed in the corresponding part of the p+-layer 72 by the diffusion of Zn or the ion implantation of Be.
  • ohmic electrodes are respectively formed on the n++-layer 75, p++-layer 76 and cap layer 74 as the source electrode 78, the drain electrode 79 and a gate electrode 77 by evaporation.
  • the leakage current elucidated in Figs. 1(a) and 1(b) is almost null, and hence, a semiconductor device of still better characteristics can be realized.
  • the first semiconductor layer defined in the present invention is the buffer layer 71 formed on the crystal substrate 82.
  • Such a construction may of course be employed.
  • GaAs substrate it is possible to use Ga 1-x Al x As for the buffer layer, a GaAs-based material for the third semiconductor layer, and Ga 1-u Al u As ( u ⁇ 0.3) for the second semiconductor layer.
  • InP substrate it is possible to use InP, InAlAs or InGaAsP for the buffer layer, InGaAs or InGaAsP for the third semiconductor layer, and InAlAs, InGaAsP or InGaAlAs for the second semiconductor layer.
  • a semi-insulating material is suitable as the substrate 82.
  • FIG. 3 shows another example of a crystal structure which the semiconductor device according to the present invention possesses.
  • a substrate 31 was semi-insulating GaAs, on which a p+/n+ junction layer made up of p+-Ge (p ⁇ 1 x 1018 - 1019 cm ⁇ 3, thickness ⁇ 10 nm) 32 and n+-Ge (n ⁇ 1 x 1018 - 1019 cm ⁇ 3, thickness ⁇ 10 nm) 33, and a hetero-cap layer 34 (undoped GaAs or Al x Ga 1-x As ( x ⁇ 0.5 - 0.7), thickness: 50 to 200 nm) were grown by molecular-beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD).
  • MBE molecular-beam epitaxy
  • MOCVD metal-organic chemical vapor deposition
  • Fig. 4 shows still another example.
  • a substrate 41 was semi-insulating InP
  • a layer 42 was made of p+-In 0.53 Ga 0.47 As
  • a layer 43 was made of n+-In 0.53 Ga 0.47 As (the total thickness of the layers 42 and 43 was approximately 10 nm)
  • a hetero-cap layer 44 was made of undoped InP or In 0.52 Al 0.48 As (50 to 200 nm thick).
  • a contact for the n+-layer was formed in such a way that a contact layer having an impurity concentration of or above 2 x 1018 cm ⁇ 3 was formed by a method of ion-implanting and then annealing Si, whereupon AnGe, Ni and An were evaporated and then alloyed as an ohmic electrode.
  • the alloy layer was so deep as to penetrate the cap layer and to extend down to a level within the n+-layer.
  • a contact for the p+-layer was formed in such a way that a contact layer was formed by diffusing Zn or ion-implating Be deep enough to reach the p+-layer, whereupon Cr-Au was or Ti, Pt and An were evaporated as an ohmic electrode.
  • the parts of the layers other than device portions were mesa-etched and removed down to the substrate. Al/Ti, or the like was used as a gate metal.
  • a structure shown in Fig. 5(a) in which the barrier layer of a heterojunction was doped as in a HEMT, thereby to form a two-dimensional electron gas layer 60 and a two-dimensional hole gas layer 61 on both the sides of an undoped layer 53, and the tunneling between the layers 60 and 61 was controlled by a gate electrode 57. Since, in this case, the layer 53 was of high resistivity, the isolation between a source and a drain under the null gate voltage was improved. However, ohmic contacts for the two-dimensional electron and hole gas layers were more difficult than in the case of Fig. 1(a), and the parasitic resistance of an FET became high.
  • a semi-insulating InP substrate 51 there were grown a p+-In 0.52 Al 0.48 As layer 52 (1 x 1018 - 1019 cm ⁇ 3, 50 to 200 nm thick), the undoped In 0.53 Ga 0.47 As layer 53 (about 20 nm thick), and an n+-In 0.52 Al 0.48 As layer 54 (1 x 1018 - 1019 cm ⁇ 3, 50 to 200 nm thick).
  • a p+-In 0.52 Al 0.48 As layer 52 (1 x 1018 - 1019 cm ⁇ 3, 50 to 200 nm thick
  • the undoped In 0.53 Ga 0.47 As layer 53 about 20 nm thick
  • an n+-In 0.52 Al 0.48 As layer 54 (1 x 1018 - 1019 cm ⁇ 3, 50 to 200 nm thick.
  • numerals 55 and 56 designate n-type and p-type contact layers, numerals 58 and 59 source and drain electrodes, and numerals 62 and 63 ionized donors and acceptors, respectively.
  • numeral 64 indicates the two-dimensional electron gas layer, numeral 65 the two-dimensional hole gas layer, numeral 66 the ionized donors, and numeral 67 the ionized acceptors.
  • the hetero-cap layer epitaxially grown on the p+/n+ junction layer was used.
  • FET's in each of which the hetero-cap layer was replaced with an insulator gate such as of SiO2 or SiN x were fabricated for trial, and similar high-speed switching characteristics were attained.
  • the FET in Fig. 1(a) had a very low series resistance, so that the thermal noise was of low level, and characteristics favorable for a high-frequency and low-noise transistor could be achieved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
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  • Junction Field-Effect Transistors (AREA)

Claims (6)

  1. Tunneleffekt-Halbleiterbauelement mit:
    - einer ersten Halbleiterschicht (1; 31; 41; 52; 71);
    - einer zweiten Halbleiterschicht (4; 34; 44; 54; 74);
    - einer dritten Halbleiterschicht (2, 3; 32, 33; 42, 43; 53; 72, 73) mit freien Elektronen und Löchern in ihr, welche dritte Halbleiterschicht zwischen der ersten und der zweiten Halbleiterschicht angeordnet ist und eine schmalere Bandlücke aufweist, so daß die sich ergebenden Bandunstetigkeiten an einer ersten Grenze zwischen der dritten Halbleiterschicht und der ersten Halbleiterschicht eine erste Sperre gegen die Löcher (11; 15; 61; 65; 81) im Valenzband bilden, und an einer zweiten Grenze zwischen der dritten Halbleiterschicht und der zweiten Halbleiterschicht eine zweite Sperre gegen die Elektronen (11; 14; 60; 64; 80) im Leitungsband bilden, wobei die Löcher und Elektronen jeweils ein zweidimensionales Löchergas an der ersten Grenze bzw. ein zweidimensionales Elektronengas an der zweiten Grenze bilden und sie durch einen Abstand voneinander getrennt sind, der ausreichend klein dafür ist, das Tunneln von Ladungsträgern zu ermöglichen;
    - einem ersten Kontaktbereich (5, 55, 75), der die Elektronen kontaktiert;
    - einem zweiten Kontaktbereich (6, 56, 76), der die Löcher kontaktiert;
    - einer ersten und einer zweiten Elektrode (8, 9; 58, 59; 78, 79), die auf dem ersten bzw. dem zweiten Kontaktbereich ausgebildet ist; und
    - einer Gateelektrode (7; 57; 77), die das elektrische Innenfeld in der dritten Halbleiterschicht steuert, um dadurch den Tunnelvorgang von Ladungsträgern zu steuern, die zwischen den Grenzen fließen dürfen.
  2. Halbleiterbauelement nach Anspruch 1, bei dem die dritte Halbleiterschicht eine p⁺-Schicht (2, 32, 42, 72) und eine n⁺-Schicht (3, 33, 43, 73) aufweist, die zwischen sich einen p⁺n⁺-Übergang bilden, welcher Übergang das elektrische Innenfeld in der dritten Halbleiterschicht erzeugt.
  3. Halbleiterbauelement nach Anspruch 1, bei dem die erste Halbleiterschicht (52) mit p-Fremdstoffen und die zweite Halbleiterschicht (54) mit n-Fremdstoffen dotiert ist und die dritte Halbleiterschicht (53) undotiert ist, wobei die Fremdstoffe das elektrische Innenfeld der dritten Halbleiterschicht erzeugen.
  4. Halbleiterbauelement nach Anspruch 1, bei dem die erste Halbleiterschicht (31) aus einem Halbleitermaterial aus GaAs besteht, die zweite Halbleiterschicht (34) aus einem Halbleitermaterial aus AlxGa1-xAs besteht, und die dritte Halbleiterschicht (32, 33) aus einem Halbleitermaterial aus Ge besteht.
  5. Halbleiterbauelement nach Anspruch 1, bei dem die erste Halbleiterschicht (41) aus einem Halbleitermaterial aus InP besteht, die zweite Halbleiterschicht (44) aus einem Halbleitermaterial aus In0,52Al0,48As besteht, und die dritte Halbleiterschicht (42, 43) aus einem Halbleitermaterial aus In0,53Ga0,47As besteht.
  6. Verfahren zum Herstellen des Tunneleffekt-Halbleiterbauelements nach Anspruch 1, mit den folgenden Schritten:
    - Ausbilden der dritten Halbleiterschicht (2, 3; 53; 72, 73) auf der ersten Halbleiterschicht (1; 52; 71) und der zweiten Halbleiterschicht (4; 54; 74) auf der dritten Halbleiterschicht;
    - Ausbilden der ersten und zweiten Kontaktbereiche (5, 6; 55, 56; 75, 76) durch Diffusion oder Ionenimplantation mindestens in die dritte Halbleiterschicht (2, 3; 53; 72, 73) hinein, wobei ein erster Kontaktbereich (5; 55; 75) von einem ersten Leitungstyp und ein Zweiter Kontaktbereich (6; 56; 76) von einem zweiten Leitungstyp gebildet werden;
    - Ausbilden der ersten und der zweiten Elektroden (8, 9; 58, 59; 78, 79) auf dem ersten bzw. zweiten Kontaktbereich (5, 6; 55, 56; 75, 76); und
    - Ausbilden der Gateelektrode (7; 57; 77) auf der zweiten Halbleiterschicht (4; 54; 74).
EP87110764A 1986-07-25 1987-07-24 Steuerbare Tunneldiode Expired - Lifetime EP0256360B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP61173649A JPH0783108B2 (ja) 1986-07-25 1986-07-25 半導体装置
JP173649/86 1986-07-25

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EP0256360A2 EP0256360A2 (de) 1988-02-24
EP0256360A3 EP0256360A3 (en) 1990-02-07
EP0256360B1 true EP0256360B1 (de) 1993-11-24

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EP87110764A Expired - Lifetime EP0256360B1 (de) 1986-07-25 1987-07-24 Steuerbare Tunneldiode

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US (1) US4835581A (de)
EP (1) EP0256360B1 (de)
JP (1) JPH0783108B2 (de)
CA (1) CA1265626A (de)
DE (1) DE3788253T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2619250B1 (fr) * 1987-08-05 1990-05-11 Thomson Hybrides Microondes Transistor hyperfrequence a double heterojonction
US5172194A (en) * 1987-09-16 1992-12-15 National Science Council Structures of modulation doped base hot electron transistors
US6253307B1 (en) 1989-05-04 2001-06-26 Texas Instruments Incorporated Data processing device with mask and status bits for selecting a set of status conditions
US5142349A (en) * 1991-07-01 1992-08-25 Motorola, Inc. Self-doped high performance complementary heterojunction field effect transistor
US5313117A (en) * 1991-07-22 1994-05-17 Nippon Telegraph And Telephone Corporation Semiconductor logic circuit using two n-type negative resistance devices
JP2773474B2 (ja) * 1991-08-06 1998-07-09 日本電気株式会社 半導体装置
US5401980A (en) * 1991-09-04 1995-03-28 International Business Machines Corporation 2D/1D junction device as a Coulomb blockade gate
DE69202554T2 (de) * 1991-12-25 1995-10-19 Nec Corp Tunneltransistor und dessen Herstellungsverfahren.
DE4238545A1 (de) * 1992-11-14 1994-05-19 Daimler Benz Ag Drucksensor und ein Verfahren zu dessen Herstellung
JP3141080B2 (ja) * 1994-06-22 2001-03-05 ケイディディ株式会社 半導体機能素子
JPH10190003A (ja) * 1996-12-27 1998-07-21 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US6617643B1 (en) 2002-06-28 2003-09-09 Mcnc Low power tunneling metal-oxide-semiconductor (MOS) device
AU2003266701A1 (en) * 2002-10-09 2004-05-04 Matsushita Electric Industrial Co., Ltd. Plasma oscillation switching device
US7026642B2 (en) * 2003-08-27 2006-04-11 Micron Technology, Inc. Vertical tunneling transistor
JP4840056B2 (ja) * 2006-09-29 2011-12-21 Ｔｏｔｏ株式会社 水栓及びその取付方法
US7839209B2 (en) * 2006-10-05 2010-11-23 Nxp B.V. Tunnel field effect transistor
US8436422B2 (en) 2010-03-08 2013-05-07 Sematech, Inc. Tunneling field-effect transistor with direct tunneling for enhanced tunneling current
US8421165B2 (en) 2010-05-11 2013-04-16 Sematech, Inc. Apparatus, system, and method for tunneling MOSFETs using self-aligned heterostructure source and isolated drain
GB2482308A (en) 2010-07-28 2012-02-01 Univ Sheffield Super junction silicon devices
US8586993B2 (en) 2012-02-28 2013-11-19 Infineon Technologies Austria Ag Normally-off compound semiconductor tunnel transistor
US20140090684A1 (en) * 2012-09-24 2014-04-03 Joshua R. Smith Heterojunction electrode with two-dimensional electron gas and surface treatment
TWI555209B (zh) * 2013-07-29 2016-10-21 高效電源轉換公司 具有降低的輸出電容之氮化鎵裝置及其製法
KR101515071B1 (ko) * 2013-11-29 2015-04-24 가천대학교 산학협력단 실리콘 집적가능한 게르마늄 기반의 높은 정공이동도를 갖는 트랜지스터
US9768311B2 (en) 2014-07-24 2017-09-19 Ecole Polytechnique Federale De Lausanne (Epfl) Semiconductor tunneling device
CN104241375B (zh) * 2014-08-29 2017-03-22 北京大学 一种跨骑型异质结共振隧穿场效应晶体管及其制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3462700A (en) * 1966-08-10 1969-08-19 Bell Telephone Labor Inc Semiconductor amplifier using field effect modulation of tunneling
DE2913068A1 (de) * 1979-04-02 1980-10-23 Max Planck Gesellschaft Heterostruktur-halbleiterkoerper und verwendung hierfuer
CA1179071A (en) * 1981-06-17 1984-12-04 Tadashi Fukuzawa Semiconductor device
US4538165A (en) * 1982-03-08 1985-08-27 International Business Machines Corporation FET With heterojunction induced channel
JPS59111371A (ja) * 1982-12-16 1984-06-27 Nippon Telegr & Teleph Corp <Ntt> 電界効果トランジスタ
JPH0654784B2 (ja) * 1984-06-11 1994-07-20 沖電気工業株式会社 半導体装置
JPS60263471A (ja) * 1984-06-11 1985-12-26 Oki Electric Ind Co Ltd 半導体装置
JPS6112081A (ja) * 1984-06-27 1986-01-20 Hitachi Ltd 半導体装置
US4686550A (en) * 1984-12-04 1987-08-11 American Telephone And Telegraph Company, At&T Bell Laboratories Heterojunction semiconductor devices having a doping interface dipole
JPS61147577A (ja) * 1984-12-21 1986-07-05 Toshiba Corp 相補型半導体装置
JPS61174776A (ja) * 1985-01-30 1986-08-06 Sony Corp ヘテロ接合電界効果トランジスタ
CA1256590A (en) * 1985-03-15 1989-06-27 Yuichi Matsui Compound semiconductor device with layers having different lattice constants

Also Published As

Publication number Publication date
CA1265626A (en) 1990-02-06
DE3788253T2 (de) 1994-03-17
EP0256360A3 (en) 1990-02-07
DE3788253D1 (de) 1994-01-05
JPH0783108B2 (ja) 1995-09-06
JPS6331173A (ja) 1988-02-09
EP0256360A2 (de) 1988-02-24
US4835581A (en) 1989-05-30

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