Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
  • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
  • G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Definitions

• the invention relates to a page mode write system for an E 2 PROM memory.
• E 2 PROMs are integrated circuits and are typically manufactured in NMOS technology. Most of the active devices of an E 2 PROM are NMOS transistors formed by heavily doped N-type (N+) source and drain regions separated by a lightly doped P-type (P-) region, all in a semiconductor substrate. The P- region forms the channel between the N+ regions. The conductivity between the N+ regions through the channel is controlled by electrical signals on a gate electrode positioned in close proximity over, but isolated from, the channel.
• N+ N-type
• P- lightly doped P-type
• E 2 PROMs are organized in a rectangular array of memory cells formed in a semiconductor substrate with each cell in the array storing a single bit of information.
• the cells are addressed by their row and column locations in the array.
• Each cell includes a word select transistor, having a control gate coupled to a word line, and a stacked gate transistor, having a program gate coupled to a program gate line (PGL).
• PGL program gate line
• Independent, user-generated voltage signals clocked onto the word line and PGL control the word select and stacked gate transistors, respectively.
• the stacked gate transistor includes a floating polysilicon gate positioned below the program gate. If the signal on the PGL is clocked high, then the stacked gate transistor will conduct when the floating gate is discharged of negative charge and will not conduct when the floating gate is charged negatively.
• the word select and stacked gate transistors of the cell are connected to form a series circuit between a bit line and a bit line ground.
• a central N+ region of the cell forms the drain of the word select transistor and the source of the stacked gate transistor
• a given cell in the array is read by the following procedure. First the bit line connected to the cell is biased positively while the word and program gate lines intersecting the cell are biased to predetermined voltages.
• a current sensing amplifier provides a digital output corresponding to the flow of current from the bit line through the cell to a bit line ground coupled to ground. Current will flow if the floating gate is discharged, which is the logic 0 state and will not flow if the cell is charged, which is the logic 1 state.
• the floating gate in the cell is charged by electrons tunneling through a tunneling structure which includes a thin tunneling oxide layer positioned between a region of the floating gate and a central N+ region.
• the tunneling structure functions as a capacitor having capacitance C t . A high voltage drop across the tunneling capacitor will cause electrons to tunnel through the tunneling oxide layer.
• the floating gate is not directly connected to any external voltage supply.
• the voltage drop across the tunneling structure is induced by applying a voltage difference between the program gate and the central N+ region.
• a coupling structure includes the program gate, a floating gate, and a thin oxide layer separating the two gates.
• the coupling structure functions as a capacitor having capacitance C p .
• C p capacitance
• a byte consists of eight bits horizontally disposed on adjacent bit lines and accessed by a single word line, correspondingly; a page generally consists of a set of bytes horizontally disposed and accessed by a single word line.
• E 2 PROM memory cells including a page mode write cycle. The page mode write greatly increases the speed of writing new data into the E 2 PROM memory array.
• a typical 64K E 2 PROM array is organized into 256 or 512 pages with either thirty-two or sixteen bytes per page.
• the page mode circuitry includes a page buffer memory consisting of sixteen or thirty-two bytes external to the E 2 PROM memory array and interposed between the write circuitry of the exter- nal system and the E 2 PROM array.
• the user writes data into the external page mode buffer during a page load cycle of the page mode write cycle.
• the data stored in the external buffer is written into the selected page of the E 2 PROM memory array by charging and discharging the floating gate of the memory cells in the array, as described above .
• E 2 PROM memory arrays A severe limitation to existing E 2 PROM memory arrays relates to the number of times that the floating gates in the cells may be charged and discharged. Each charge and discharge operation is termed a cycle, and most E 2 PROM arrays have increased failure rates after a given number of cycles have been completed. Often, several bytes in a page will contain data that does not need to be updated, but will neverthe less go through a charge and discharge cycle during a page mode write that does not change the data in the byte. Accordingly, a page mode write system that does not induce a charge/discharge cycle in a byte not being updated would greatly increase the lifetime of the E 2 PROM array.
• E 2 PROM memory arrays First, the need for an external page mode buffer is eliminated. Secondly, the flexibility of the write mode is greatly increased due to the freedom of the system from any external clocking scheme.
• the latches of the present system are continually active and able to receive new data at the user's behest. Additionally, the duration of the load cycle is user-controlled and may be extended to any desired time period. Further, the present invention facilitates writing data into a given set of bytes in the page while preventing bytes not in the page from undergoing a charge/discharge cycle. Other advantages of the invention will be apparent in view of the following description and appended claims.
• Each bit line forms an active node of a bit line latch for storing data during the load cycle.
• each byte incl-udes a program gate (PG) line that is latched to a selected state to control whether its associated byte will have data written into it during the page mode write cycle.
• PG program gate
• the latching of the input data into the array during the load cycle is made possible due to a unique system wherein an independent bit line ground (BLG) is associated with each bit line.
• BLG bit line ground
• each page includes thirty-two bytes disposed along a horizontal word line with the array including 256 word lines and pages.
• Each byte includes eight bit lines, eight independent bit line grounds, a PG line, a bit line latch associated with each bit line and a PG latch associated with the PG line, and circuitry for accessing the various bytes in the page and for controlling the voltage on the bit lines and PG lines.
• Each byte in the page has a unique Y address (Y 0 , Y 1 , ... Y 31 ) where Y n is accessed through a standard Y decoder circuit.
• the PG and bit line latches are three transistor latches that actively couple the PG line and bit lines, respectively, to ground.
• the PG line and bit lines are connected to pumps which pull up the PG and bit lines respectively to selected voltages when the lines are not actively coupled to ground by the latches.
• the load cycle terminates a fixed time interval after a word enable signal is clocked high. If the user wishes to remain in the page load cycle it may toggle, i.e., continually clock between its high and low-states, to prevent the predetermined time interval from elapsing. Thus, the duration of the page load cycle is controlled by the user. Additionally, the PG and BL latches are active latches that are independent of any external clock. Thus, the latches will accept new data whenever it is entered by the user independent of any external clocking scheme. Accordingly, the present system allows great user flexibility in. changing or updating the data loaded during the page mode load cycle.
• the write cycle begins wherein the data latched onto the bit lines in selected bytes is programmed into the
• the write cycle is divided into two sub-cycles, a charge subcycle and a discharge subcycle.
• the PG lines latched to a high voltage state will be pulled to about 20 volts. However, those PG lines latched low will remain at low voltage.
• the present invention is a page mode write system for an E 2 PROM memory array that obviates the need for an external page buffer, increases page mode write flexibility, and increases the endurance of the E 2 PROM array.
• Fig. 1 is a schematic diagram of a typical
• FIG. 2 is a block diagram of the present invention.
• Fig. 3 is a schematic diagram of a byte in the present invention.
• Fig. 4 is a timing diagram depicting the state of the control signals utilized in the present invention
• Fig. 5 is a schematic diagram of a voltage pump circuit suitable for use in the present system.
• the present invention is a system for implementing a page mode write into an E 2 PROM memory array.
• Fig. 1 is a circuit diagram of an E 2 PROM memor cell 8.
• a word select NMOS transistor 10 includes a source 12 coupled to a bit line (BL) 14, a P- channel 16, a drain formed by a central N+ region or terminal 18, and a control gate 20.
• a stacked gate transistor 22 includes a source being the central terminal 18, a P- channel 24, a drain 26 coupled to a bit line ground (BLG) 28, a floating gate (FG) 30, and a program gate (PG) 32.
• the word select transistor 10 and stacked gate transistor 22 form a series circuit between the BL 14 and BLG 28.
• the control gate 20 is coupled to a word line (WL) 36 and PG 32 is coupled to PG line (PGL) 38.
• a tunneling structure 34 includes a thin tunnelling dielectric region that allows electrons to tunnel between the central terminal 18 and the FG 30 under appropriate voltage bias conditions.
• Table 1 is a state table setting forth the voltage states for the word, PG, bit, and bit ground lines during the discharge, charge, and read operations.
• both the word line 36 and BL 14 are set at about 20 volts.
• the high voltage on the word line minimizes the resistance of the P- channel 16 of the word select transistor 10 and assures that the central terminal 18 raise to about 20 volts.
• the BLG 38 is open so that the bit ground N+ terminal 26 is floating with respect to the voltage supply, thereby allowing no current to flow through the BLG 28.
• the central terminal 18 may thus be fully raised to the about 20-volt level to discharge the floating gate 30.
• the program gate 32 disposed over the floating polysilicon gate 30 is biased at zero volts.
• the BL 14 is grounded at zero volts and the WL 36 is again charged to twenty volts to reduce the resistance of the first channel region 16 and assure that the central terminal 18 is grounded.
• the PGL 30 is biased to twenty volts, thereby biasing the floating gate 30 to a high voltage (approximately +15 volts) due to the capacitive coupling between the PG 32 and the floating polysilicon gate 30. Electrons tunnel from the central terminal 18 through the tunneling region 34 into the polysilicon gate 30.
• the WL 36 is biased to +5 volts and the BLG 28 is grounded.
• the WL 36 is biased so that the word select transistor 10 is on and conducts while the PGL 30 is biased so that the stacked gate transistor 22 conducts if the floating polysilicon gate 30 is discharged and does not conduct if the floating polysilicon gate 30 is charged.
• current will flow from the BL 12 to the BLG 28 if the polysilicon gate 30 is discharged (logic 0 state) and will not flow if the polysilicon gate 30 is charged (logic 1 state).
• the cell 8 is first programmed so that the floating polysilicon gate 30 is charged and the cell is in a logic 1 state. If a logic 1 is to be stored in the cell, the floating polysilicon gate 30 is then programmed so that the floating polysilicon gate 30 is discharged.
• the cell 8 is formed by diffusing the bit line, central terminal, and bit ground N+ regions 12,
• oxide layer is then deposited over the surface of the P- substrate and the N+ regions. This oxide layer includes a thin dielectric tunneling region formed by methods well-known in the art.
• the polysilicon WL and PGL lines 36, 38, metal BL and BLG 14, 28 and insulating oxide layers are also formed by standard methods well known in the art.
• Fig. 2 is a schematic diagram depicting the overall architectural layout of the present invention.
• thirty-two bytes 40 each containing eight bits, are disposed along a selected WL 36.
• Each byte is coupled to, a data bus 42 comprising eight data lines 44 by applying a voltage signal to a Y n terminal 46 where Y n couples the nth byte to the data bus 42.
• the array will include two hundred and fifty-six WLs 36 so that there will be two hundred and fifty-six pages in the E 2 PROM array.
• Any page in the array is selected by providing the appropriate WL address (usually denoted the X address) while any particular byte in a page is selected by providing the array with a Y address which selects the appropriate Y n terminal 46.
• Each byte has associated with it a set of byte latches 48 which are active latches having the respective bit lines 14 in the byte 40 coupled to a node in the latch 48.
• Each byte includes a PG line 38 coupled to a V PG line 50 included in the data bus 42.
• the Y n terminal 46 also controls the coupling of each PGL 38 to the V PG line 50.
• Fig. 3 is a detailed schematic diagram of the nth bite of the mth page of the E 2 PROM array.
• the mth page is disposed along WL 36 and the nth byte is accessed by terminal Y 46.
• the byte includes eight E 2 PROM memory cells 8, each connected between a respective vertical BL 14 and a vertical BLG 28.
• the byte also includes a PG line 38 oriented parallel to the BLs 14.
• Each BL 14 includes a first terminal 14A connected to a terminal of a bit line access transistor (T DL ) 60 with the second terminal of the bit line access transistor connected to a data line 44 in the data bus
• the gates of all the T DL s 60 in the byte are connected to the Y n terminal 46.
• a second terminal of the bit line 14B is connected to an I/O port of a bit line pump 62.
• the bit line pump 62 has a second input connected to a V PP2 terminal 64.
• the second terminal 14B of each bit line 14 is also connected to a bit line discharge transistor (T BLD ) 66 with a second terminal of T BLD 66 connected to ground.
• the gates of the T BLD s 66 in the byte are connected to a PL line 68.
• the PG line 38 has a first terminal 38A connected to a first terminal of a PGL access transistor (T VPG ) 70 with the second terminal of T VPG 70 connected to the V PG line 50 and with the gate of the T VPG 70 connected to the Y n terminal 46.
• a second terminal 38B of PGL 38 is connected to the I/O port of a PG pump 72.
• a second port of the PG pump 72 is connected to a Y PP1 terminal 74.
• a first node 76 of the PG line is connected to a first terminal of a PG discharge transistor (T PGD )
• T PGD 78 with the second terminal of T PGD 78 connected to ground and the gate of T PGD 78 connected to a PLPG line
• a second node 82 on PGL 38 is connected to the first terminal of a program transistor 84 having its second terminal connected to the program gates 32 of the E 2 PROM memory cells 8 in the byte and having its gate connected to the word line 36.
• the BLGs 28 have a first terminal 28A connecte to a terminal of a bit line ground transistor (T BLG ) 86 with the second terminal of T BLG 86 connected to ground and with the gate of T BLG 86 connected to an SA line 88.
• Each bit line latch 48 has a first terminal
• the bit line latch 48 includes first, second, and third transistors (T 1 , T 2 , and T 3 ) 91, 92, and 93 where T 1 is an NMOS depletion mode transistor and T 2 and T 3 are NMOS enhancement mode transistors.
• T 1 is connected between the input terminal 48A and a node A 94 with the gate of T 1 connected to node A so that T 1 functions as a depletion load transistor.
• T 2 is connected between Node A 94 and ground with the gate of T 2 connected to node B 95 of the latch 48.
• the BL 14 is also connected to node B 95 of the latch 48.
• T 3 is connected between the bit line 14 and ground with the gate of T 3 connected to node A 94.
• the PGL latch 96 is structurally identical to the bit line latch 48 with the substitution of the PGL 38 for the BL 14.
• the data to be loaded into the byte is clocked onto the data lines as a series of voltage states on the data lines 44 in the data bus 42. Since there are only eight data lines 44 only eight bits of information may be loaded during a single cycle.
• a particular byte in the page is selected by providing a set of Y address bits to the Y decoder to activate the Y n terminal 46. If an entire page is to be written in one write cycle, thirty-two byte load cycles must be completed before the page write operation is implemented. As described above, the user may extend the load cycle indefinitely by toggling the signal to prevent the preset time interval from timing out.
• the page mode write operation is divided into a load cycle and a write cycle.
• the write cycle is further divided into a charge subcycle and a discharge subcycle.
• the following steps are followed to load eight bits of data into the nth byte of the mth page.
• the BLs 14 and PGL 38 of the byte are grounded so that PGL 38 in all the BLs 14 are pulled low.
• the data is clocked onto the data bus 42 and the V PG line is clocked high while the Y n terminal is also clocked high to activate the access transistors 60 and 70.
• PGL 38 is coupled to the V PG line 50 and the BLs 14 are coupled to respective data lines 44 in the data bus 42.
• the BL latches 48 and PGL latch 96 are powered up by BLL 90 to actively latch the BLs 14 to the data states on the corresponding data lines 44 and the PGL to the state of the V PG line 50.
• active latch refers to a latch that couples a low BL 14 to ground independently of any external clocking system. Y n terminal is then clocked low to decouple PGL 38 and the BLs 14 from the data bus 42.
• the PGL 38 and BLs 14 in the nth byte will remain latched at these data values until the write cycle is begun. If the data in the nth byte is to be changed the above-described steps are repeated so that the new data is latched into the byte.
• the load operation does not affect the data stored in the memory cells 8 since the voltages on the BLs 14 and program gates 32 are not of sufficient magnitude to charge or discharge the floating gates 30 of the memory cells 8.
• the charge subcycle begins a fixed time period after the last leading rising edge of the signal. If the PGL 38 is latched high, then it is pulled to about 20 volts to pull all the program gates 32 of the memory cells in the byte to about 20 volts.
• the word line 36 is also pulled to about 20 volts to couple the central terminal 18 of each memory cell to its corresponding BL 14.
• Those memory cells coupled to low BLs 14 will have their floating gates fully charged due to the about 20 volt difference between the central terminal 18 and the program gate 32.
• Those memory cells coupled to high BLs 14 will have their floating gates 30 only partially charged since the voltage differential between the program gate 32 and the central terminal 18 is less than about 20 volts. Accordingly, at the end of the charge cycle all the floating gates 30 in the byte are either fully or partially charged.
• the discharge subcycle begins after the charge cycle has been completed.
• the PG line 38 and, correspondingly, all the program gates 32 are pulled low.
• the high BLs 14 are then pulled to about 20 volts while the low BLs 14 remain low. Accordingly, an about 20 volt differential between the program gates and high
• BLs 14 is developed that discharges the floating gates 30 of the memory cells 8 coupled to the high BLs 14.
• no voltage drop is developed between the program gate 32 and central terminal 18 of the memor cells 8 connected to low BLs 14 and thus the floating gates 30 of those memory cells remain charged.
• the present invention allows data to be written into a given set of bytes in the page while preventing those bytes not in the given set from undergoing a charge/discharge cycle.
• the size of the given set may range from a single byte to the full 32 bytes.
• Fig. 4 is a timing diagram depicting the states on the various control lines at different times during the load and write cycle.
• the load cycle is initiated, with CE low by pulling WE low.
• Y DIS goes high to deactivate the access transistors 60 and 70 and the one shot PGL and PL clocks go high to activate T pGD 78 and T BLD 66, thereby pulling PGL 38 and BLs 14 low.
• V PG 50 is clocked high and the data to be loaded is clocked onto data lines 44.
• Y DIS then goes low and Y n 46 is pulled high to activate access transistors 60 and 70.
• BLL 90 is clocked high to power up the latches 48 and 96.
• BL latch 48 When BLL 90 is high, current flows through T, and charges node A 94. If BL 0 14 is low, then node B 95 is low and transistor T 2 is off. Accordingly, node A is charged positively and T 3 is activated, thus coupling BL 0 14 to ground. Thus, a low BL 0 14 is latched to ground by the BL latch 48.
• BL 0 14 is high, node B 95 is high and transistor T 2 is activated, thereby discharging node A and deactivating T 3 . Accordingly, BL 0 14 is isolated from ground and the action of the BL pump 62 connected to V PP2 terminal 64 maintains the BL 0 14 at five volts. It is important to note that the BL latch 48 is active, i.e., it will latch the BL 14 to a new state independent of any external clocking.
• node B would turn on T 2 thereby discharging node A and in turn deactivating T 3 to isolat BL 0 14 from ground and latch BL 0 14 to five volts via the BL pump 62.
• the data in a byte may be changed during the load cycle at any time selected by the user and thus the load cycle provides for flexible data chang ing.
• the SA line 88 is pulled low to deactivate the BL ground transistors 86 and decouple the BLGs 28 from ground.
• all the BLGs 28 in the byte are electrically independent during the load cycle. This independence facilitates the latching of the load data onto the BLs 14 for the reasons set forth below.
• the BLGs 28 in the byte are coupled together. This coupling results in a lack of independence between the various E 2 PROM cells.
• V PPl is pulled to twenty volts.
• the PG pump is designed so that if PGL 38 is high, then the PG pump will pump PGL 38 to about 20 volts. However, if PGL 38 is low, then PGL will remain low. Turning now to the case where PGL is high, the twenty volts on PGL 38 is coupled to the program gates 32 of all the memory cells 8 in the byte. Additionally, the word line 36 is pulled high to couple the central terminal of the cell to the respective BLs 14. As described above, the floating gates 30 in memory cells 8 connected to low BLs 14 will be fully charged while the floating gates 30 in memory cells 8 connected to high BLs 14 will be partially charged.
• V PP1 goes back to 5 volts and PLPG 80 is clocked high to pull PGL 38 low.
• all the floating gates in the memory cells of the byte are either charged or partially charged, depending on whether their associated BLs 14 were low or high.
• V PP2 is pulled to about 20 volts and the BLs 14 latched high are pumped to about 20 volts by the BL pump 62. Those BLs 14 latched low will remain low during the discharge cycle.
• the word line 36 is pulled to about 20 volts to couple the central terminal 18 of the memory cells 8 to the BLs 14 so that the central terminal 18 of the high BLs 14 is pulled to about 20 volts and the central terminal 18 coupled to the BLs 14 remains low.
• the program gates 32 are grounded via the PGL 38 and thus a 20 volt difference is developed between the program gate and central terminal 18 for those cells connected to BLs 14 latched high.
• a BL pump 62 is depicted, however, it is to be understood that the functioning of the PG pump 72 is identical.
• the I/O port of the BL pump 62 is connected to the second terminal 14B of the BL 14.
• a second terminal of the pump 62 is connected to V PP2 64.
• the pump circuit includes first and second transistors (Q 1 and Q 2 ) 100 and 102 and a capacitor C 1 104.
• a BL pump input is connected to a clock input 106.
• the terminals of transistor Q 1 100 connect the
• V PP2 terminal 64 to a charging node 108. If the voltage at the BL 14 terminal is latched low, then transistor Q 1 100 is inactivated and the charging node 108 is isolated from the V PP2 terminal 64. Accordingly, BLs 14 latched low deactivate the BL pump 62 and remain grounded when
• V PP2 is pulled to about 20 volts.
• the BL pump 62 may be replaced by other active pull-up means such as a resistor coupled to the V PP2 terminal 64 by a transistor activated by clocking the BL high.
• the above description is presented by way of example, not limitation.
• changes in the voltage states, timing, circuitry of the latches, and physical layout of the array described above could be made by persons of ordinary skill in the art within the scope of the invention.
• the latches, pump circuitry, and other circuitry peripheral to the underlying E 2 PROM memory cell array has been described as NMOS circuitry. It is known in the art to design equivalent circuitry in PMOS, CMOS, bipolar, and other circuitry technologies. Such substitution is included within the scope of the present invention which is defined by the appended claims.

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• 1986
  • 1986-01-30 EP EP19860901245 patent/EP0211069A4/de active Pending
  • 1986-01-30 WO PCT/US1986/000222 patent/WO1986004727A1/en not_active Application Discontinuation
  • 1986-01-30 JP JP50109686A patent/JPS62501736A/ja active Pending

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