WO1986004727A1

WO1986004727A1 - Efficient page mode write circuitry for e2proms

Info

Publication number: WO1986004727A1
Application number: PCT/US1986/000222
Authority: WO
Inventors: Michael S. Briner; Colin S. Bill; Paul Suciu; Darrell Rinerson
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1985-02-11
Filing date: 1986-01-30
Publication date: 1986-08-14
Also published as: EP0211069A4; JPS62501736A; EP0211069A1

Abstract

A page mode write system for an E2PROM array including active latches (48) for storing loaded data on bit lines (14), independent bit line grounds (28) for isolating the cells (8) in a byte (40), and program gate lines (38) in each byte (40) for tagging those bytes (40) that will undergo a charge/discharge cycle during the write cycle.

Description

EFFICIENT PAGE MODE WRITE CIRCUITRY FOR E²PROMS

BACKGROUND OF THE INVENTION The invention relates to a page mode write system for an E²PROM memory.

E²PROMs are integrated circuits and are typically manufactured in NMOS technology. Most of the active devices of an E²PROM are NMOS transistors formed by heavily doped N-type (N+) source and drain regions separated by a lightly doped P-type (P-) region, all in a semiconductor substrate. The P- region forms the channel between the N+ regions. The conductivity between the N+ regions through the channel is controlled by electrical signals on a gate electrode positioned in close proximity over, but isolated from, the channel.

E²PROMs are organized in a rectangular array of memory cells formed in a semiconductor substrate with each cell in the array storing a single bit of information. The cells are addressed by their row and column locations in the array. Each cell includes a word select transistor, having a control gate coupled to a word line, and a stacked gate transistor, having a program gate coupled to a program gate line (PGL). Independent, user-generated voltage signals clocked onto the word line and PGL control the word select and stacked gate transistors, respectively. The stacked gate transistor includes a floating polysilicon gate positioned below the program gate. If the signal on the PGL is clocked high, then the stacked gate transistor will conduct when the floating gate is discharged of negative charge and will not conduct when the floating gate is charged negatively.

The word select and stacked gate transistors of the cell are connected to form a series circuit between a bit line and a bit line ground. A central N+ region of the cell forms the drain of the word select transistor and the source of the stacked gate transistor A given cell in the array is read by the following procedure. First the bit line connected to the cell is biased positively while the word and program gate lines intersecting the cell are biased to predetermined voltages. A current sensing amplifier provides a digital output corresponding to the flow of current from the bit line through the cell to a bit line ground coupled to ground. Current will flow if the floating gate is discharged, which is the logic 0 state and will not flow if the cell is charged, which is the logic 1 state. The floating gate in the cell is charged by electrons tunneling through a tunneling structure which includes a thin tunneling oxide layer positioned between a region of the floating gate and a central N+ region. The tunneling structure functions as a capacitor having capacitance C_t. A high voltage drop across the tunneling capacitor will cause electrons to tunnel through the tunneling oxide layer.

The floating gate is not directly connected to any external voltage supply. The voltage drop across the tunneling structure is induced by applying a voltage difference between the program gate and the central N+ region. A coupling structure includes the program gate, a floating gate, and a thin oxide layer separating the two gates. The coupling structure functions as a capacitor having capacitance C_p . When a preselected voltage is applied to the coupling electrode, a fraction of the voltage drop, between the coupling electrode and the drain is capacitively coupled to the tunneling structure The basic unit of information in the E²PROM memory array is the bit, however, information may be retrieved either by the byte or the page. Generally, a byte consists of eight bits horizontally disposed on adjacent bit lines and accessed by a single word line, correspondingly; a page generally consists of a set of bytes horizontally disposed and accessed by a single word line. Recently, manufacturers have announced the introduction of E²PROM memory cells including a page mode write cycle. The page mode write greatly increases the speed of writing new data into the E²PROM memory array.

A typical 64K E²PROM array is organized into 256 or 512 pages with either thirty-two or sixteen bytes per page. In existing systems the page mode circuitry includes a page buffer memory consisting of sixteen or thirty-two bytes external to the E²PROM memory array and interposed between the write circuitry of the exter- nal system and the E²PROM array. The user writes data into the external page mode buffer during a page load cycle of the page mode write cycle. Upon completion of the page load cycle the data stored in the external buffer is written into the selected page of the E²PROM memory array by charging and discharging the floating gate of the memory cells in the array, as described above .

Several disadvantages accrue from the external page buffer required in existing systems. First, additional circuitry is required to implement the buffer and results in redundancy between the circuitry and the E²PROM array and the page buffer. Secondly, the latches in the external page buffer are generally independently clocked and function to sample incoming data at predetermined points in an external clocking cycle.

The user of the system may only update the data at times specified by this external clocking system and thus existing page mode write systems are inherently inflexible. Additionally, many existing page mode write systems write new data into every byte in the page during a write cycle. A severe limitation to existing E²PROM memory arrays relates to the number of times that the floating gates in the cells may be charged and discharged. Each charge and discharge operation is termed a cycle, and most E²PROM arrays have increased failure rates after a given number of cycles have been completed. Often, several bytes in a page will contain data that does not need to be updated, but will neverthe less go through a charge and discharge cycle during a page mode write that does not change the data in the byte. Accordingly, a page mode write system that does not induce a charge/discharge cycle in a byte not being updated would greatly increase the lifetime of the E²PROM array.

Objects Of The Invention It is an object of the invention to eliminate the need for an external buffer in an E²PROM array.

It is a further object of the invention to facilitate writing data into a given set of bytes in the page while preventing the bytes not in the given set from undergoing a charge/discharge cycle.

It is a still further object of the invention to increase the flexibility of the page mode write operation.

SUMMARY OF THE INVENTION The above and other objects are achieved by the present invention which solves many of the problems associated with existing page mode write systems for

E²PROM memory arrays. First, the need for an external page mode buffer is eliminated. Secondly, the flexibility of the write mode is greatly increased due to the freedom of the system from any external clocking scheme. The latches of the present system are continually active and able to receive new data at the user's behest. Additionally, the duration of the load cycle is user-controlled and may be extended to any desired time period. Further, the present invention facilitates writing data into a given set of bytes in the page while preventing bytes not in the page from undergoing a charge/discharge cycle. Other advantages of the invention will be apparent in view of the following description and appended claims.

The latches for temporary storage of the incoming data during the page mode load operation are implemented within the memory array itself. Each bit line forms an active node of a bit line latch for storing data during the load cycle. Additionally, each byte incl-udes a program gate (PG) line that is latched to a selected state to control whether its associated byte will have data written into it during the page mode write cycle. At the start of the load cycle, each byte in the page is cleared by pulling the PG line and bit lines to a low voltage state. Data is latched into the byte by clocking the PG line high and clocking the BLs high or low depending on the data state.

The latching of the input data into the array during the load cycle is made possible due to a unique system wherein an independent bit line ground (BLG) is associated with each bit line. These independent BLGs isolate the memory cells in the byte and prevent any coupling between the bit lines in the byte during the load cycle.

In a preferred embodiment, each page includes thirty-two bytes disposed along a horizontal word line with the array including 256 word lines and pages. Each byte includes eight bit lines, eight independent bit line grounds, a PG line, a bit line latch associated with each bit line and a PG latch associated with the PG line, and circuitry for accessing the various bytes in the page and for controlling the voltage on the bit lines and PG lines. Each byte in the page has a unique Y address (Y₀, Y₁ , ... Y₃₁) where Y_n is accessed through a standard Y decoder circuit.

According to one aspect of the invention, the PG and bit line latches are three transistor latches that actively couple the PG line and bit lines, respectively, to ground. The PG line and bit lines are connected to pumps which pull up the PG and bit lines respectively to selected voltages when the lines are not actively coupled to ground by the latches.

The load cycle terminates a fixed time interval after a word enable

signal is clocked high. If the user wishes to remain in the page load cycle it may toggle, i.e., continually clock

between its high and low-states, to prevent the predetermined time interval from elapsing. Thus, the duration of the page load cycle is controlled by the user. Additionally, the PG and BL latches are active latches that are independent of any external clock. Thus, the latches will accept new data whenever it is entered by the user independent of any external clocking scheme. Accordingly, the present system allows great user flexibility in. changing or updating the data loaded during the page mode load cycle.

Once the preset time interval has elapsed, the write cycle begins wherein the data latched onto the bit lines in selected bytes is programmed into the

E²PROM cells. The write cycle is divided into two sub-cycles, a charge subcycle and a discharge subcycle.

During the charge cycle, the PG lines latched to a high voltage state will be pulled to about 20 volts. However, those PG lines latched low will remain at low voltage.

Turning now to a byte having a PG line latched high, all the PGs in the byte are coupled to the PG line and are pulled to about 20 volts. Accordingly, the memory cells connected to a bit line latched low will be fully charged due to the voltage drop between the program gate and the bit line of the cell. Those memory cells connected to bit lines latched high will be only partially charged because the voltage difference is slightly lower than for those cells having the bit line latched low. During the discharge subcycle, the PG line is clocked low and the bit lines latched high are pulled to about 20 volts. However, the bit lines latched low remain grounded. The memory cells connected to the bit lines latched high will have their floating gates discharged while the memory cells connected to the bit lines latched low will remain charged. Thus, the data latched onto the bit lines is written into the E²PROM cells.

Only those bytes having the PG line clocked high and data latched onto the bit lines undergo a charge/discharge cycle during the write operation. Accordingly, data may be written into a given set of bytes in the page and the bytes not in the given set are prevented from undergoing a charge discharge cycle.

Thus, the present invention is a page mode write system for an E²PROM memory array that obviates the need for an external page buffer, increases page mode write flexibility, and increases the endurance of the E²PROM array.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a schematic diagram of a typical

E²PROM memory cell. Fig. 2 is a block diagram of the present invention.

Fig. 3 is a schematic diagram of a byte in the present invention.

Fig. 4 is a timing diagram depicting the state of the control signals utilized in the present invention

Fig. 5 is a schematic diagram of a voltage pump circuit suitable for use in the present system.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention is a system for implementing a page mode write into an E²PROM memory array.

Fig. 1 is a circuit diagram of an E²PROM memor cell 8. In Fig. 1, a word select NMOS transistor 10 includes a source 12 coupled to a bit line (BL) 14, a P- channel 16, a drain formed by a central N+ region or terminal 18, and a control gate 20. A stacked gate transistor 22 includes a source being the central terminal 18, a P- channel 24, a drain 26 coupled to a bit line ground (BLG) 28, a floating gate (FG) 30, and a program gate (PG) 32. The word select transistor 10 and stacked gate transistor 22 form a series circuit between the BL 14 and BLG 28. The control gate 20 is coupled to a word line (WL) 36 and PG 32 is coupled to PG line (PGL) 38. A tunneling structure 34 includes a thin tunnelling dielectric region that allows electrons to tunnel between the central terminal 18 and the FG 30 under appropriate voltage bias conditions.

Table 1 is a state table setting forth the voltage states for the word, PG, bit, and bit ground lines during the discharge, charge, and read operations.

TABLE 1 WL PGL BL BLG

Discharge +20 0 +20 Open

Charge +20 +20 0 Open

Read + 5 + 1.1 + 1.5 0

The charge, discharge, read, and write operation for the cell 8 will now be described with reference to Table 1 and Fig. 1. During the discharge operation both the word line 36 and BL 14 are set at about 20 volts. The high voltage on the word line minimizes the resistance of the P- channel 16 of the word select transistor 10 and assures that the central terminal 18 raise to about 20 volts. The BLG 38 is open so that the bit ground N+ terminal 26 is floating with respect to the voltage supply, thereby allowing no current to flow through the BLG 28. The central terminal 18 may thus be fully raised to the about 20-volt level to discharge the floating gate 30. The program gate 32 disposed over the floating polysilicon gate 30 is biased at zero volts. Thus, electrons in the polysilicon gate 30 are induced to tunnel through the tunneling region 34 into the central terminal 18 and the floating polysilicon gate 30 is discharged. If the polysilicon gate 30 were discharged before commencing the erase operation, then it would remain in the discharged condition.

During the charge cycle the BL 14 is grounded at zero volts and the WL 36 is again charged to twenty volts to reduce the resistance of the first channel region 16 and assure that the central terminal 18 is grounded. The PGL 30 is biased to twenty volts, thereby biasing the floating gate 30 to a high voltage (approximately +15 volts) due to the capacitive coupling between the PG 32 and the floating polysilicon gate 30. Electrons tunnel from the central terminal 18 through the tunneling region 34 into the polysilicon gate 30.

During a read operation the WL 36 is biased to +5 volts and the BLG 28 is grounded. The WL 36 is biased so that the word select transistor 10 is on and conducts while the PGL 30 is biased so that the stacked gate transistor 22 conducts if the floating polysilicon gate 30 is discharged and does not conduct if the floating polysilicon gate 30 is charged. Thus, current will flow from the BL 12 to the BLG 28 if the polysilicon gate 30 is discharged (logic 0 state) and will not flow if the polysilicon gate 30 is charged (logic 1 state). During a write operation the cell 8 is first programmed so that the floating polysilicon gate 30 is charged and the cell is in a logic 1 state. If a logic 1 is to be stored in the cell, the floating polysilicon gate 30 is then programmed so that the floating polysilicon gate 30 is discharged.

The cell 8 is formed by diffusing the bit line, central terminal, and bit ground N+ regions 12,

18, and 26 into the P- substrate by standard photolithographic processes. An oxide layer is then deposited over the surface of the P- substrate and the N+ regions. This oxide layer includes a thin dielectric tunneling region formed by methods well-known in the art. The polysilicon WL and PGL lines 36, 38, metal BL and BLG 14, 28 and insulating oxide layers are also formed by standard methods well known in the art.

Fig. 2 is a schematic diagram depicting the overall architectural layout of the present invention. In Fig. 2, thirty-two bytes 40, each containing eight bits, are disposed along a selected WL 36. Each byte is coupled to, a data bus 42 comprising eight data lines 44 by applying a voltage signal to a Y_n terminal 46 where Y_n couples the nth byte to the data bus 42. Typically, the array will include two hundred and fifty-six WLs 36 so that there will be two hundred and fifty-six pages in the E²PROM array. Any page in the array is selected by providing the appropriate WL address (usually denoted the X address) while any particular byte in a page is selected by providing the array with a Y address which selects the appropriate Y_n terminal 46. Each byte has associated with it a set of byte latches 48 which are active latches having the respective bit lines 14 in the byte 40 coupled to a node in the latch 48. Each byte includes a PG line 38 coupled to a V_PG line 50 included in the data bus 42. The Y_n terminal 46 also controls the coupling of each PGL 38 to the V_PG line 50.

Fig. 3 is a detailed schematic diagram of the nth bite of the mth page of the E²PROM array. In Fig. 3, the mth page is disposed along WL 36 and the nth byte is accessed by terminal Y 46. The byte includes eight E²PROM memory cells 8, each connected between a respective vertical BL 14 and a vertical BLG 28. The byte also includes a PG line 38 oriented parallel to the BLs 14.

Each BL 14 includes a first terminal 14A connected to a terminal of a bit line access transistor (T_DL) 60 with the second terminal of the bit line access transistor connected to a data line 44 in the data bus

42 corresponding to the respective BL 14. The gates of all the T_DLs 60 in the byte are connected to the Y_n terminal 46. A second terminal of the bit line 14B is connected to an I/O port of a bit line pump 62. The bit line pump 62 has a second input connected to a V_PP2 terminal 64. The second terminal 14B of each bit line 14, is also connected to a bit line discharge transistor (T_BLD) 66 with a second terminal of T_BLD 66 connected to ground. The gates of the T_BLDs 66 in the byte are connected to a PL line 68.

The PG line 38 has a first terminal 38A connected to a first terminal of a PGL access transistor (T_VPG) 70 with the second terminal of T_VPG 70 connected to the V_PG line 50 and with the gate of the T_VPG 70 connected to the Y_n terminal 46. A second terminal 38B of PGL 38 is connected to the I/O port of a PG pump 72.

A second port of the PG pump 72 is connected to a Y_PP1 terminal 74. A first node 76 of the PG line is connected to a first terminal of a PG discharge transistor (T_PGD)

78 with the second terminal of T_PGD 78 connected to ground and the gate of T_PGD 78 connected to a PLPG line

80. A second node 82 on PGL 38 is connected to the first terminal of a program transistor 84 having its second terminal connected to the program gates 32 of the E²PROM memory cells 8 in the byte and having its gate connected to the word line 36. The BLGs 28 have a first terminal 28A connecte to a terminal of a bit line ground transistor (T_BLG) 86 with the second terminal of T_BLG 86 connected to ground and with the gate of T_BLG 86 connected to an SA line 88. Each bit line latch 48 has a first terminal

48A connected to a BLL 90. The bit line latch 48 includes first, second, and third transistors (T₁, T₂, and T₃) 91, 92, and 93 where T₁ is an NMOS depletion mode transistor and T₂ and T₃ are NMOS enhancement mode transistors. T₁ is connected between the input terminal 48A and a node A 94 with the gate of T₁ connected to node A so that T₁ functions as a depletion load transistor. T₂ is connected between Node A 94 and ground with the gate of T₂ connected to node B 95 of the latch 48. The BL 14 is also connected to node B 95 of the latch 48. T₃, is connected between the bit line 14 and ground with the gate of T₃ connected to node A 94.

The PGL latch 96 is structurally identical to the bit line latch 48 with the substitution of the PGL 38 for the BL 14.

A brief overview of the functioning of the system will now be presented with reference to Fig. 3. In the following discussion, the voltages on the various control lines will be clocked either high or low where in general the high voltage is equal to 5 volts and the low voltage is equal to 0 volts or ground. Any voltage level not equal to one of these values will be specified independently if important to the function of the invention. It is assumed in the following discussion that a particular page in the memory array has been selected by providing a set of address bits to an X decoder and selecting a particular word line, e.g. WL_m . The bytes in the page are loaded in independent cycles. During a given byte load cycle the data to be loaded into the byte is clocked onto the data lines as a series of voltage states on the data lines 44 in the data bus 42. Since there are only eight data lines 44 only eight bits of information may be loaded during a single cycle. A particular byte in the page is selected by providing a set of Y address bits to the Y decoder to activate the Y_n terminal 46. If an entire page is to be written in one write cycle, thirty-two byte load cycles must be completed before the page write operation is implemented. As described above, the user may extend the load cycle indefinitely by toggling the signal to prevent the preset time interval from timing out.

The page mode write operation is divided into a load cycle and a write cycle. The write cycle is further divided into a charge subcycle and a discharge subcycle.

The following steps are followed to load eight bits of data into the nth byte of the mth page. First, the BLs 14 and PGL 38 of the byte are grounded so that PGL 38 in all the BLs 14 are pulled low. Subsequently, the data is clocked onto the data bus 42 and the V_PG line is clocked high while the Y_n terminal is also clocked high to activate the access transistors 60 and 70. Once the access transistors are activated, PGL 38 is coupled to the V_PG line 50 and the BLs 14 are coupled to respective data lines 44 in the data bus 42. The BL latches 48 and PGL latch 96 are powered up by BLL 90 to actively latch the BLs 14 to the data states on the corresponding data lines 44 and the PGL to the state of the V_PG line 50. The term "active latch" as used herein refers to a latch that couples a low BL 14 to ground independently of any external clocking system. Y_n terminal is then clocked low to decouple PGL 38 and the BLs 14 from the data bus 42.

The PGL 38 and BLs 14 in the nth byte will remain latched at these data values until the write cycle is begun. If the data in the nth byte is to be changed the above-described steps are repeated so that the new data is latched into the byte. The load operation does not affect the data stored in the memory cells 8 since the voltages on the BLs 14 and program gates 32 are not of sufficient magnitude to charge or discharge the floating gates 30 of the memory cells 8. The charge subcycle begins a fixed time period after the last leading rising edge of the signal. If the PGL 38 is latched high, then it is pulled to about 20 volts to pull all the program gates 32 of the memory cells in the byte to about 20 volts. The word line 36 is also pulled to about 20 volts to couple the central terminal 18 of each memory cell to its corresponding BL 14. Those memory cells coupled to low BLs 14 will have their floating gates fully charged due to the about 20 volt difference between the central terminal 18 and the program gate 32. Those memory cells coupled to high BLs 14 will have their floating gates 30 only partially charged since the voltage differential between the program gate 32 and the central terminal 18 is less than about 20 volts. Accordingly, at the end of the charge cycle all the floating gates 30 in the byte are either fully or partially charged. The discharge subcycle begins after the charge cycle has been completed. The PG line 38 and, correspondingly, all the program gates 32 are pulled low. The high BLs 14 are then pulled to about 20 volts while the low BLs 14 remain low. Accordingly, an about 20 volt differential between the program gates and high

BLs 14 is developed that discharges the floating gates 30 of the memory cells 8 coupled to the high BLs 14. On the other hand, no voltage drop is developed between the program gate 32 and central terminal 18 of the memor cells 8 connected to low BLs 14 and thus the floating gates 30 of those memory cells remain charged.

In view of the above, it is apparent that, at the end of the write cycle, the E²PROM memory cells in the byte have been reprogrammed with the new data latche onto the BLs 14 during the load cycle. Only those bytes in the page that require data updates will be loaded prior to the write cycle. Those bytes not requiring data updates will not be loaded and will have their PGL 38 and BLs 14 all in the low voltage state due to the initial clearing utilizing the PLPG line 80 and PL line 68. As described more fully below, bytes having the PGL 38 and all BLs 14 clocked low do not undergo a charge/discharge cycle during the write operation. Accordingly, the present invention allows data to be written into a given set of bytes in the page while preventing those bytes not in the given set from undergoing a charge/discharge cycle. For a 32 byte page the size of the given set may range from a single byte to the full 32 bytes.

A more detailed description of the load and write cycles will now be presented with reference to Fig. 3 and Fig. 4. Fig. 4 is a timing diagram depicting the states on the various control lines at different times during the load and write cycle.

Turning first to the load cycle, the load cycle is initiated, with CE low by pulling WE low. At this time Y_DIS goes high to deactivate the access transistors 60 and 70 and the one shot PGL and PL clocks go high to activate T_pGD 78 and T_BLD 66, thereby pulling PGL 38 and BLs 14 low. If data is to be loaded into the nth bit then V_PG 50 is clocked high and the data to be loaded is clocked onto data lines 44. Y_DIS then goes low and Y_n 46 is pulled high to activate access transistors 60 and 70. Correspondingly, BLL 90 is clocked high to power up the latches 48 and 96.

The functioning of the BL latch 48 will now be described with reference to Fig. 3. When BLL 90 is high, current flows through T, and charges node A 94. If BL₀ 14 is low, then node B 95 is low and transistor T₂ is off. Accordingly, node A is charged positively and T₃ is activated, thus coupling BL₀ 14 to ground. Thus, a low BL₀ 14 is latched to ground by the BL latch 48.

On the other hand, if BL₀ 14 is high, node B 95 is high and transistor T₂ is activated, thereby discharging node A and deactivating T₃. Accordingly, BL₀ 14 is isolated from ground and the action of the BL pump 62 connected to V_PP2 terminal 64 maintains the BL₀ 14 at five volts. It is important to note that the BL latch 48 is active, i.e., it will latch the BL 14 to a new state independent of any external clocking. For example, if BL₀ 14 was switched from low to high in a subsequent load cycle, node B would turn on T₂ thereby discharging node A and in turn deactivating T₃ to isolat BL₀ 14 from ground and latch BL₀ 14 to five volts via the BL pump 62.

Accordingly, the data in a byte may be changed during the load cycle at any time selected by the user and thus the load cycle provides for flexible data chang ing. During the load cycle, the SA line 88 is pulled low to deactivate the BL ground transistors 86 and decouple the BLGs 28 from ground. Thus, all the BLGs 28 in the byte are electrically independent during the load cycle. This independence facilitates the latching of the load data onto the BLs 14 for the reasons set forth below. In most E²PROM arrays the BLGs 28 in the byte are coupled together. This coupling results in a lack of independence between the various E²PROM cells. For example, assume that BLG₀ and BLG₇ are coupled together, that the floating gate 30 in the 0th memory cell 8 and the seventh memory cell 8 are discharged so that the stacked gate transistors 22 conduct. During the load cycle the program gates 32 are high and WL 36 is high, so that a closed circuit is formed between BL₀ and BL₇ via the access transistor and the stacked gate transistor of the 0th memory cell 8, through BLG₀ 14 via the coupling to BLG₇, through the stacked gate transistor and access transistor of the 7th memory cell to BL₇. Accordingly, if BL₀ were latched low and BL₇ were latched high, this closed circuit would cause the states of BL₀ and BL₇ to assume some intermediate voltage level between 0 and 5 volts, thereby preventing the active latching of the data onto the BLs 14. The charge subcycle of the write cycle will now be described. If remains high for a preset time interval, then clock T times the charge and discharge subcycles. The user may extend the duration of the load cycle indefinitely by toggling the

signal low before the preset time interval elapses. The time interval may be clocked by a counter (not shown) that is started when WE is clocked high and is reset when

is clocked low.

During the charge subcycle, V_PPl is pulled to twenty volts. The PG pump is designed so that if PGL 38 is high, then the PG pump will pump PGL 38 to about 20 volts. However, if PGL 38 is low, then PGL will remain low. Turning now to the case where PGL is high, the twenty volts on PGL 38 is coupled to the program gates 32 of all the memory cells 8 in the byte. Additionally, the word line 36 is pulled high to couple the central terminal of the cell to the respective BLs 14. As described above, the floating gates 30 in memory cells 8 connected to low BLs 14 will be fully charged while the floating gates 30 in memory cells 8 connected to high BLs 14 will be partially charged.

At the end of the charge cycle V_PP1 goes back to 5 volts and PLPG 80 is clocked high to pull PGL 38 low. At this point all the floating gates in the memory cells of the byte are either charged or partially charged, depending on whether their associated BLs 14 were low or high.

During the discharge cycle, V_PP2 is pulled to about 20 volts and the BLs 14 latched high are pumped to about 20 volts by the BL pump 62. Those BLs 14 latched low will remain low during the discharge cycle. The word line 36 is pulled to about 20 volts to couple the central terminal 18 of the memory cells 8 to the BLs 14 so that the central terminal 18 of the high BLs 14 is pulled to about 20 volts and the central terminal 18 coupled to the BLs 14 remains low. The program gates 32 are grounded via the PGL 38 and thus a 20 volt difference is developed between the program gate and central terminal 18 for those cells connected to BLs 14 latched high. Accordingly, those floating gates are discharged while the floating gates 30 in memory cells 8 connected to low BLs 14 remain charged. Thus, at the end of the write cycle, the floating gates 30 in memory cells 8 coupled to low BLs 14 are charged while the floating gates 30 of memory cells 8 coupled to high BLs 14 are discharged. The write operation occurs simultaneously for all bytes in the bit and accordingly an entire page is written in parallel into the memory. Note that for a low PGL 38 and low BLs 14 the PG pump and BL pumps, 72 and 62 respectively, did not pump the PGL and BLs 38 and 14 up to about 20 volts during the write cycle. The latches 96 and 48 and pumps 72 and 62 cooperate to maintain low

PGLs and BLs 38 and 14 at ground during the entire write cycle. Bytes having the PGL 38 and BLs 14 all latched low do not go through a charge and discharge cycle during the write cycle because the low PGL 38 and BLs 14 are not affected by the write cycle. Accordingly, the endurance of E²PROM memory cell array is increased.

The functioning of the PG pump 72 and BL pump 62 will now be described with reference to Fig. 5. In Fig. 5 a BL pump 62 is depicted, however, it is to be understood that the functioning of the PG pump 72 is identical. Referring now to Fig. 6, the I/O port of the BL pump 62 is connected to the second terminal 14B of the BL 14. A second terminal of the pump 62 is connected to V_PP2 64. The pump circuit includes first and second transistors (Q₁ and Q₂ ) 100 and 102 and a capacitor C₁ 104. A BL pump input is connected to a clock input 106. The terminals of transistor Q₁ 100 connect the

V_PP2 terminal 64 to a charging node 108. If the voltage at the BL 14 terminal is latched low, then transistor Q₁ 100 is inactivated and the charging node 108 is isolated from the V_PP2 terminal 64. Accordingly, BLs 14 latched low deactivate the BL pump 62 and remain grounded when

V_PP2 is pulled to about 20 volts. The BL pump 62 may be replaced by other active pull-up means such as a resistor coupled to the V_PP2 terminal 64 by a transistor activated by clocking the BL high. The above description is presented by way of example, not limitation. For example, changes in the voltage states, timing, circuitry of the latches, and physical layout of the array described above could be made by persons of ordinary skill in the art within the scope of the invention. In particular, the latches, pump circuitry, and other circuitry peripheral to the underlying E²PROM memory cell array has been described as NMOS circuitry. It is known in the art to design equivalent circuitry in PMOS, CMOS, bipolar, and other circuitry technologies. Such substitution is included within the scope of the present invention which is defined by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A system for writing data into a page of an E²PROM memory array with each page including N bytes and with each byte including k E²PROM cells connected to k bit lines, N and k being integers, said system comprising: means for selecting a given set of bytes in the page; means for actively latching data onto the bit lines of said given set of bytes; and means for writing the data latched onto said bit lines into the E²PROM memory cells connected to said bit lines of said given set of bytes, where the number of bytes in said given set ranges from 1 byte to

N bytes.

2. The invention of claim 1 wherein said means for latching comprises: means for electrically isolating the E²PROM memory cells in a byte.

3. The invention of claim 2 wherein said means for actively latching comprises: a bit line latch, having a given bit line in a byte coupled to a node of said latch, for actively connecting said given bit line to ground when said given bit line is in a low voltage state.

4. The invention of claim 3 wherein said means for electrically isolating comprises: k bit line grounds, each connected to one of the E²PROM memory cells in the byte and with each bit line ground in the byte electrically isolated from all other bit line grounds in the byte; and means for selectively coupling the bit line grounds in the byte to ground.

5. The invention of claim 4 wherein said means for writing comprises: a program gate (PG) line selectively connected to the program gates of the E²PROM cells in a byte; and means for latching said PG line to a selected voltage state.

6. The invention of claim 5 wherein said means for latching said bit lines further comprises: means for pulling a bit line not actively latched to ground to a high voltage state.

7. The invention of claim 6 wherein said means for writing comprises: means for pulling a bit line not actively latched to ground to about 20 volts to discharge the ffllooaatting gate m the E²PROM cell coupled to said bit line.

8. The invention of claim 7 wherein said means for writing further comprises: means for pulling said PG line to a high voltage state when said PG line is not actively latched to ground .

9. The invention of claim 8 wherein said means for writing further comprises: means for pulling said PG line to about 20 volts when said PG line is not actively coupled to ground to charge or partially charge the floating gates of the E²PROM memory cells in the byte.

10. A byte in a system for writing data into a page of an E²PROM memory cell, with said page including N bytes, and with said system of the type having a data bus including a V_PG line and k data lines, where N and k are positive integers, said byte in said system comprising: k parallel bit lines; k bit line grounds oriented parallel to said bit lines, with each of said bit line grounds being electrically isolated from all other bit ground lines in the byte; k E²PROM memory cells interconnected between one of said bit lines and a respective one of said bit- line grounds; a program gate (PG) line; a BLL line; bit line ground coupling means for selectively connecting each of said bit line grounds to groun a bit line latch, having a first terminal coupled to said BLL line and having one of said bit lines coupled to a node of said latch with said latch for actively connecting said coupled bit line to ground when said coupled bit line is in a low voltage state; a PG line latch having a first terminal coupled to said BLL line and having said PG line coupled to a node of said PG latch with said latch for actively connecting said PG line to ground when said PG line is in a low voltage state; means for pulling a bit line to a high voltage state when said bit line is not latched to ground; means for pulling said PG line to a high voltage state when said PG line is not latched to ground bit line data access means for selectively coupling each of said bit lines to a respective one of the data lines of said data bus;

PG line state access means for selectively coupling said PG line to the V_PG line in said data bus; and PG access means for selectively coupling said PG line to the program gates of the memory cells in the given byte.

11. The invention of claim 10 wherein said means for pulling said bit line high comprises: a pump circuit coupled to said bit line.

12. The invention of claim 11 wherein said bit line latch comprises: a circuit including a plurality of transistors.

13. The invention of claim 12 where said bit line latch is a circuit having a first circuit node, where said circuit comprises: a first MOS depletion mode transistor having a first terminal coupled to said BLL line, a second terminal -coupled to the first circuit note, and a gate coupled to the first circuit node; a second MOS enhancement mode transistor having a first terminal coupled to the first circuit node, a second terminal coupled to ground, and a gate coupled to a given one of said bit lines; and a third MOS enhancement mode transistor having a first terminal coupled to said given bit line, a second terminal coupled to ground, and a gate coupled to the first circuit node, where said latch couples said given bit line to ground when said given bit line is in the low voltage state.

14. A method for writing data into a page of an E²PROM memory array, with each page of the type ineluding N bytes, with k E²PROM cells and bit lines (BLs) per byte, where N and k are positive integers, said method comprising the steps of: selecting a given byte in said page; loading data onto the BLs of said selected byte; and writing said loaded data into the E²PROM cells of the selected byte.

15. The method of claim 14 wherein said step of loading further comprises the steps of: clocking data, in the form of high and low voltage states, onto the BLs of said selected byte; actively latching BLs clocked low to a low voltage state; and actively maintaining BLs clocked high in a high voltage state.

16. The method of claim 15 further comprising the steps of: determining whether a given byte does not require new data; and preventing the memory cells in said given byte from undergoing a charge/discharge cycle during a page mode write.

17. A system for writing data into a page of an E²PROM memory array, with each page of the type including N bytes, with k E²PROM cells and bit (BLs) per byte, where N and k are positive integers, said system comprising: means for selecting a given byte in said page; means for loading data onto the BLs of said selected byte; and means for writing said loaded data into the E²PROM cells of the selected byte.

18. The system of claim 17 wherein said means for loading comprises: means for clocking data, in the form of high and low voltage states, onto the BLs of said selected byte; means for actively latching BLs clocked low to a low voltage state; and means for actively maintaining BLs clock high in a high voltage state.

19. The system of claim 18 further comprisin means for determining whether a given byte does not require new data; and means for preventing the memory cells said given byte from undergoing a charge/discharge cycle during a page mode write.

20. A system for writing data into a page of an E²PROM memory array of the type having N bytes per page and k bit lines per byte, N and k being integers, said system comprising: means for loading data onto the bit line of selected bytes in the page during a load cycle; means for accepting an externally supplied signal having first and second states; means for clocking a predetermined time interval; means for starting the clocking of an entire predetermined time interval when said external signal is toggled from said first state to said second state; means for resetting said clocking means when said external signal is toggled from said second state to said first state; and means for terminating said load cycle when said means for clocking completes the clocking of said predetermined time interval.

21. A system for writing data into a page of an E²PROM memory array with each page including N bytes and with each byte including k E²PROM cells connected to k bit lines, N and k being integers, said system comprising: means for selecting a given set of bytes in the page; means for actively latching data onto the bit lines of said given set of bytes; means for writing the data latched onto said bit lines into the E²PROM memory cells connected to said bit lines of said given set of bytes, where the number of bytes in said given set ranges from 1 byte to N bytes; and means for preventing bytes in the page not in the given set from undergoing a charge/discharge cycle when data is written into bytes in the given set.