EP0191459A2 - Circuit de mise en forme d'onde - Google Patents

Circuit de mise en forme d'onde Download PDF

Info

Publication number
EP0191459A2
EP0191459A2 EP86101715A EP86101715A EP0191459A2 EP 0191459 A2 EP0191459 A2 EP 0191459A2 EP 86101715 A EP86101715 A EP 86101715A EP 86101715 A EP86101715 A EP 86101715A EP 0191459 A2 EP0191459 A2 EP 0191459A2
Authority
EP
European Patent Office
Prior art keywords
digital
read
output
terminals
address control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86101715A
Other languages
German (de)
English (en)
Other versions
EP0191459A3 (fr
Inventor
Yuichi Kojima
Yoshiyuki Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of EP0191459A2 publication Critical patent/EP0191459A2/fr
Publication of EP0191459A3 publication Critical patent/EP0191459A3/fr
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
    • H04L25/03834—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using pulse shaping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/03—Digital function generators working, at least partly, by table look-up
    • G06F1/035—Reduction of table size
    • G06F1/0356—Reduction of table size by using two or more smaller tables, e.g. addressed by parts of the argument

Definitions

  • the present invention relates generally to a waveform shaping circuit and more particularly to a waveform shaping circuit for use with a digital signal transmission apparatus of a digital communication system.
  • a prior art digital signal transmission apparatus of a digital communication system is generally constructed as shown in Fig. 1.
  • the digital signal from a signal source 1 is supplied through a waveform shaping circuit 2 to a modulator 3.
  • the modulated signal from the modulator 3 is supplied through a transmission line 4 to a demodulator 5 provided on a receiving side.
  • the demodulated signal from the demodulator 5 is supplied through a slicer 6 to an output terminal 7.
  • the inter symbol interference and interference between adjacent channels must be minimized.
  • the waveform shaping circuit 2 in Fig. 1 is constructed by such a binary transversal filter as shown in Fig. 2. Since this binary transversal filter can be designed in a direct time region, it is expected that the circuit can be made high in precision.
  • reference numeral 8 designates a data input terminal to which a digital data signal to be transmitted is applied.
  • Reference numerals 9a, 9b, ... 9h respectively designate flip-flop circuits which constitute a shift register 9 which is supplied with the digital data signal from the data input terminal 8.
  • reference numeral 10 designates a clock input terminal to which a clock signal having the frequency twice as high as a data transfer rate is applied. The clock signal applied to this clock signal input terminal 10 is supplied to the flip-flop circuits 9a, 9b, ... 9h constituting the shift register 9 as a shift signal.
  • Reference numerals lla, lib, ... llh respectively designate resistors which construct a weighting circuit.
  • Reference numeral 12 designates an output terminal.
  • the shift register 9 supplied with the input data signal is operated at the clock signal having the frequency twice as high as the data transfer rate and the output signals from the respective flip-flop circuits 9a, 9b, ... 9h which constitute the shift register 9 are weighted by the resistance values of the weighting resistors lla, llb, -... llh. Since this binary transversal filter uses the resistors lla, llb, ... llh as the weighting circuits, when it is intended to increase the accuracy in waveform-shaping, . a fine adjusting circuit must be provided for each tap or stage of the shift register. Further, this binary transversal filter has a defect that it will be directly affected by the logical amplitude fluctuation of the output from the shift register 9.
  • a waveform shaping circuit is proposed that instead of the resistors lla, llb, ... llh constituting the weighting circuit, there are provided a ROM (read only memory) 13 and a D/A (digital-to-analog) converting circuit 14 as shown in Fig. 3.
  • a ROM read only memory
  • D/A digital-to-analog
  • 8 output terminals of the shift register 9 formed of 8 flip-flop circuits 9a, 9b, ... 9h are respectively connected to address control terminals of the ROM 13 having the address control terminals, the number thereof being corresponding to the number of the output terminals.
  • the ROM 13 generates a data corresponding to the input pattern to the ROM 13 as the 8-bit digital value.
  • the 8-bit digital output signal from the ROM 13 is supplied to the D/A converting circuit 14 and also a clock signal from an input terminal 10 is supplied to the D/A converting circuit 14.
  • the output side of this D/A converting circuit 14 is connected to an output terminal 12.
  • Other circuit elements are formed the same as those of Fi g. 2. In the example shown in Fig.
  • the weighting of each tap of the shift register 9 is prepared as the table, the value corresponding to the input pattern of the data signal is generated as the digital value and this digital value is converted to the desired analog waveform by the D/A converting circuit 14, there is an advantage that it is possible to remove such the defect that the resistor is used as the weighting circuit.
  • a waveform shaping circuit is proposed as shown in Fig. 4.
  • the data signal applied to the data input terminal 8 is supplied to a plurality of shift registers, for example, two shift registers 9 1 and 9 2 each formed of a predetermined stage, for example, 4 stages of flip-flop circuits 9a, 9b, 9c and 9d and having predetermined stages.
  • 4 output terminals of each of these two shift registers 9 1 and 9 2 are respectively connected to address control terminals of two weighting ROMs 13 1 and 13 2 , the number of address control terminals of each of which is made corresponding to the number of the output terminals.
  • a clock signal Pl having the frequency twice as high as the data transfer rate, which is applied to the clock input terminal 10, is supplied to a 1 ⁇ 2 frequency divider 15.
  • a clock signal P2 having the frequency equal to the data transfer rate and generated at the output of the h frequency divider 15 is supplied to each of the flip-flop circuits 9a, 9b, 9c and 9d of the shift register 9 1 as a shift signal.
  • this clock signal P2 is supplied through a ⁇ phase shifter 16, which shifts the phase of the clock signal P2 by ⁇ , to the respective flip-flop circuits 9a, 9b, 9c and 9d forming the shift register 9 2 as a shift signal.
  • 8-bit output signals from the ROMs 13 1 and 13 2 are respectively supplied to D/A converting circuits 14 1 and 14 2 and the clock signal P1 from the clock input terminal 10 is supplied to these A/D converting circuits 14 1 and 14 2 . Then, analog output signals from the D/A converting circuits 14 1 and 14 2 are added together and then fed to an output terminal 12.
  • the shift register 9 1 is driven by using the clock signal P2 having the frequency equal to the data transfer rate and the shift register 9 2 is driven by the clock signal which results from phase-shifting the clock signal P2 by ⁇ by the 7 phase shifter 16
  • the shift registers 9 1 and 9 2 are equivalently driven by the clock signal having the frequency twice as high as the data transfer rate.
  • a waveform shaping circuit for use with a digital signal transmission apparatus comprising:
  • a digital data signal to be transmitted and applied to the data input terminal 8 is supplied to the shift register 9 formed of, for example, 8 flip-flop circuits 9a, 9b, ... 9h.
  • the 8 output terminals of this shift register 9 is divided by two, the output terminals of 4 flip-flop circuits 9a, 9b, 9c and 9d are connected to address control terminals of the first ROM 13 1 having 4 addresses; while, the- output terminals of the succeeding 4 flip-flop circuits 9e, 9f, 9g and 9h are respectively connected to the address control terminals of the second ROM 13 2 having 4 addresses.
  • the clock signal P1 having the frequency twice as high as the data transfer rate and applied to the clock input terminal 10 is supplied to the respective flip-flop circuits 9a, 9b, ... 9h which form the shift register 9.
  • the 8-bit digital output signals from the first and second ROMs 13 1 and 13 2 are both supplied to an 8-bit digital adder 17 in which they are added together.
  • the output signal from the digital adder 17 is supplied to the D/A converting circuit 14, and the output side of the D/A converting circuit 14 is connected to the output terminal 12. Also, this D/A converting circuit 14 is operated by the clock signal PI having the frequency twice as high as the data transfer rate applied to the clock input terminal 10.
  • the output signals from the plurality of ROMs 13 1 and 13 2 are added in digital manner and then converted from a digital signal to an analog signal, even if the stage number (tap number) of the shift register 9 is increased, a waveform shaping circuit having multi-stages can be realized by preparing the ROMs of a proper number and the digital adder 17.
  • the weighting circuit is formed of the plurality of ROMs 13 1 and 13 2 and the D/A converting circuit 14, it is possible to realize the waveform shaping circuit which can waveform-shape the signal with high precision.
  • the output signals from the plurality of ROMs 13 1 and 13 2 are digitally added and then converted from the digital signal to the analog signal, it is sufficient to provide the single D/A converting circuit 14 so that the apparatus can be made small in size so much.
  • Fig. 6 illustrates another embodiment of the waveform shaping circuit according to the present invention. This embodiment is a modified example in which the number of the stages of the shift register is increased more than ever.
  • Fi g . 6 like parts corresponding to those of Figs. 4 and 5 are marked with the same reference numerals and will not be described in detail.
  • the data signal applied to the data input terminal 8 is supplied to two shift registers 9 1 and 9 2 each formed of, for example, 8 flip-flop circuits 9a, 9b, ... 9h.
  • the 8 output terminals of one shift register 9 1 are divided by two, and 4 output terminals of the 4 flip-flop circuits 9a, 9b, 9c and 9d from the first one are respectively connected to the address control terminals of the first ROM 13 1 having 4 addresses; while, 4 output terminals of the succeeding 4 flip-flop circuits 9e, 9f, 9c and 9h are respectively connected to the address control terminals of the second ROM 13 2 having 4 addresses.
  • This clock signal P2 is also supplied through the ⁇ phase shifter 16, which phase-shifts the clock signal P2 by ⁇ , to the respective flip-flop circuits 9a, 9b, ... 9h of the shift register 9 2 as the shift signal.
  • the 8-bit digital output signals from the first and second ROMs 13 1 and 13 2 are both supplied to an 8-bit digital adder 17 1 in which they are added; while, the 8-bit digital output signals from the third and fourth ROMs 13 3 and 13 4 are both supplied to an 8-bit digital adder 17 2 and thereby added together.
  • the 8-bit digital output signals from the digital adders 17 1 and 17 2 are supplied to an 8-bit digital adder 18 in which they are added together.
  • the output signal from this digital adder 18 is supplied through the D/A converting circuit 14 to the output terminal 12, while this D/A converting circuit 14 is operated by the clock signal Pl having the frequency twice as high as the data transfer rate generated at the clock input terminal 10.
  • the clock signal Pl having the frequency twice as high as the data transfer rate generated at the clock input terminal 10.
  • the ROMs 13 1 and 13 2 are divided into plural ones, the output signals from the plurality of ROMs 13 1 and 13 2 are digitally added and then converted from the digital signal to the analog signal by the single D/A converter, even if the number of the stages of the shift register 9 is increased, it is possible to realize the waveform shaping circuit having the multi-stages by using a proper number of the ROMs and the digital adders.
  • the weighting circuit is formed of the plurality of ROMs 13 1 and 13 2 and the D/A converting circuit 14, it is possible to obtain the waveform shaping circuit with high precision. Further, since the output signals from the plurality of ROMs 13 1 and 13 2 are digitally added together and then converted from the digital signal to the analog signal, it is sufficient that only one D/A converter 14 is provided. Hence, the waveform shaping circuit of the present invention can be made small in size.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Manipulation Of Pulses (AREA)
EP86101715A 1985-02-13 1986-02-11 Circuit de mise en forme d'onde Withdrawn EP0191459A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60026029A JPS61186012A (ja) 1985-02-13 1985-02-13 伝送装置の波形整形回路
JP26029/85 1985-02-13

Publications (2)

Publication Number Publication Date
EP0191459A2 true EP0191459A2 (fr) 1986-08-20
EP0191459A3 EP0191459A3 (fr) 1989-05-03

Family

ID=12182276

Family Applications (1)

Application Number Title Priority Date Filing Date
EP86101715A Withdrawn EP0191459A3 (fr) 1985-02-13 1986-02-11 Circuit de mise en forme d'onde

Country Status (7)

Country Link
US (1) US4794555A (fr)
EP (1) EP0191459A3 (fr)
JP (1) JPS61186012A (fr)
KR (1) KR950005115B1 (fr)
CN (1) CN1007115B (fr)
AU (1) AU588851B2 (fr)
CA (1) CA1264824A (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6369310A (ja) * 1986-09-11 1988-03-29 Nec Corp デイジタルフイルタ
IT1227520B (it) * 1988-12-06 1991-04-12 Sgs Thomson Microelectronics Filtro digitale programmabile
JPH0710072B2 (ja) * 1989-05-18 1995-02-01 株式会社ケンウッド 角度変調回路
US5117385A (en) * 1990-03-16 1992-05-26 International Business Machines Corporation Table lookup multiplier with digital filter
JPH04270510A (ja) * 1990-12-28 1992-09-25 Advantest Corp ディジタルフィルタ及び送信機
EP1331778B1 (fr) * 1993-06-25 2005-06-01 Matsushita Electric Industrial Co., Ltd. Procédé et dispositif de mise en forme d'onde
US5379242A (en) * 1993-09-01 1995-01-03 National Semiconductor Corporation ROM filter
US20030195913A1 (en) * 2002-04-10 2003-10-16 Murphy Charles Douglas Shared multiplication for constant and adaptive digital filters
US7502980B2 (en) * 2006-08-24 2009-03-10 Advantest Corporation Signal generator, test apparatus, and circuit device
US9209912B2 (en) * 2009-11-18 2015-12-08 Silicon Laboratories Inc. Circuit devices and methods for re-clocking an input signal

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2437736A1 (fr) * 1978-09-29 1980-04-25 Siemens Ag Filtre transversal pour des signaux numeriques
EP0040088A1 (fr) * 1980-05-13 1981-11-18 Secretary of State for Industry in Her Britannic Majesty's Gov. of the United Kingdom of Great Britain and Northern Ireland Synthétiseur d'ondes au standard d'emission d'aide à l'atterrissage du type V.O.R.
GB2095067A (en) * 1981-03-12 1982-09-22 Standard Telephones Cables Ltd Digital filter arrangement
EP0078101A2 (fr) * 1981-10-27 1983-05-04 Itt Industries, Inc. Multiplieur pour former une somme de produits

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2118410A5 (fr) * 1970-12-17 1972-07-28 Ibm France
JPS52109352A (en) * 1976-03-10 1977-09-13 Hitachi Ltd Digital filter
DE2842552A1 (de) * 1978-09-29 1980-04-03 Exnii Kuznetschno Pressovogo M Antrieb fuer hydraulische spindelpressen
JPS55117322A (en) * 1979-03-02 1980-09-09 Fujitsu Ltd Binary transversal filter
US4435823A (en) * 1980-12-29 1984-03-06 Harris Corporation Adaptive equalizer capable of linear and nonlinear weighting

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2437736A1 (fr) * 1978-09-29 1980-04-25 Siemens Ag Filtre transversal pour des signaux numeriques
EP0040088A1 (fr) * 1980-05-13 1981-11-18 Secretary of State for Industry in Her Britannic Majesty's Gov. of the United Kingdom of Great Britain and Northern Ireland Synthétiseur d'ondes au standard d'emission d'aide à l'atterrissage du type V.O.R.
GB2095067A (en) * 1981-03-12 1982-09-22 Standard Telephones Cables Ltd Digital filter arrangement
EP0078101A2 (fr) * 1981-10-27 1983-05-04 Itt Industries, Inc. Multiplieur pour former une somme de produits

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PHILIPS RESEARCH REPORTS, vol. 30, no. 1, february 1975, pages 73-84, Eindhoven, NL; T.A.C.M. CLAASEN et al.: "Some considerations on the implementation of digital systems for signal processing" *

Also Published As

Publication number Publication date
AU588851B2 (en) 1989-09-28
JPS61186012A (ja) 1986-08-19
CN1007115B (zh) 1990-03-07
KR950005115B1 (ko) 1995-05-18
KR860006884A (ko) 1986-09-15
US4794555A (en) 1988-12-27
CN86100810A (zh) 1986-08-13
CA1264824A (fr) 1990-01-23
AU5323086A (en) 1986-08-21
EP0191459A3 (fr) 1989-05-03

Similar Documents

Publication Publication Date Title
EP0440187B1 (fr) Dispositif à conversion de signaux binaires d'entrée en signaux en phase et en quadrature correspondants
US5379322A (en) Baseband signal generator for digital modulator
US5369378A (en) Digital DQPSK modulator
EP0191459A2 (fr) Circuit de mise en forme d'onde
US5237324A (en) System and method for producing baseband analog modulation signals
US4646327A (en) Waveform shaping apparatus
US4008373A (en) Digital differential phase shift keyed modulator
US4812786A (en) Method and system for providing precise multi-function modulation
JP2510490B2 (ja) デイジタル変調器
JPH07114345B2 (ja) 変調装置
EP0032152A4 (fr) Modulateur a touches de decalage de frequences a 1 bit.
US4873500A (en) Phase accumulation continuous phase modulator
US7120204B2 (en) Waveform generator operable in accordance with a plurality of band limitation characteristics
EP0620667A1 (fr) Modulateur pour signaux pi/4 QPSK
US4786882A (en) Quadriphase phase modulation system
JPS5972818A (ja) トランスバ−サルフイルタ
SU1688441A1 (ru) Устройство синхронизации несущей
JPS61184914A (ja) 伝送装置の波形整形回路
JPH07193605A (ja) 多値変調回路
KR19990003657A (ko) 디지탈 필터
JPH06103033A (ja) 複数固定倍率器
JPH0738382A (ja) ディジタルフィルタ
JPH06181476A (ja) π／４シフトＱＰＳＫ変調器およびそれを用いた通信装置
JPH04280144A (ja) 帯域制限用ロールオフフィルタを用いたｐｓｋ変調用波形生成回路
JPS61287348A (ja) スクランブル回路

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB NL

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB NL

17P Request for examination filed

Effective date: 19890703

17Q First examination report despatched

Effective date: 19901221

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19920103

RIN1 Information on inventor provided before grant (corrected)

Inventor name: CHIBA, YOSHIYUKI

Inventor name: KOJIMA, YUICHI